CN100565830C - Solid encapsulation structure and manufacture method thereof - Google Patents

Solid encapsulation structure and manufacture method thereof Download PDF

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Publication number
CN100565830C
CN100565830C CN200610125646.8A CN200610125646A CN100565830C CN 100565830 C CN100565830 C CN 100565830C CN 200610125646 A CN200610125646 A CN 200610125646A CN 100565830 C CN100565830 C CN 100565830C
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China
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conductive layer
semiconduction
weld pad
hole
layer
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CN101131947A (en
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黄敏龙
王维中
郑博仁
余国宠
苏清辉
罗建文
林千琪
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Abstract

A kind of solid encapsulation structure and manufacture method thereof, this manufacture method may further comprise the steps: a semiconduction body (a) is provided; (b) form at least one blind hole on this semiconduction body; (c) form an insulating barrier on the sidewall of this blind hole; (d) form a conductive layer on this insulating barrier; (e) this conductive layer of patterning; (f) remove the part of this semiconduction body lower surface and the some of this insulating barrier, to expose the part of this conductive layer; (g) form the lower end of a scolder at this conductive layer; (h) pile up a plurality of these semiconduction bodies, and carry out reflow; And (i) the semiconduction body after cutting this and piling up, to form a plurality of solid encapsulation structures.By this, the lower end of this conductive layer and on the formed space of conductive layer of semiconduction body of scolder " insertion " below in, thereby make this conductive layer more firm, and the whole height of this solid encapsulation structure can reduce effectively after engaging with engaging of this scolder.

Description

Solid encapsulation structure and manufacture method thereof
Technical field
The present invention relates to a kind of encapsulating structure and manufacture method thereof, particularly about a kind of solid encapsulation structure and manufacture method thereof.
Background technology
Fig. 1 is the U.S.'s schematic diagram of a kind of solid encapsulation structure before reflow that the 4th, 499, No. 655 patent disclosed.This solid encapsulation structure 1 comprises a first module 10 and one second unit 20.This first module 10 comprises one first semiconduction body 11, at least one first hole 12, one first conductive layer (conductive layer), 13 and 1 first scolder (solder) 14.This first semiconduction body 11 has a first surface 111 and a second surface 112; this first surface 111 has at least one first weld pad (not shown) and one first protective layer (protection layer) 113, and this first protective layer 113 exposes this first weld pad.This first semiconduction body 11 is run through in this first hole 12.This first conductive layer 13 is positioned on the sidewall in this first hole 12, and covers this first weld pad and this first protective layer 113.This first scolder 14 is positioned at this first hole 12, and is electrically connected this first weld pad through this first conductive layer 13.These first scolder, 14 upper ends extend on the first surface 111 of this first semiconduction body 11, and its lower end extends to the below of the second surface 112 of this first semiconduction body 11.
This Unit second 20 is stacked on this first module 10.This Unit second 20 comprises one second semiconduction body 21, at least one second hole 22, one second conductive layer 23 and one second scolder 24.This second semiconduction body 21 has a first surface 211 and a second surface 212, and this first surface 211 has at least one second weld pad (not shown) and one second protective layer 213, and this second protective layer 213 exposes this second weld pad.This second semiconduction body 21 is run through in this second hole 22.This second conductive layer 23 is positioned on the sidewall in this second hole 22, and covers this second weld pad and this second protective layer 213.This second scolder 24 is positioned at this second hole 22, and this second scolder 24 sees through this second conductive layer 23 and is electrically connected this second weld pad.These second scolder, 24 upper ends extend to the top of the first surface 211 of this second semiconduction body 21, and its lower end extends to the below of the second surface 212 of this second semiconduction body 21.The lower end aligned of this second scolder 24 contacts the upper end of this first scolder 14, after reflow (reflow), makes this first module 10 and this Unit second 20 engage and becomes this solid encapsulation structure 1, as shown in Figure 2.
In this solid encapsulation structure 1, the generation type of this first scolder 14 and this second scolder 24 is that this first semiconduction body 11 and this second semiconduction body 21 are arranged on the top that a scolder is bathed (solder bath), utilize capillarity to make scolder enter this first hole 12 and second hole 22, and form this first scolder 14 and this second scolder 24.
The shortcoming of this solid encapsulation structure 1 is as follows: because this first scolder 14 and this second scolder 24 are to utilize capillarity formed, therefore its upper end and lower end are semicircle spherical (Fig. 1), thereby make this first module 10 and this Unit second 20 when aiming at joint, the difficulty that can increase aim at, and the joint between this first module 10 and this Unit second 20 and built on the sand after the reflow (reflow).In addition, the spherical scolder of these unnecessary semicircles can't reduce whole height after making that this first module 10 and this Unit second 20 engage effectively.
Therefore, be necessary to provide the solid encapsulation structure and the manufacture method thereof of a kind of innovation and tool progressive, to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of solid encapsulation structure; comprise a semiconduction body (semiconductor body) is provided; this semiconduction body has a first surface and a second surface; this first surface has an at least one weld pad and a protective layer (protection layer); this protective layer exposes this weld pad, and this manufacture method further may further comprise the steps:
(a) form the first surface of at least one blind hole at this semiconduction body;
(b) form an insulating barrier (isolation layer) on the sidewall of this blind hole;
(c) form a conductive layer (conductive layer), this conductive layer covers this weld pad, this protective layer and this insulating barrier;
(d) this conductive layer of patterning;
(e) remove the part of this semiconduction body second surface and the some of this insulating barrier, to expose the part of this conductive layer;
(f) form the lower end of a scolder at this conductive layer; And
(g) pile up a plurality of these semiconduction bodies, and carry out reflow (ref1ow).
Compared with prior art, in the present invention, because the lower end of this conductive layer exposes under the second surface of this semiconduction body, therefore in the back welding process after piling up, in the blind hole of this conductive layer lower end together with the semiconduction body of its scolder " insertion " below, thereby make that the joint of two semiconduction bodies is more firm up and down, and the whole height of this solid encapsulation structure can effectively reduce after engaging.
Another object of the present invention is to provide a kind of solid encapsulation structure, comprise a first module and Unit one second.This first module comprises: one first semiconduction body, at least one first hole, one first insulating barrier, one first conductive layer and one first scolder.
This first semiconduction body has a first surface and a second surface, and this first surface has at least one first weld pad and one first protective layer, and this first protective layer exposes this first weld pad.This first semiconduction body is run through in this first hole.This first insulating barrier is positioned on the sidewall in this first hole.This first conductive layer covers this first weld pad, this first protective layer of part and this first insulating barrier, and the lower end of this first conductive layer extends to the below of the second surface of this first semiconduction body.This first scolder is positioned at this first hole, and this first scolder sees through this first conductive layer and is electrically connected this first weld pad.
This second element stack is on this first module.This Unit second comprises one second semiconduction body, at least one second hole, one second insulating barrier and one second conductive layer.This second semiconduction body has a first surface and a second surface, and this first surface has at least one second weld pad and one second protective layer, and this second protective layer exposes this second weld pad.This second semiconduction body is run through in this second hole.This second insulating barrier is positioned on the sidewall in this second hole.This second conductive layer covers this second weld pad, this second protective layer of part and this second insulating barrier, and the lower end of this second conductive layer extends to the below of the second surface of this second semiconduction body, and contacts the upper end of this first scolder.
The present invention is further illustrated below in conjunction with accompanying drawing and embodiment.
Description of drawings
Fig. 1 is the U.S.'s schematic diagram of solid encapsulation structure before reflow that the 4th, 499, No. 655 patent disclosed;
Fig. 2 shows the U.S.'s schematic diagram of solid encapsulation structure after reflow that the 4th, 499, No. 655 patent disclosed;
Fig. 3 shows the schematic flow sheet of first embodiment of the manufacture method of solid encapsulation structure of the present invention;
Fig. 4 to Figure 15 shows each fabrication steps schematic diagram among first embodiment of manufacture method of solid encapsulation structure of the present invention;
Figure 16 shows the schematic flow sheet of second embodiment of the manufacture method of solid encapsulation structure of the present invention;
Figure 17 to Figure 18 shows part fabrication steps schematic diagram among second embodiment of manufacture method of solid encapsulation structure of the present invention; And
Figure 19 shows the cross-sectional schematic of solid encapsulation structure of the present invention.
Embodiment
Relevant detailed description of the present invention and technology contents, existing as follows with regard to accompanying drawings:
Fig. 3 is the schematic flow sheet of first embodiment of the manufacture method of solid encapsulation structure of the present invention.Cooperation to Figure 15, shows each fabrication steps schematic diagram among first embodiment of manufacture method of solid encapsulation structure of the present invention with reference to figure 4.At first, cooperate, shown in step S301, provide a semiconduction body (semiconductor body) 31 with reference to figure 3 and Fig. 4.This semiconduction body 31 can be a wafer or a chip.This semiconduction body 31 has a first surface 311 and a second surface 312, and this first surface 311 has an at least one weld pad 32 and a protective layer (protection layer) 33, and this protective layer 33 exposes this weld pad 32.
Then, cooperate, shown in step S302, form the first surface 311 of at least one blind hole 34 at this semiconduction body 31 with reference to figure 3 and Fig. 5.In the present embodiment, this blind hole 34 is positioned at the next door of this weld pad 32.Yet in other was used, this blind hole 34 can run through this weld pad 32.
Then, cooperate, shown in step S303, form an insulating barrier (isolationlayer) 35 on the sidewall of this blind hole 34 with reference to figure 3 and Fig. 6.
Then, cooperate with reference to figure 3 and Fig. 7, shown in step S304, form a conductive layer (conductive layer) 36, this conductive layer 36 covers this weld pad 32, this protective layer 33 and this insulating barrier 35.The material of this conductive layer 36 is titanium, copper, copper/titanium alloy or other metal.
Then, cooperate with reference to figure 3 and Fig. 8, shown in step S305, this conductive layer 36 of patterning.
Then, cooperate, preferably, shown in step S306, form a passivation layer (passivation layer) 37 on this conductive layer 36, with the conductive layer 36 of protecting this patterning with reference to figure 3 and Fig. 9.This passivation layer 37 can utilize any existing mode to form.In addition, be understandable that this step is a step optionally.
Then, shown in step S307, remove the part of these semiconduction body 31 second surfaces 312 and the some of this insulating barrier 35, to expose the part of this conductive layer 36.With reference to Figure 10, in the present embodiment, earlier grind this semiconduction body 31 second surfaces 312 in the mode of grinding back surface (backside grinding), trim up to the lower end of this second surface 312 with this insulating barrier 35, promptly the lower end of this insulating barrier 35 is revealed in this second surface 312.Then, the lower end of these semiconduction body 31 second surfaces 312 of etching and this insulating barrier 35 again, exposing the lower end of this conductive layer 36, this moment, the lower end of this conductive layer 36 extended to the below of the second surface 312 of this semiconduction body 31, as shown in figure 11.Yet, be understandable that, in other is used, can not use the mode of this grinding back surface, and directly process this semiconduction body 31 second surfaces 312, to expose the lower end of this conductive layer 36 with etching mode.
Then, cooperate with reference to figure 3 and Figure 12, preferably, shown in step S308, form a barrier layer (barrier layer) 38 in the lower end of this conductive layer 36, this barrier layer 38 covers the lower end of the conductive layer 36 of this exposure.This barrier layer 38 can be nickel, chromium, chromium/copper alloy or other metal.Be understandable that this step is a step optionally.
Then, cooperate, shown in step S309, form the lower end of a scolder 39 attached to this conductive layer 36 with reference to figure 3 and Figure 13.Be understandable that this scolder 39 can utilize and for example electroplate the formation of (plating) or other existing mode.
Then, cooperate with reference to figure 3 and Figure 14, shown in step S310, pile up a plurality of these semiconduction bodies 31, the scolder 39 that wherein is positioned at the semiconduction body 31 of top is aimed at the conductive layer 36 formed spaces of the semiconduction body 31 that is positioned at the below.
Then, cooperation is with reference to figure 3 and Figure 15, shown in step S311, carry out reflow (reflow) processing procedure, make the scolder 39 of the semiconduction body 31 above being positioned at be melted in the conductive layer 36 formed spaces of the semiconduction body 31 of below, therefore two semiconduction bodies 31 see through the welding of this conductive layer 36 and this scolder 39 and are bonded together up and down.At last, shown in step S312, the semiconduction body 31 after cutting this and piling up is to form a plurality of solid encapsulation structures 40.Preferably, shown in step S313, form at least one soldered ball 43 below this solid encapsulation structure 40, the scolder 39 of these conductive layer 36 lower ends of the semiconduction body 31 of below is formed this soldered ball 43 by being positioned at.Be understandable that this step is a step optionally.
Figure 16 is the schematic flow sheet of second embodiment of the manufacture method of solid encapsulation structure of the present invention.The step S401 to S409 of present embodiment and the step S301 to S309 of first embodiment are identical.Present embodiment and this first embodiment difference are: cut this semiconduction body 31 at the step S410 of present embodiment, to form a plurality of unit 41,42.Then, step S411 piles up these unit 41,42, and wherein this conductive layer 36 and this scolder 39 of two semiconduction bodies 31 are aligned with each other up and down, as shown in figure 17.At last, step S412 carries out reflow (reflow), to form a plurality of solid encapsulation structures 40, as shown in figure 18.Prepared this solid encapsulation structure 40 (Figure 18) of present embodiment is identical with prepared this solid encapsulation structure 40 (Figure 15) of this first embodiment.
Preferably, step S413 forms at least one soldered ball 43 below this solid encapsulation structure 40, and this soldered ball 43 is positioned at the lower end of this conductive layer 36 of the semiconduction body 31 of below.Be understandable that this step is a step optionally.
Figure 19 is the cross-sectional schematic of solid encapsulation structure of the present invention.The solid encapsulation structure 5 of this figure and Figure 15 and solid encapsulation structure 40 shown in Figure 180 are identical, but for convenience of explanation, similar elements is given different labels.This solid encapsulation structure 5 comprises a first module 50 and one second unit 60.This first module 50 comprises one first semiconduction body 51, at least one first hole 52, one first insulating barrier (isolationlayer) 53, one first conductive layer (conductive layer), 54 and 1 first scolder 55.
This first semiconduction body 51 is a wafer or chip, has a first surface 511 and a second surface 512, and this first surface 511 has at least one first weld pad 513 and one first protective layer 514, and this first protective layer 514 exposes this first weld pad 513.This first semiconduction body 51 is run through in this first hole 52, and in the present embodiment, this first hole 52 is positioned at the next door of this first weld pad 513.Yet in other was used, this first weld pad 513 can be run through in this first hole 52.
This first insulating barrier 53 is positioned on the sidewall in this first hole 52.This first conductive layer 54 covers this first weld pad 513, this first protective layer 514 of part and this first insulating barrier 53, and the lower end of this first conductive layer 54 is connected, and extends to the below of the second surface 512 of this first semiconduction body 51.Preferably, this first module 50 further comprises one first barrier layer (barrier layer) (not shown), covers the lower end of this first conductive layer 54.Preferably, these first conductive layer, 54 tops comprise that further a passivation layer (passivation layer) (not shown) covers this first conductive layer 54, to protect this first conductive layer 54.
This first scolder 55 is positioned at this first hole 52 and is positioned on first conductive layer 54, and this first scolder 55 sees through this first conductive layer 54 and is electrically connected this first weld pad 513.
This Unit second 60 is stacked on this first module 50.This Unit second 60 comprises one second semiconduction body 61, at least one second hole 62, one second insulating barrier (isolationlayer) 63 and one second conductive layer (conductive layer) 64.This second semiconduction body 61 is a wafer or chip; have a first surface 611 and a second surface 612; this first surface 611 has at least one second weld pad 613 and one second protective layer (protectionlayer) 614, and this second protective layer 614 exposes this second weld pad 613.This second semiconduction body 61 is run through in this second hole 62, and in the present embodiment, this second hole 62 is positioned at the next door of this second weld pad 613.Yet in other was used, this second weld pad 613 can be run through in this second hole 62.
This second insulating barrier 63 is positioned on the sidewall in this second hole 62.This second conductive layer 64 covers this second weld pad 613, this second protective layer 614 of part and this second insulating barrier 63; the lower end of this second conductive layer 64 is connected; and extend to the below of the second surface 612 of this second semiconduction body 61, and contact the upper end of this first scolder 55.Preferably, this Unit second 60 further comprises one second barrier layer (not shown), covers the lower end of this second conductive layer 64.Preferably, these second conductive layer, 64 tops comprise that further a passivation layer (not shown) covers this second conductive layer 64, to protect this second conductive layer 64.
In addition, if necessary, one second scolder (not shown) can be inserted in this second hole 62.Therefore, in the present invention, this second hole 62 can be empty or insert this second scolder in addition again.Preferably, this solid encapsulation structure 5 further comprises at least one soldered ball 43, is positioned at the lower end of this first conductive layer 54.
Compared with prior art, in the solid encapsulation structure 5 of the present invention, because the lower end of this second conductive layer 64 and on scolder 39 expose under the second surface 612 of this Unit second 60, therefore in the processing procedure of reflow, the lower end of this second conductive layer 64 and on these first conductive layer, 54 formed spaces of scolder 39 " insertion " in, and this scolder 39 is melted in these first conductive layer, 54 formed spaces and forms this first scolder 55.By this, can make that the joint between this first conductive layer 54 and this second conductive layer 64 is more firm.In addition, this first hole 52 and this second hole 62 can be designed to taper as shown in FIG., with the above-mentioned joint effect of further increase.In addition, because in this first scolder 55 of lower end " insertion " of this second conductive layer 64, the whole height of this solid encapsulation structure 5 can effectively reduce after therefore engaging.

Claims (9)

1, a kind of manufacture method of solid encapsulation structure; comprise a semiconduction body is provided; this semiconduction body has a first surface and a second surface; this first surface has an at least one weld pad and a protective layer; this protective layer exposes this weld pad, it is characterized in that: this manufacture method further may further comprise the steps:
(a) form the first surface of at least one blind hole at this semiconduction body;
(b) form an insulating barrier on the sidewall of this blind hole;
(c) form a conductive layer, this conductive layer covers this weld pad, this protective layer and this insulating barrier;
(d) this conductive layer of patterning;
(e) remove the part of this semiconduction body second surface and the some of this insulating barrier, to expose the part of this conductive layer;
(f) form the lower end of a scolder at this conductive layer;
(g) pile up a plurality of these semiconduction bodies, and carry out reflow; And
(h) the semiconduction body after cutting this and piling up is to form a plurality of solid encapsulation structures.
2, manufacture method as claimed in claim 1 is characterized in that further comprising that one forms the step of at least one soldered ball below this solid encapsulation structure.
3, manufacture method as claimed in claim 1 is characterized in that this blind hole is to be positioned at this weld pad side or to run through this weld pad.
4, manufacture method as claimed in claim 1 is characterized in that step (d) comprises further that afterwards one forms the step of a passivation layer on this conductive layer, to protect the conductive layer of this patterning.
5, manufacture method as claimed in claim 1 is characterized in that step (e) comprises further that afterwards one forms the step of a barrier layer, and this barrier layer covers the conductive layer of this exposure.
6, a kind of solid encapsulation structure comprises:
One first module comprises: one first semiconduction body, have a first surface and a second surface, and this first surface has at least one first weld pad and one first protective layer, and this first protective layer exposes this first weld pad; This first semiconduction body is run through at least one first hole; One first conductive layer covers this first weld pad and this first protective layer of part; And one first scolder, being positioned at this first hole, this first scolder sees through this first conductive layer and is electrically connected this first weld pad; And
Unit one second, be stacked on this first module, this Unit second comprises: one second semiconduction body has a first surface and a second surface, this first surface has at least one second weld pad and one second protective layer, and this second protective layer exposes this second weld pad; This second semiconduction body is run through at least one second hole; And one second conductive layer, cover this second weld pad and this second protective layer of part;
It is characterized in that: this first module further comprises one first insulating barrier, is positioned on the sidewall in this first hole; This first conductive layer covers this first insulating barrier and is positioned at this first hole, and this first conductive layer lower end is the below that is connected and stretch out the second surface of this first semiconduction body; This first scolder is positioned at first hole and is positioned on this first conductive layer;
This Unit second further comprises one second insulating barrier, is positioned on the sidewall in this second hole; This second conductive layer covers this second insulating barrier and is positioned at this second hole, and this second conductive layer lower end is the below that is connected and stretch out the second surface of this second semiconduction body, and stretches into first hole of first module and the last end in contact of first scolder.
7, the described solid encapsulation structure of claim 6 it is characterized in that this first hole is to be positioned at this first weld pad side or to run through this first weld pad, and this second hole also is to be positioned at this second weld pad side or to run through this second weld pad.
8,, it is characterized in that this first module further comprises one first passivation layer, covers this first conductive layer as claim 6 or 7 described solid encapsulation structures; This Unit second further comprises one second passivation layer, covers this second conductive layer.
9,, it is characterized in that this first module further comprises one first barrier layer, covers the lower end of this first conductive layer as claim 6 or 7 described solid encapsulation structures; This Unit second further comprises one second barrier layer, covers the lower end of this second conductive layer.
CN200610125646.8A 2006-08-25 2006-08-25 Solid encapsulation structure and manufacture method thereof Active CN100565830C (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859746B (en) * 2009-04-07 2012-06-27 宏齐科技股份有限公司 Conductive substrate structure for forming conductive channel by two-sided cutting and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8963316B2 (en) * 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859746B (en) * 2009-04-07 2012-06-27 宏齐科技股份有限公司 Conductive substrate structure for forming conductive channel by two-sided cutting and manufacturing method thereof

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