CN100562972C - 使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法 - Google Patents

使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法 Download PDF

Info

Publication number
CN100562972C
CN100562972C CNB2004800307527A CN200480030752A CN100562972C CN 100562972 C CN100562972 C CN 100562972C CN B2004800307527 A CNB2004800307527 A CN B2004800307527A CN 200480030752 A CN200480030752 A CN 200480030752A CN 100562972 C CN100562972 C CN 100562972C
Authority
CN
China
Prior art keywords
type
effect transistor
material layer
type field
lattice constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2004800307527A
Other languages
English (en)
Other versions
CN101199037A (zh
Inventor
德雷斯蒂·奇达姆巴拉奥
奥默·多库马西
陈华杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101199037A publication Critical patent/CN101199037A/zh
Application granted granted Critical
Publication of CN100562972C publication Critical patent/CN100562972C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

一种半导体器件和制造半导体器件的方法。所述半导体器件包括pFET和nFET的沟道。在pFET沟道的源极和漏极区中选择性地生长SiGe层，且在nFET沟道的源极和漏极区中选择性地生长Si:C层。SiGe和Si:C层匹配下面的Si层的晶格网络以产生应力分量。在一个实施例中，这导致在pFET沟道中的压应力分量和在nFET沟道中的拉应力分量。

Description

使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法
技术领域
本发明总体涉及一种半导体器件及制造方法，更具体而言，涉及一种半导体器件及制造方法，其在器件制造过程中在器件中施加拉应力和压应力。
背景技术
半导体器件衬底内的机械应力可以调节器件性能。即，已知半导体器件内的应力提高了半导体器件的特性。因此，为了改善半导体器件的特性，在n型器件(例如，NFET)和/或p型器件(例如，PFET)的沟道中产生了拉应力和/或压应力。然而，相同的应力分量，无论是拉应力或是压应力，有差别地影响n型器件和p型器件的特性。
例如，公知当器件形成于硅层(或盖)上，且该硅层(或盖)外延生长在另一外延生长的SiGe层上，且SiGe层在硅衬底的顶部上应力松弛时，器件表现出更好的性能特性。在该系统中，硅盖经历了双轴拉应变。当未松弛的SiGe层外延生长于硅上时，其将具有与硅衬底一致的晶格常数。在(通过例如高温工艺)松弛之后，SiGe晶格常数接近其本征晶格常数，该本征晶格常数大于硅的晶格常数。完全松弛的SiGe层具有接近其本征值的晶格常数。当在其上外延生长硅层时，硅层与松弛的SiGe层的较大晶格常数一致，且这对于形成于其上的硅层施加了物理双轴应力(例如，扩张)。该施加到硅层的物理应力是有利于形成于其上的器件(例如，CMOS器件)的，因为扩张的硅层增强了N型器件性能，且SiGe层中较高的Ge浓度改善了P型器件性能。
硅衬底上的SiGe中的松弛通过形成错配位错来产生。对于完全松弛的衬底，可以设想有等距分开的错配位错的网格，其松弛了应力。错配位错通过在衬底中提供了额外的硅半平面从而促进了SiGe层中的晶格常数趋向其本征值。然后，调节SiGe/硅界面之间的失配应力，且SiGe晶格常数被允许变大。
然而，该常规方法的问题在于其需要非常厚(例如，大致
Figure C20048003075200061
到
Figure C20048003075200062
的厚度)的多层SiGe缓冲层以在其表面部分实现错配位错，同时需要避免SiGe层和硅衬底层之间的螺位错，由此在多层SiGe层的表面上实现松弛的SiGe结构。而且，该方法显著增加了制造时间和成本。另外，厚的分层SiGe缓冲层不能容易地应用于绝缘体上硅衬底(SOI)。这是因为对于绝缘体上硅，为了SOI有效的益处，硅厚度必须小于
Figure C20048003075200063
SiGe缓冲层晶格太厚了。
另一问题在于形成于SiGe层和硅外延层之间的错配位错是随机的且是高度不均匀的，且由于异相成核不能被容易地控制，所以错配位错不能被容易地控制。而且，错配位错密度从一个位置到另一位置显著不同。因此，从非均匀的错配位错引起的物理应力趋于在硅外延层中也高度不均匀，且该不均匀应力导致了具有更大可变性的对于性能的不均匀益处。另外，在错配密度高的那些位置，所述缺陷通过短路器件端子和通过其它显著的泄漏机制从而降低了器件性能。
此外，已知在固有具有拉应力的Si上外延生长Si:C。Si:C/Si材料叠层中1％的C含量可以导致在Si:C中500MPa量级的拉应力水平。比较而言，在SiGe/Si系统中，则需要约6％的Ge来导致500MPa的压应力。如Ernst等在VLSI Symp.，2002，p92中所示，可以在外延生长期间，将这1％水平的C引入Si中。在Ernst等的文献中，显示了nFET的Si/Si:C/Si层状沟道。然而，在Ernst等的文献的结构中，在常规的有应变的Si的方法中提供Si:C作为沟道中的叠层。因此，在Ernst等的文献的结构中，Si:C自身被用作部分的沟道。该方法的问题在于迁移率没有被提高，反而根据C含量由散射而被阻碍了。
发明内容
在本发明的第一方面，一种制造半导体结构的方法包括：在衬底中形成p型场效应晶体管(pFET)沟道和n型场效应晶体管(nFET)沟道。在衬底上形成与各自的沟道相关的pFET堆体和nFET堆体。第一材料层提供在与pFET堆体相关的源极/漏极区。第一材料层具有与衬底的基晶格常数不同的晶格常数以在pFET沟道内产生压应力状态。第二材料层提供在与nFET堆体相关的源极/漏极区。第二材料层具有与衬底的基晶格常数不同的晶格常数以在nFET沟道内产生拉应力状态。
在本发明的另一方面中，提供了一种制造半导体结构的方法，所述方法包括：在衬底中形成p型场效应晶体管(pFET)沟道和n型场效应晶体管(nFET)沟道。在衬底上分别形成与pFET沟道和nFET沟道相关的pFET结构和nFET结构。将pFET结构和nFET结构的区域蚀刻到预定的深度。在pFET结构的蚀刻区域中提供了第一材料以在pFET沟道中产生压应力，第一材料具有与衬底的基晶格常数不同的晶格常数。在nFET结构的蚀刻区域中提供了第二材料以在nFET沟道中产生拉应力，第二材料具有与衬底的基晶格常数不同的晶格常数。提供nFET和pFET结构的掺杂源极和漏极区。
在本发明的又一方面中，半导体结构包括半导体衬底，且pFET和nFET形成于衬底中各自的沟道中。pFET沟道的源极和漏极区中的第一材料层具有与衬底的晶格常数不同的晶格常数。nFET沟道的源极和漏极区中的第二材料层具有与衬底的晶格常数不同的晶格常数。
附图说明
图1a到1e示出了根据本发明形成器件的制造工艺；
图2图示了根据本发明的pFET器件中应力的位置；以及
图3图示了根据本发明的nFET器件中应力的位置。
具体实施方式
本发明涉及半导体器件及制造方法，其接近CMOS器件的nFET沟道提供拉应力而接近CMOS器件的pFET沟道提供压应力。在本发明的一个实施例中，纵向拉应力非常接近nFET沟道而同时压应力非常接近pFET沟道。另外，在本发明中，提供了一种工艺和结构来将SiGe和Si:C材料集成入CMOS技术中。
例如，在硅衬底中在源极/漏极(S/D)区中提供了(例如，埋入)有高度拉应力的Si:C膜，以在纵向将拉应力施加到其栅极区下的沟道中的nFET结构上。相似地，在硅衬底中在S/D区中提供了(例如，埋入)有高度压应力的SiGe膜，以在纵向将压应力施加到其栅极区下的沟道中的pFET结构上。相似于SiGe层，Si:C层比较薄(在其临界厚度下)，且没有松弛。nFET的晶体管沟道区通过来自Si:C层的应力而产生应变，而pFET的沟道区被提供有来自SiGe的压应力。
因为将SiGe层埋入pFET的S/D区，所以仍可以形成低电阻硅化物。有趣的是，埋入的(例如，表面下或与表面共平面)Si:C膜可以比表面上的Si:C对应部分施加更大的应力，因为该膜表面不是没有应力的。在本发明中，设想Si:C的不同厚度和突起，无论是埋入或与表面共平面或从平面升起。应可以理解通过调整SiGe层中Ge含量的浓度，可调整pFET沟道中的压应力。相似地，通过调整Si:C层中的C浓度，可以调整nFET沟道中的拉应力。这是因为这些材料的晶格常数。
在本发明中，显示了Si:C具有适当的应力，Si:C包含了适当的C含量，且Si:C可以外延和选择性地生长。而且，在本发明中，Si:C不用作沟道下直接构建的叠层，而是作为拉伸状态的nFET S/D区的替代材料，且因此在沟道区中施加了拉伸应力。因此该Si:C膜将拉应力施加到nFET沟道，同时SiGe将压应力施加到pFET沟道。
图1a到1e表现了根据本发明形成器件的制造工艺。在图1a中，提供了绝缘体上硅(SOI)20等。例如使用垫氧化、垫氮化物沉积、基于光刻的构图、由氮化物、氧化物和硅构成的堆体下至埋入氧化物的反应离子蚀刻(RIE)、边缘氧化、衬垫沉积、填充沉积和化学机械抛光，将层20构图以形成浅沟槽隔离(STI)部件25。STI形成工艺在本领域中是公知的。然后剥离垫氮化物。以任何公知的方式，栅极堆体形成于该结构上以形成pFET和nFET，栅极堆体例如包括栅极电介质和多晶硅。按照公知的方式为pFET和nFET形成TEOS盖43和44。
仍参考图1a，使用任何公知的工艺，在pFET和nFET堆体上分别形成分隔物。例如，分隔物38形成于pFET堆体40a的侧壁上，且分隔物42形成于pFET堆体45a的侧壁上。分隔物例如可以是氧化物或氮化物分隔物。
在图1b中，将薄衬垫50毯覆式沉积在例如包括pFET堆体、nFET堆体和其S/D区的结构上方。在一个实施例中，薄衬垫50是Si3N4衬垫或任何根据硬掩模材料的氮化物或氧化物基的材料。薄衬垫的厚度范围大致为5到20nm。薄衬垫50可以作为保护层。然后硬掩模51形成于nFET堆体45a和其S/D区上方。
将pFET堆体40a周围的区域蚀刻到衬垫50。然后将衬垫50蚀刻且相邻于堆体40a形成(蚀刻)S/D区52。根据SOI层的厚度，S/D区52的深度为约20到100nm。在pFET堆体40a的区52中生长有高度压应力的选择性外延SiGe层60，如图1c所示，完全填充S/D蚀刻的区52。SiGe层60可以被生长为约10到100nm的厚度，尽管由本发明也可以设想其它的厚度。在一个实施例中，SiGe层生长为高于栅极氧化物表面的厚度。使用任何公知的工艺，比如例如湿法化学工艺，去除硬掩模和衬垫的剩余部分。在工艺步骤中，在去除硬掩模之前，将掺杂剂离子注入以形成pFET堆体40a附近的S/D区。
独立而言，SiGe一般具有大于SOI的晶格常数。即，SiGe材料的晶格常数与Si的晶格常数不匹配。然而，在本发明的结构中，由于SiGe层的生长，SiGe层的晶格结构将趋于匹配下面的Si的晶格结构。这造成了SiGe层和与之相邻或相近的沟道区具有压应力。在一个实施例中，SiGe层的Ge含量对于Si含量的比例可以大于0％且更大。
仍参考本发明的工艺，在图1d中，例如再次在包括nFET、pFET和其S/D区的结构上方毯覆式沉积薄衬垫50。在一个实施例中，薄衬垫50是Si3N4衬垫或任何根据硬掩模材料的氮化物或氧化物材料。薄衬垫的厚度范围大致为5到20nm。薄衬垫50可以作为保护层。
然后掩模51形成于pFET堆体40a上方，且将nFET堆体45a周围的区域蚀刻到衬垫50。然后将衬垫50蚀刻且相邻于堆体45a形成(蚀刻)S/D区54。根据SOI层的厚度，S/D区54的深度为约20到100nm。可以使用任何公知的工艺来蚀刻区54。
在nFET堆体45a的区54中生长有高度拉应力的选择性外延Si:C层62，如图1e所示，Si:C层62被生长为约10到100nm的厚度。应当理解Si:C层62可以外延生长为其它厚度，如本发明所设想的。在一个实施例中，C含量对于硅含量的比例可以大于0到4％。使用任何公知的工艺，比如例如使用湿法化学工艺，去除抗蚀剂和薄衬垫的剩余部分。
独立而言，Si:C一般具有比下面的Si更小的晶格常数。即，Si:C材料的晶格常数与Si的晶格常数不匹配。然而，在本发明的结构中，由于Si:C层在nFET的堆体45a的S/D区内的生长，Si:C层的晶格结构将趋于匹配下面的Si的晶格结构。这造成Si:C层和与之相邻或相近的沟道区具有拉应力。
在一个实施例中，例如，通过进行RIE、湿法蚀刻或其它工艺或其组合，用于工艺优化以凹进这样的层，Si:C和/或SiGe层可以嵌入器件内。然后，使用任何公知工艺，Si选择性生长在区52和54的上方。然后可使用任何公知工艺进行源极和漏极注入。还可以进行进一步的工艺来构建器件和互连。
如现在可以理解的，Si:C和SiGe层可以被嵌入器件内，或可以与器件共平面，或可以从器件升起。在一个实施例中，Si:C和SiGe膜沉积为10到100nm的厚度，其提供了一种将(压或拉)应力增加到MOSFET的更有成本效率的方法。在升起的实施例中，Si:C和SiGe层可以在器件的表面上方升起约50nm。应认识到通过本发明也可以设想其它的厚度。
而且，还可以用P型掺杂剂原位掺杂SiGe且用n型掺杂剂原位掺杂Si:C来分别形成pFET和nFET的源极和漏极区。
本领域的普通技术人员应还理解可以相等地在图1b和1c所示的工艺步骤之前进行图1d和1e的工艺步骤。而且，可以进行比如例如标准离子注入的进一步工艺步骤来形成pFET和nFET的S/D区。由于在该工艺期间nFET和pFET区中的栅极氧化物作为掩模，通过离子注入形成S/D区是自对准的。
图2图示了根据本发明的pFET器件的应力的位置。如图2所示，直接在具有未松弛SiGe区的pFET下面出现了压应力。更具体而言，在本发明的结构中，SiGe层的晶格结构匹配下面的硅绝缘层的晶格结构。这造成SiGe层及周围区域处于压应力下。
图3图示了根据本发明的nFET器件的应力的位置。如图3所示，在nFET的沟道中出现了拉应力。更具体而言，在本发明的结构中，Si:C层的晶格结构匹配下面的硅绝缘层20的晶格结构以在nFET沟道中形成拉应力分量。
虽然就实施例描述了本发明，但是本领域的技术人员可以认识到本发明可以在修改的情况下且在权利要求的精神和范围内被实践。例如，本发明可以被容易地应用于体衬底。

Claims (18)

1、一种制造半导体结构的方法，包括的步骤为：
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道；
在p型场效应晶体管沟道中形成p型场效应晶体管堆栈，在n型场效应晶体管沟道中形成n型场效应晶体管堆栈；
在与p型场效应晶体管堆栈相关的源极/漏极区提供第一材料层，所述第一材料层具有与所述衬底的基晶格常数不同的晶格常数以在p型场效应晶体管沟道内产生压应力状态；以及
在与n型场效应晶体管堆栈相关的源极/漏极区提供第二材料层，所述第二材料层具有与所述衬底的基晶格常数不同的晶格常数以在n型场效应晶体管沟道内产生拉应力状态，
其中所述第一材料层和所述第二材料层生长为10到100nm的厚度。
2、根据权利要求1所述的方法，其中所述第一材料层是SiGe，SiGe的Ge含量对于Si的比例大于0％。
3、根据权利要求1所述的方法，其中所述第二材料层是Si:C。
4、根据权利要求3所述的方法，其中所述Si:C的C含量对于硅含量的比例为4％或更小。
5、根据权利要求1所述的方法，其中所述第一材料层是未松弛的SiGe，且所述第二材料层是未松弛的Si:C。
6、根据权利要求1所述的方法，其中
通过将掩模放置在n型场效应晶体管沟道上方且蚀刻p型场效应晶体管的区域，以及在p型场效应晶体管的蚀刻的区域内选择性地生长所述第一材料层，从而形成所述第一材料层；以及
通过将掩模放置在p型场效应晶体管沟道上方且蚀刻n型场效应晶体管的区域，以及在n型场效应晶体管的蚀刻的区域内选择性地生长所述第二材料层，从而形成所述第二材料层。
7、根据权利要求6所述的方法，还包括的步骤为：
在蚀刻p型场效应晶体管堆栈的区域和在选择性地生长所述第一材料层之前，在所述掩模下和所述n型场效应晶体管堆栈上方提供保护层；以及
在蚀刻n型场效应晶体管堆栈的区域和在选择性地生长所述第二材料层之前，在所述掩模下和所述p型场效应晶体管堆栈上方提供保护层。
8、根据权利要求1所述的方法，其中所述第一材料层和所述第二材料层嵌入所述衬底中。
9、一种制造半导体结构的方法，包括的步骤为：
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道；
在所述衬底上分别形成与p型场效应晶体管沟道和n型场效应晶体管沟道相关的p型场效应晶体管结构和n型场效应晶体管结构；
蚀刻p型场效应晶体管结构和n型场效应晶体管结构的区域；
在p型场效应晶体管结构的蚀刻的区域中形成第一材料以在p型场效应晶体管沟道中提供压应力，所述第一材料具有与所述衬底的基晶格常数不同的晶格常数；
在n型场效应晶体管结构的蚀刻的区域中形成第二材料以在n型场效应晶体管沟道中提供拉应力，所述第二材料具有与所述衬底的基晶格常数不同的晶格常数；以及
掺杂p型场效应晶体管结构和n型场效应晶体管结构的源极和漏极区，
其中所述第一材料和所述第二材料生长为10到100nm的厚度。
10、根据权利要求9所述的方法，其中所述第一材料是SiGe，所述第二材料是Si:C。
11、根据权利要求9所述的方法，其中
通过将保护层放置在n型场效应晶体管结构和p型场效应晶体管结构上方且在p型场效应晶体管沟道的源极和漏极区内生长所述第一材料，从而形成所述第一材料；以及
通过将保护层放置在p型场效应晶体管结构和p型场效应晶体管结构的源极和漏极区以及n型场效应晶体管结构上方，和在n型场效应晶体管沟道的源极和漏极区内生长所述第二材料，从而形成所述第二材料。
12、根据权利要求9所述的方法，其中所述第一材料和所述第二材料嵌入所述衬底中。
13、根据权利要求9所述的方法，其中所述第一材料和所述第二材料升起在所述衬底的表面的上方。
14、根据权利要求9所述的方法，其中所述第一材料是未松弛的SiGe。
15、根据权利要求9所述的方法，还包括的步骤为：用p型掺杂剂原位掺杂第一材料和用n型掺杂剂原位掺杂第二材料以分别形成p型场效应晶体管和n型场效应晶体管的源极和漏极区。
16、一种半导体结构，包括：
形成于衬底中的p型场效应晶体管沟道；
形成于所述衬底中的n型场效应晶体管沟道；
在p型场效应晶体管沟道的源极和漏极区中的第一材料层，所述第一材料层具有与所述衬底的晶格常数不同的晶格常数；以及
在n型场效应晶体管沟道的源极和漏极区中的第二材料层，所述第二材料层具有与所述衬底的晶格常数不同的晶格常数，
其中所述第一材料层和所述第二材料层生长为10到100nm的厚度。
17、根据权利要求16所述的结构，其中所述第一材料层是SiGe且所述第二材料层是Si:C。
18、根据权利要求16所述的结构，其中所述第一材料层和所述第二材料层分别在p型场效应晶体管沟道和n型场效应晶体管沟道中产生了不同类型的应力。
CNB2004800307527A 2003-10-20 2004-10-19 使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法 Active CN100562972C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/689,506 US7303949B2 (en) 2003-10-20 2003-10-20 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US10/689,506 2003-10-20

Publications (2)

Publication Number Publication Date
CN101199037A CN101199037A (zh) 2008-06-11
CN100562972C true CN100562972C (zh) 2009-11-25

Family

ID=34521428

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800307527A Active CN100562972C (zh) 2003-10-20 2004-10-19 使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法

Country Status (7)

Country Link
US (5) US7303949B2 (zh)
EP (1) EP1676297A4 (zh)
JP (1) JP2007528593A (zh)
KR (1) KR100985935B1 (zh)
CN (1) CN100562972C (zh)
TW (1) TWI351762B (zh)
WO (1) WO2005043591A2 (zh)

Families Citing this family (160)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642566B2 (en) * 2006-06-12 2010-01-05 Dsm Solutions, Inc. Scalable process and structure of JFET for small and decreasing line widths
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US7354815B2 (en) * 2003-11-18 2008-04-08 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
US7247534B2 (en) * 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
US7122435B2 (en) * 2004-08-02 2006-10-17 Texas Instruments Incorporated Methods, systems and structures for forming improved transistors
US7067868B2 (en) * 2004-09-29 2006-06-27 Freescale Semiconductor, Inc. Double gate device having a heterojunction source/drain and strained channel
US7335544B2 (en) * 2004-12-15 2008-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making MOSFET device with localized stressor
KR100703967B1 (ko) * 2005-02-28 2007-04-05 삼성전자주식회사 씨모스 트랜지스터 및 그 제조 방법
JP4515305B2 (ja) * 2005-03-29 2010-07-28 富士通セミコンダクター株式会社 ｐチャネルＭＯＳトランジスタおよびその製造方法、半導体集積回路装置の製造方法
KR101225269B1 (ko) * 2005-05-26 2013-01-22 파나소닉 주식회사 시스템의 공존을 가능하게 하는 통신장치
DE102005030583B4 (de) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement
EP1908103B1 (en) * 2005-06-30 2011-01-05 Advanced Micro Devices, Inc. Technique for forming contact insulation layers silicide regions with different characteristics
US20070018252A1 (en) * 2005-07-21 2007-01-25 International Business Machines Corporation Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same
US20070026599A1 (en) * 2005-07-27 2007-02-01 Advanced Micro Devices, Inc. Methods for fabricating a stressed MOS device
US7470943B2 (en) 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US7436169B2 (en) * 2005-09-06 2008-10-14 International Business Machines Corporation Mechanical stress characterization in semiconductor device
JP2007073800A (ja) * 2005-09-08 2007-03-22 Seiko Epson Corp 半導体装置
JP2007165817A (ja) * 2005-11-18 2007-06-28 Sony Corp 半導体装置およびその製造方法
US8159030B2 (en) * 2005-11-30 2012-04-17 Globalfoundries Inc. Strained MOS device and methods for its fabrication
US7422950B2 (en) * 2005-12-14 2008-09-09 Intel Corporation Strained silicon MOS device with box layer between the source and drain regions
US8101485B2 (en) * 2005-12-16 2012-01-24 Intel Corporation Replacement gates to enhance transistor strain
ATE449418T1 (de) * 2005-12-23 2009-12-15 Imec Methode für ein selektives epitaktisches wachstum von source/drain gebieten
US20070158739A1 (en) * 2006-01-06 2007-07-12 International Business Machines Corporation Higher performance CMOS on (110) wafers
US20070184600A1 (en) * 2006-02-06 2007-08-09 Freescale Semiconductor Stressed-channel CMOS transistors
JP4847152B2 (ja) * 2006-02-22 2011-12-28 富士通セミコンダクター株式会社 半導体装置とその製造方法
US20070238236A1 (en) * 2006-03-28 2007-10-11 Cook Ted Jr Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain
US20070238267A1 (en) * 2006-03-28 2007-10-11 International Business Machines Corporation Epitaxy of Silicon-Carbon Substitutional Solid Solutions by Ultra-Fast Annealing of Amorphous Material
JP2007281038A (ja) * 2006-04-03 2007-10-25 Toshiba Corp 半導体装置
US20070287244A1 (en) * 2006-04-26 2007-12-13 Applied Materials, Inc., A Delaware Corporation ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS
WO2007130240A1 (en) * 2006-04-28 2007-11-15 Advanced Micro Devices , Inc. A transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility
DE102006019835B4 (de) * 2006-04-28 2011-05-12 Advanced Micro Devices, Inc., Sunnyvale Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist
US20070257315A1 (en) * 2006-05-04 2007-11-08 International Business Machines Corporation Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors
US7560326B2 (en) * 2006-05-05 2009-07-14 International Business Machines Corporation Silicon/silcion germaninum/silicon body device with embedded carbon dopant
KR100703986B1 (ko) * 2006-05-22 2007-04-09 삼성전자주식회사 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same
US8278176B2 (en) * 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US7618866B2 (en) * 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
US7473594B2 (en) 2006-07-25 2009-01-06 International Business Machines Corporation Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
DE102006035666B3 (de) * 2006-07-31 2008-04-17 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur
US8211761B2 (en) * 2006-08-16 2012-07-03 Globalfoundries Singapore Pte. Ltd. Semiconductor system using germanium condensation
US8154051B2 (en) * 2006-08-29 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. MOS transistor with in-channel and laterally positioned stressors
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
JP2008060408A (ja) * 2006-08-31 2008-03-13 Toshiba Corp 半導体装置
JP5114919B2 (ja) * 2006-10-26 2013-01-09 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8039284B2 (en) * 2006-12-18 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual metal silicides for lowering contact resistance
US7892931B2 (en) * 2006-12-20 2011-02-22 Texas Instruments Incorporated Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
US8217423B2 (en) 2007-01-04 2012-07-10 International Business Machines Corporation Structure and method for mobility enhanced MOSFETs with unalloyed silicide
KR100855977B1 (ko) * 2007-02-12 2008-09-02 삼성전자주식회사 반도체 소자 및 그 제조방법
US7927954B2 (en) * 2007-02-26 2011-04-19 United Microelectronics Corp. Method for fabricating strained-silicon metal-oxide semiconductor transistors
US20080237733A1 (en) * 2007-03-27 2008-10-02 International Business Machines Corporation Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress
US20080272395A1 (en) * 2007-05-03 2008-11-06 Dsm Solutions, Inc. Enhanced hole mobility p-type jfet and fabrication method therefor
JP5133619B2 (ja) * 2007-07-02 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7615435B2 (en) * 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
US8058123B2 (en) 2007-11-29 2011-11-15 Globalfoundries Singapore Pte. Ltd. Integrated circuit and method of fabrication thereof
US7767579B2 (en) * 2007-12-12 2010-08-03 International Business Machines Corporation Protection of SiGe during etch and clean operations
JP2009152394A (ja) * 2007-12-20 2009-07-09 Toshiba Corp 半導体装置及びその製造方法
KR101197464B1 (ko) * 2007-12-26 2012-11-09 삼성전자주식회사 반도체 장치의 제조 방법
US7892932B2 (en) * 2008-03-25 2011-02-22 International Business Machines Corporation Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US7838372B2 (en) * 2008-05-22 2010-11-23 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
US20090302348A1 (en) * 2008-06-10 2009-12-10 International Business Machines Corporation Stress enhanced transistor devices and methods of making
US20100001317A1 (en) 2008-07-03 2010-01-07 Yi-Wei Chen Cmos transistor and the method for manufacturing the same
US7759142B1 (en) * 2008-12-31 2010-07-20 Intel Corporation Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
KR20100081667A (ko) * 2009-01-07 2010-07-15 삼성전자주식회사 스트레인드 채널을 갖는 반도체 장치 및 그 제조 방법
US8216893B2 (en) 2009-01-26 2012-07-10 International Business Machines Corporation Stress enhanced transistor devices and methods of making
US7670934B1 (en) * 2009-01-26 2010-03-02 Globalfoundries Inc. Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions
KR20100087256A (ko) 2009-01-26 2010-08-04 인터내셔널 비지네스 머신즈 코포레이션 개선된 트랜지스터 소자 및 제조 방법
US7935593B2 (en) 2009-02-05 2011-05-03 Samsung Electronics Co., Ltd. Stress optimization in dual embedded epitaxially grown semiconductor processing
US8305829B2 (en) * 2009-02-23 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
DE102009010847B4 (de) * 2009-02-27 2012-12-27 Advanced Micro Devices, Inc. Integration von Halbleiterlegierungen in PMOS- und NMOS-Transistoren unter Anwendung eines gemeinsamen Ätzprozesses für Aussparungen
US8305790B2 (en) * 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
US8957482B2 (en) * 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8461015B2 (en) * 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8264032B2 (en) * 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8472227B2 (en) * 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8022488B2 (en) * 2009-09-24 2011-09-20 International Business Machines Corporation High-performance FETs with embedded stressors
KR20110036312A (ko) * 2009-10-01 2011-04-07 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20110097867A1 (en) * 2009-10-22 2011-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of controlling gate thicknesses in forming fusi gates
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8592325B2 (en) * 2010-01-11 2013-11-26 International Business Machines Corporation Insulating layers on different semiconductor materials
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
KR101576529B1 (ko) * 2010-02-12 2015-12-11 삼성전자주식회사 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법
US8299535B2 (en) * 2010-06-25 2012-10-30 International Business Machines Corporation Delta monolayer dopants epitaxy for embedded source/drain silicide
CN102386226B (zh) * 2010-08-31 2013-08-28 中国科学院微电子研究所 半导体结构及其制造方法
CN102446953B (zh) * 2010-09-30 2015-08-05 中国科学院微电子研究所 一种半导体结构及其制造方法
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
CN102456739A (zh) * 2010-10-28 2012-05-16 中国科学院微电子研究所 半导体结构及其形成方法
US8426265B2 (en) 2010-11-03 2013-04-23 International Business Machines Corporation Method for growing strain-inducing materials in CMOS circuits in a gate first flow
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8361847B2 (en) 2011-01-19 2013-01-29 International Business Machines Corporation Stressed channel FET with source/drain buffers
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8372705B2 (en) 2011-01-25 2013-02-12 International Business Machines Corporation Fabrication of CMOS transistors having differentially stressed spacers
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US20120292637A1 (en) * 2011-05-17 2012-11-22 Globalfoundries Inc. Dual Cavity Etch for Embedded Stressor Regions
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
CN102789986B (zh) * 2011-05-20 2015-03-04 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
KR101865754B1 (ko) * 2011-07-01 2018-06-12 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN102856259A (zh) * 2011-07-01 2013-01-02 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US20130099318A1 (en) 2011-10-25 2013-04-25 International Business Machines Corporation Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US8507915B2 (en) * 2011-11-30 2013-08-13 International Business Machines Corporation Low resistance embedded strap for a trench capacitor
US8963202B2 (en) * 2012-02-09 2015-02-24 United Microelectronics Corporation Electrostatic discharge protection apparatus
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
CN103855096B (zh) * 2012-12-04 2016-06-29 中芯国际集成电路制造(上海)有限公司 Cmos晶体管的形成方法
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US20140306290A1 (en) * 2013-04-11 2014-10-16 International Business Machines Corporation Dual Silicide Process Compatible with Replacement-Metal-Gate
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
KR102069275B1 (ko) 2013-06-07 2020-01-22 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
CN104253090B (zh) * 2013-06-26 2017-11-03 中芯国际集成电路制造(上海)有限公司 Cmos晶体管的形成方法
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9245972B2 (en) 2013-09-03 2016-01-26 United Microelectronics Corp. Method for manufacturing semiconductor device
US20150069327A1 (en) * 2013-09-11 2015-03-12 International Business Machines Corporation Fin field-effect transistors with superlattice channels
US9391077B2 (en) 2014-02-10 2016-07-12 International Business Machines Corporation SiGe and Si FinFET structures and methods for making the same
US9385191B2 (en) 2014-11-20 2016-07-05 United Microelectronics Corporation FINFET structure
US9685510B2 (en) 2015-09-10 2017-06-20 International Business Machines Corporation SiGe CMOS with tensely strained NFET and compressively strained PFET
US10115808B2 (en) 2016-11-29 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. finFET device and methods of forming
WO2018101278A1 (ja) * 2016-11-30 2018-06-07 株式会社リコー 酸化物又は酸窒化物絶縁体膜形成用塗布液、酸化物又は酸窒化物絶縁体膜、電界効果型トランジスタ、及びそれらの製造方法
US10134876B2 (en) 2017-03-31 2018-11-20 Globalfoundries Inc. FinFETs with strained channels and reduced on state resistance
KR102484092B1 (ko) 2019-12-13 2023-01-04 울산대학교 산학협력단 고 유전율 및 밴드갭을 가지는 게이트 구조체 및 이의 제조방법
KR20220108885A (ko) 2021-01-27 2022-08-04 삼성디스플레이 주식회사 표시 장치

Family Cites Families (135)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US86472A (en) * 1869-02-02 photo-lithographer
US90791A (en) * 1869-06-01 Improvement in saw-guide and jointer
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
DE3676781D1 (de) * 1985-09-13 1991-02-14 Siemens Ag Integrierte bipolar- und komplementaere mos-transistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
US5059559A (en) * 1987-11-02 1991-10-22 Hitachi, Ltd. Method of aligning and bonding tab inner leads
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) * 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
JP2851753B2 (ja) 1991-10-22 1999-01-27 三菱電機株式会社 半導体装置およびその製造方法
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5354698A (en) * 1993-07-19 1994-10-11 Micron Technology, Inc. Hydrogen reduction method for removing contaminants in a semiconductor ion implantation process
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US6107690A (en) * 1995-09-26 2000-08-22 Micron Technology, Inc. Coated semiconductor die/leadframe assembly and method for coating the assembly
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
EP0838858B1 (de) * 1996-09-27 2002-05-15 Infineon Technologies AG Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US6159815A (en) * 1996-09-27 2000-12-12 Siemens Aktiengesellschaft Method of producing a MOS transistor
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
US5840598A (en) * 1997-08-14 1998-11-24 Micron Technology, Inc. LOC semiconductor assembled with room temperature adhesive
JP3139426B2 (ja) * 1997-10-15 2001-02-26 日本電気株式会社 半導体装置
JPH11163343A (ja) * 1997-11-28 1999-06-18 Nec Corp 半導体装置およびその製造方法
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (ko) * 1998-03-02 2000-12-15 윤종용 집적 회로에 트렌치 아이솔레이션을 형성하는방법
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US6165383A (en) 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US5989978A (en) 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6319794B1 (en) 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
ATE394794T1 (de) 1999-03-12 2008-05-15 Ibm Ge kanal-heterostruktur mit hoher geschwindigkeit für feldeffektanordnungen
US6103563A (en) * 1999-03-17 2000-08-15 Advanced Micro Devices, Inc. Nitride disposable spacer to reduce mask count in CMOS transistor formation
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6310390B1 (en) * 1999-04-08 2001-10-30 Micron Technology, Inc. BGA package and method of fabrication
US6270353B1 (en) 1999-06-07 2001-08-07 International Business Machines Corporation Low cost shallow trench isolation using non-conformal dielectric material
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6631995B2 (en) * 1999-09-02 2003-10-14 Koninklijke Philips Electronics N.V. Method of and device for generating an image having a desired brightness
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6476462B2 (en) 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
JP2001338988A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
WO2002043151A1 (en) 2000-11-22 2002-05-30 Hitachi, Ltd Semiconductor device and method for fabricating the same
US7312485B2 (en) * 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
JP2003086708A (ja) * 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
US6844227B2 (en) 2000-12-26 2005-01-18 Matsushita Electric Industrial Co., Ltd. Semiconductor devices and method for manufacturing the same
US6563152B2 (en) * 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) * 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3678661B2 (ja) 2001-03-08 2005-08-03 シャープ株式会社 半導体装置
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
KR100387531B1 (ko) * 2001-07-30 2003-06-18 삼성전자주식회사 반도체소자 제조방법
US6908810B2 (en) * 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
EP1428262A2 (en) 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) * 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
WO2003028106A2 (en) * 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6656798B2 (en) * 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP2003152177A (ja) * 2001-11-19 2003-05-23 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6703271B2 (en) 2001-11-30 2004-03-09 Taiwan Semiconductor Manufacturing Company Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
US6819192B2 (en) * 2002-02-14 2004-11-16 Sun Microsystems, Inc. Jitter estimation for a phase locked loop
JP2003243532A (ja) * 2002-02-15 2003-08-29 Toshiba Corp 相補型半導体装置および相補型半導体装置の製造方法
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
WO2003105206A1 (en) * 2002-06-10 2003-12-18 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
JP2004031753A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
US6573172B1 (en) * 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6882010B2 (en) * 2002-10-03 2005-04-19 Micron Technology, Inc. High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US7022561B2 (en) * 2002-12-02 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device
US6808980B2 (en) 2002-12-05 2004-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6974981B2 (en) 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US7001837B2 (en) * 2003-01-17 2006-02-21 Advanced Micro Devices, Inc. Semiconductor with tensile strained substrate and method of making the same
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6955952B2 (en) * 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7045408B2 (en) * 2003-05-21 2006-05-16 Intel Corporation Integrated circuit with improved channel stress properties and a method for making it
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US6982433B2 (en) * 2003-06-12 2006-01-03 Intel Corporation Gate-induced strain for MOS performance improvement
US6927414B2 (en) * 2003-06-17 2005-08-09 International Business Machines Corporation High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US7279746B2 (en) 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7342289B2 (en) 2003-08-08 2008-03-11 Taiwan Semiconductor Manufacturing Co., Ltd Strained silicon MOS devices
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US7012324B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Lead frame with flag support structure
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US8008724B2 (en) * 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7122849B2 (en) * 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7205206B2 (en) * 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7316960B2 (en) * 2004-07-13 2008-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Strain enhanced ultra shallow junction formation
US7354806B2 (en) * 2004-09-17 2008-04-08 International Business Machines Corporation Semiconductor device structure with active regions having different surface directions and methods

Also Published As

Publication number Publication date
EP1676297A4 (en) 2008-06-25
US9023698B2 (en) 2015-05-05
US20070296038A1 (en) 2007-12-27
CN101199037A (zh) 2008-06-11
TW200525759A (en) 2005-08-01
US20050082616A1 (en) 2005-04-21
US20070264783A1 (en) 2007-11-15
US20120196412A1 (en) 2012-08-02
US7303949B2 (en) 2007-12-04
US9401424B2 (en) 2016-07-26
WO2005043591A8 (en) 2005-11-03
US20140322873A1 (en) 2014-10-30
WO2005043591A3 (en) 2007-06-21
US8168489B2 (en) 2012-05-01
TWI351762B (en) 2011-11-01
US8901566B2 (en) 2014-12-02
EP1676297A2 (en) 2006-07-05
WO2005043591A2 (en) 2005-05-12
JP2007528593A (ja) 2007-10-11
KR20060090828A (ko) 2006-08-16
KR100985935B1 (ko) 2010-10-06

Similar Documents

Publication Publication Date Title
CN100562972C (zh) 使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法
KR100473663B1 (ko) Ｃｍｏｓ 장치 제조방법
TW506076B (en) CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same
US7452761B2 (en) Hybrid SOI-bulk semiconductor transistors
US7560328B2 (en) Strained Si on multiple materials for bulk or SOI substrates
US7781800B2 (en) Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
US7202120B2 (en) Semiconductor integrated circuit device and fabrication process thereof
US7928474B2 (en) Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
US7335929B2 (en) Transistor with a strained region and method of manufacture
US8216904B2 (en) Strained transistor and method for forming the same
US20070231983A1 (en) Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US7544548B2 (en) Trench liner for DSO integration
KR101904114B1 (ko) 다양한 변형 상태를 갖는 트랜지스터 채널을 포함하는 반도체 층을 제조하는 방법, 및 관련 반도체 층
JP5204106B2 (ja) 電子移動度が増大したトランジスタを形成する方法
US20090315115A1 (en) Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement
US7863141B2 (en) Integration for buried epitaxial stressor
KR20040093183A (ko) 소스/드레인 확장부에서 도판트의 확산 유출을 방지하기위한 실리콘 산화물 라이너의 이온 주입
US8853752B2 (en) Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
JP2011066042A (ja) 半導体装置とその製造方法
CN103367226A (zh) 半导体器件制造方法
US20130260532A1 (en) Method for Manufacturing Semiconductor Device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant