CN100561732C - 形成半导体封装的方法及其结构 - Google Patents

形成半导体封装的方法及其结构 Download PDF

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CN100561732C
CN100561732C CNB2004800274152A CN200480027415A CN100561732C CN 100561732 C CN100561732 C CN 100561732C CN B2004800274152 A CNB2004800274152 A CN B2004800274152A CN 200480027415 A CN200480027415 A CN 200480027415A CN 100561732 C CN100561732 C CN 100561732C
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lead
conductive layer
lead frame
coupled
wire
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CN1856878A (zh
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达文·S·马哈德万
迈克尔·E·查普曼
阿尔温德·S·萨利安
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H01L2924/3025—Electromagnetic shielding

Abstract

通过在模制密封剂(35，62)上形成导电层(42，64)从而形成一种电磁干扰(EMI)和/或电磁辐射屏蔽。导电层(42，64)可以用引线与半导体封装(2，50)的引线框(10，52)电耦连。电耦连的执行如下：将引线框(10)的两个器件部分(2，4，6，8)引线接合在一起，然后通过在上面的模制密封剂(35)内形成一个凹槽(40)切割该引线键合(10)从而形成两个引线(33)。然后将导电层(42)与两个引线(33)的每一个电耦连。在另一个实施例中，在半导体单元片(57)上形成环状引线键合(61)。在模制密封之后，除去部分的模制密封剂(62)从而暴露环形引线键合(61)的一部分。然后在模制密封剂(62)和环形引线键合(61)暴露部分的上面形成导电层(64)，从而使导电层(64)与环形引线键合(61)电耦连。

Description

形成半导体封装的方法及其结构
技术领域
本发明总体上涉及半导体器件，更特别地，涉及半导体封装。
背景技术
半导体器件需要加以保护，以免受到由其它产品发射到大气中的电磁波的干扰。例如，汽车中，燃烧的火花塞能够产生电磁波，对安装在车篷下的微控制器产生不良干扰。传统的封装并不保护其内部的半导体器件免于电磁波的干扰。
为了防止电磁波干扰，人们将一组半导体器件布置在模块或盒子内。该模块能够屏蔽半导体器件使之免于电磁干扰(EMI)。尽管使用模块可以提供对外部干扰的完全EMI保护，但是模块内部的半导体器件还是会彼此相互干扰。出于低成本的要求和系统复杂性的增加，需要有一种自身能够屏蔽电磁波的半导体封装，从而能够将半导体器件布置在汽车的各个部位，可以带有模块或者不带有模块。例如，为了检测来自不同方向的碰撞，需要将合适的传感器定位在汽车的各个位置。而且，不能够将没有EMI保护的传感器与其它会产生EMI的半导体器件分组在相同的模块内。但是如果为了电磁保护而将每个传感器布置在单独的模块内，则会使成本变得高昂。
防止电磁干扰的一个解决办法是，在模制封装之前，在半导体器件上设置一个金属帽。该解决办法只能够应用于球栅阵列(BGA)封装，其密封一个大的半导体单元片(也就是，至少1平方英寸)。
发明内容
因此，需要有一种用于解决元件水平EMI屏蔽的方法，其能够用于各种具有任何半导体单元片尺寸的封装。
本发明提供一种半导体封装，包括：
引线框，其具有标签和键合焊垫；
半导体单元片，其附着到标签上并与键合焊垫电耦连；
模制密封剂，其位于半导体单元片之上，其中模制密封剂具有凹槽；
导电层，其位于模制密封剂之上；以及
引线，其将引线框电耦连于凹槽中的导电层。
根据本发明的上述半导体封装的一个实施例，其中导电层包含铁磁材料。
根据本发明的上述半导体封装的一个实施例，其中引线通过半导体单元片和引线键合耦连于引线框。
根据本发明的上述半导体封装的一个实施例，其中引线通过焊垫耦连于引线框。
根据本发明的上述半导体封装的一个实施例，其中导电层是一个电磁屏蔽。
本发明还提供一种形成半导体封装的方法，该方法包括：
提供引线框，该引线框具有标签、第一接地焊垫、和第二接地焊垫；
将半导体单元片附着到标签；
在半导体单元片之上形成模制密封剂；
在模制密封剂之上形成导电层；以及
使用引线将引线框电耦连于导电层，
其中，使用引线将引线框电耦连于导电层的步骤进一步包括：
提供具有第一端和第二端的引线；
将第一端电耦连于第一接地焊垫，将第二端电耦连于第二接地焊垫；以及
除去模制密封剂的一部分以暴露引线的一部分；
其中，形成导电层的步骤进一步包括：
将导电层电耦连于引线。
根据本发明的上述方法的一个实施例，其中，在半导体单元片之上形成模制密封剂的步骤进一步包括在引线上形成模制密封剂。
根据本发明的上述方法的一个实施例，其中，除去模制密封剂的一部分以暴露引线的一部分的步骤进一步包括在模制密封剂中形成凹槽，其中凹槽具有侧壁。
根据本发明的上述方法的一个实施例，其中，形成导电层的步骤进一步包括在凹槽的侧壁之上形成导电层。
附图说明
本发明通过举例加以说明，但并不仅限于这些附图，其中相似的指代数字表示相似的元件。
图1图解了根据本发明一个实施例的包括四个部分的引线框的部分顶视图；
图2图解了根据本发明的一个实施例，图1的引线框在引线键合之后的顶视图；
图3图解了根据本发明一个实施例的图2的剖面图；
图4图解了根据本发明的一个实施例，图2的引线框在形成密封剂之后的顶视图；
图5图解了根据本发明一个实施例的图4的剖面图；
图6图解了根据本发明的一个实施例，图4的引线框在切出一个凹槽之后的顶视图；
图7图解了根据本发明一个实施例的图6的剖面图；
图8图解了根据本发明的一个实施例，图7的引线框在形成导电层之后的顶视图；
图9图解了根据本发明的一个实施例，半导体封装被切单(singulation)之后的剖面图；
图10图解了根据本发明另一个实施例的半导体封装的剖面图；
本领域技术人员能够意识到，附图的图解只是为了简化和明了，并不需要按照比例绘制。例如，附图中的一些尺寸可以相对于其它元件加以放大，以便有助于提高对本发明实施例的理解。
具体实施方式
图1图解的是引线框10的一部分，其包括第一器件部分4、第二器件部分2、第三器件部分8和第四器件部分6。引线框10能够是用于任何封装的引线框，例如四平方无引线(quad-flat no-lead)(QFN)封装，其也被称作微引线框封装(MLF)和块状芯片载体(bump chipcarrier)(BCC)；球栅阵列(BGA)封装；四平方封装(QFP)；或任何其它能够用模制(molding)处理形成的或者通过下文将详细说明的切单处理形成的封装。引线框10能够是任何的导电材料，例如含镍和铁的合金；镍钯等。引线框10能够作为构图的引线框购买而得，其具有已经以期望的图式形成的键合焊垫和接地焊垫。如果购得的引线框10没有期望地形成键合焊垫或接地焊垫，则能够通过构图和腐蚀引线框10形成键合焊垫或接地焊垫。接地焊垫是专门用于将EMI屏蔽、导电层或器件接地的键合焊垫。
尽管图1中只显示了四个器件部分，但是可以存在多得多的器件部分。例如，引线框10可以包括100-200个器件部分。在图示的实施例中，出于制造的简化，每个器件部分具有相同的结构，然而这并不是必需的。
第一器件部分4包括第一标签(flag)(用于接收单元片的第一区域)12，其被第一键合焊垫16和第一接地焊垫17包围。第一标签12并不仅限于图1所示的矩形。相反，第一标签12可以是引线框10内的开放窗口，呈“X形”或类似的形状。而且，第一标签可以相对于引线框10的其它区域被提高或者缩进。在图示实施例中，第一键合焊垫16与第一标签12的侧面平行，第一接地焊垫17位于第一标签12的四个角处。(图中只用数字标记了两组第一键合焊垫16以免使附图混乱。然而，在第一标签12的每个侧面上，第一接地焊垫17之间的全部三个框都是键合焊垫。)此外，本领域技术人员应当意识到，附图中第一键合焊垫16的数目及其配置都只是出于举例的目的。可以存在任何数目的第一键合焊垫16，并且第一标签12的每个侧面都可以具有不同数目的第一键合焊垫16。而且，第一键合焊垫16可以沿着第一标签12的每个侧面彼此交错，或者可以使用任何其它合适的配置。另外，第一接地焊垫17能够具有不同的配置或位置。
第二器件部分2包括第二标签13，其被第二键合焊垫18和第二接地焊垫19包围。第三器件部分8包括第三标签15，其被第三键合焊垫22和第三接地焊垫23包围。类似地，第四器件部分6包括第四标签14，其被第四键合焊垫20和第四接地焊垫21包围。第二、第三和第四标签13、15和14可以是针对第一标签12披露的任何形状。第二、第三和第四键合焊垫18、22和20都与第一键合焊垫16相似，并且能够具有任何类似第一键合焊垫16的配置。(与第一键合焊垫16相似，并不是所有的第二、第三和第四键合焊垫18、22和20都用数字标记以避免使图1混乱)同样地，第二、第三和第四接地焊垫19、23和21都与第一接地焊垫17相似。
从半导体晶片切割半导体单元片，并用拾取和放置工具将其放置在每个标签上，这在工业上是已知的。换言之，第一半导体单元片24、第二半导体单元片25、第三半导体单元片27和第四半导体单元片26分别放置在第一标签12、第二标签13、第三标签14和第一标签15上。在一个实施例中，在每个标签上放置一个半导体单元片。在另一个实施例中，在一个标签上放置超过一个半导体单元片。例如，一个半导体单元片能够与另一个半导体单元片相邻地放置在同一个标签上，或者能够堆叠在另一个半导体单元片的上面而放置在相同的标签上。这样，多个单元片能够在相同的平面内或者彼此堆叠地放置在一个标签上。
第一、第二、第三和第四半导体单元片24-27包括半导体基片和线路，例如晶体管等。半导体基片还包括单元片键合焊垫，通过它，半导体单元片的单元片键合焊垫和围绕每个标签的键合焊垫之间实现引线键合。这样，第一半导体单元片24与第一键合焊垫16电耦连。在一个实施例中，电耦连通过第一引线键合28实现。同样地，第二半导体单元片25、第三半导体单元片27和第四半导体单元片26的每一个分别与第二键合焊垫18、第三键合焊垫20和第四键合焊垫22电耦连。在一个实施例中，电耦连分别通过第一、第二和第三半导体单元片25-27的第二引线键合29、第三引线键合30和第四引线键合31实现。引线键合28-31可以是任何导电材料，例如金或铝。在一个实施例中，每个引线键合28-31的直径大约为1/1,000-1/2,000英寸，其大约是人头发丝直径的1/4。
如果半导体单元片24-27是通过引线键合于键合焊垫16、18、20和22上而电耦连在一起的话，则在相同的引线键合处理期间，相邻器件部分的接地焊垫也可以电耦连在一起。在一个实施例中，耦连的执行是通过用引线键合将接地焊垫彼此引线键合在一起的，该引线键合与如上所述的用于将半导体单元片引线键合于键合焊垫上的引线键合是相同的。然而，如果每一个所用的引线键合在例如直径上不同，则可以使用分离的引线键合处理耦连接地焊垫和键合焊垫。
如图2所示，第一半导体单元片24与第一键合焊垫16电耦连，第二半导体单元片25与第二键合焊垫18电耦连，第三半导体单元片27与第三键合焊垫22电耦连，且第四半导体单元片26与第四键合焊垫20电耦连。而且，与第四器件部分6最接近的两个第一接地焊垫和与第一器件部分4最接近的两个第四接地焊垫电耦连。与第三器件部分8最接近的两个第二接地焊垫和与第二器件部分2最接近的两个第三接地焊垫电耦连。此外，图示中与任何器件部分都不电耦连的接地焊垫17、19、21和23与图中没有给出的器件部分电耦连。
在图2所示的实施例中，一个器件部分的每个接地焊垫都与相邻器件部分的一个接地焊垫电耦连，从而形成接地的电连接或接地引线键合32。因为接地引线键合32较细，所以它们在随后的模制密封处理期间能够崩塌或毁坏。通过将接地引线键合32沿着在随后的模制处理期间模制密封剂的流动方向加以排列，接地引线键合32更有可能保持其形状而不会崩塌。相反，如果模制封装材料与接地引线键合32成90度角流动，那么接地引线键合32很可能会崩塌。图2所示实施例中的接地引线键合32仅耦连彼此垂直相邻的器件部分，因为模制密封剂将从引线框10的顶部流向底部，或者相反。图示的实施例只是用于举例说明，并不对接地引线键合32的配置或密封剂的流动方向具有限制。例如，特别地，如果模制密封剂沿着横向方向流过器件，那么接地引线键合32可以耦连彼此横向或水平相邻的器件部分。为了避免上述与细引线键合以及模制物的流动方向有关的问题，可以使用粗的引线键合，但其不利的一方面是会使成本增加。尽管附图中显示的接地引线键合沿着一个方向，但是接地引线键合能够同时沿着多个方向，例如同时沿水平和垂直方向。在一个实施例中，接地焊垫可以具有多个引线键合，每个引线键合与不同的器件部分耦连。
图3图解了第二器件部分2和第四器件部分8的剖面图。尽管在图3中只图解了一部分引线键合，但是也可以存在其它的引线键合，用于将标签与引线框10的其它部分电耦连，虽然它们并没有被显示出来。此外，在图3中，引线框10显示为各种碎片。然而，本领域技术人员会意识到，图3中引线框10的碎片能够通过分度(indexing)、标签、引线、坝形棒(dam bar)、束结(tie-in)、诸如此类及上述的组合等耦连在一起。然而，为了避免使附图复杂化，没有显示引线框的所有部分(例如坝形棒)。
在图3中，第二器件部分2和第四器件部分8通过接地引线键合32电耦连。图示中，其中一个第二引线键合29将第二半导体单元片25电耦连于第二标签13，其中一个第四引线键合31将第三半导体单元片27电耦连于第四标签15。
如图4所示，在引线键合或电耦连半导体单元片、标签和接地引线之后，执行密封处理，用模制化合物或模制密封剂覆盖器件部分。虚线34表示模制密封剂的周界。然而，本领域技术人员会意识到，如果除了图示的四个器件部分之外，还存在其它的器件部分，那么模型的直径将延伸超过图示的四个器件部分，并覆盖其它的器件部分。模制密封剂可以是硅石填充树脂、陶瓷、无卤化物材料、诸如此类或上述的组合。模制密封剂典型地以液体状态施加，然后通过加热在UV或周围气氛中固化从而形成固体。密封剂也还能够是固体，加热使之形成液体，然后在引线框上方冷却形成固体模型。还可以使用其它的密封处理。
为了随后在接地引线键合上切割凹槽，如下文将更详细说明的，密封处理应当包括接地引线键合，这能够通过模制整个引线框10而容易地实现，正如在许多封装处理中，例如QFN处理，通常都会执行的那样。图5中第二器件部分2和第四器件部分8在密封之后的剖面图图解了模制密封剂35，其至少覆盖接地引线键合32和相关的器件部分2和8。
在密封之后，切割接地引线键合32。图6中的线条39图解了切割所遵循的线路，并且图7图解了通过在第二器件部分2和第四器件部分8之间进行切割获得的凹槽40的剖面图，其将接地引线键合32分成2个接地引线33。切割能够用具有切割刃具的锯或其它能够如下所述地分割引线键合的装置加以执行。优选地，切割刃具具有一个角度，其取决于切割深度，该深度小于模制密封剂或器件(或封装)自身部分的高度。切割的深度应当使引线键合与随后形成的覆盖导电层相接触，并且与位于器件部分底部的键合焊垫隔离。如果封装切割角度相对于器件部分足够宽，则会不利地获得金字塔形的而不是三角形的切口(或者基本上“V”形的切口或基本上“V”形的凹槽)，如图7所示。(浅)金字塔形切口会干扰或损坏器件部分内部的部件，从而使得没有空间用于使用编码对器件部分进行标记，这个步骤典型地在处理流程的后续步骤中执行。金字塔形结构还使得难以对器件部分进行测试。对于大约80mill的深度，合适的切锯刃具尖端的角度为70度。优选地，凹槽40的侧壁倾斜，从而在随后的在凹槽40上沉积导电层的处理期间，导电层将覆盖凹槽40的侧壁。凹槽不应当延伸通过整个引线框10，否则随后的导电层将覆盖凹槽的侧壁，从而与顺次连接导电层的封装引线产生短路。向引线框切割得太深还会危害引线框的机械整体性，并且使得在制造环境中难以应对或者处理。
图8图解了导电层42的沉积。导电层42能够是聚合物、金属、金属合金(例如铁磁或铁电材料)、油墨(ink)、诸如此类或上述的组合。在一个实施例中，导电层是铝(Al)、铜(Cu)、镍铁(NiFe)、锡(Sn)、锌(Zn)、诸如此类或上述的组合。如果导电层42是非铁材料(例如Al，Cu，Sn和Zn)，那么导电层42和接地引线33能够通过将半导体单元片13和15经由接地引线32连接于导电层42使之接地来保护器件部分免受EMI的干扰。如果使用铁磁材料(例如NiFe)，那么导电层42将保护器件部分免受磁辐射的干扰，这在半导体单元片13和15包含磁随机存储器(MRAM)时是有用的。(因此，如果不需要防止主要电磁辐射的干扰，则不需要接地引线33)然而，如果同时使用非铁磁材料和铁磁材料(例如铜层和NiFe层)形成导电层42，则用电磁或宽带屏蔽来保护器件部分免于同时含有电和磁的电磁场的影响，这在例如半导体器件13和15同时含有MRAM器件和晶体管时是有用的。
为了沉积导电层42，制备模制密封剂32的表面，以便将导电层42粘着于模制密封剂35。在一个实施例中，如果导电层42被焊垫印刷(pad printed)，则使用氢焰烧去可能存在的任何有机物(也就是火焰烧除(flame-off))来制备导电层。选择地，可以执行任何其它的处理，包括不处理，来制备模制密封剂35的表面。
导电层42能够通过如下方法加以沉积：物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电解电镀、化学镀层、火焰喷涂、导电漆喷涂、真空金属喷镀、焊垫印刷、诸如此类或上述的组合。导电层42的厚度优选地为X-Y单位，更优选地厚度为1-50微米；导电层42的厚度取决于期望的屏蔽效力。导电层42的最小厚度取决于用于形成导电层42的处理，最大厚度取决于导电层42的应力大小，其至少是所用材料的函数。
在沉积或施加了导电层42之后，使每个器件部分彼此分离。换言之，将每个器件部分切割或锯割成单个的器件部分。在一个实施例中，切割是在每个凹槽的顶点执行的。图8中的虚线43显示了使器件部分切单的位置。(换言之，虚线43主要是凹槽顶点的连线。)
图9图解了切单的第二器件部分2，其在第二半导体单元片13的每个侧面上具有一个接地引线33。一旦被切单，第二器件部分2便成为一个半导体封装。在图1-8中，第二器件部分2只显示了一个接地引线33，因为分享其它接地引线键合32(未显示)的器件部分没有被显示出来。相反，出于简单起见，只显示了4个器件部分。除非第二器件部分2位于引线框10的拐角或边缘，否则第二器件部分2很可能具有至少两个接地引线33，从而在半导体单元片13的每一侧上至少有一个，如图9所示。如果第二器件部分2的所有侧面都被其它器件部分包围，则第二器件部分2将很可能具有4个接地引线33(每个角一个)。附图1-8的顶视图中显示，两个接地引线键合32将第二器件部分2电连接于第四器件部分8。因此，若在第二器件部分2的另一侧上有另一个器件部分，则将还有两个接地引线键合将接地焊垫19(位于简图的顶部)电耦连于相邻的器件部分(未显示)，其在第二器件部分2的上面并且也在简图的顶部。
因为第二器件部分2具有两个接地引线33，所以也要对凹槽进行切割以形成两个接地引线33，因此凹槽将在半导体单元片13的某个侧面上被切割，并且两个凹槽的侧壁将被导电层覆盖。因此，在本实施例中，在每个凹槽的顶点进行切单之后，第二器件部分2的侧壁或两端是倾斜的，因为它们是凹槽的(倾斜的)侧壁。
尽管，如上所述，接地引线键合32使不同器件部分的接地焊垫彼此电耦连，但是不必将接地引线键合32电耦连于接地焊垫以提供EMI保护。如果键合焊垫的布局、半导体单元片的大小和标签的大小允许的话，则接地引线键合32能够耦连任何未使用的接地的或者即将被接地的而不是已经接地的键合焊垫。换言之，如果在将器件部分切单成一个封装并附着到印刷电路板(PCB)上时，未使用的键合焊垫是接地的或者随后将被接地的，那么接地的键合焊垫能够是任何未使用的键合焊垫。大体上，一个器件部分的任何接地部分都能够通过接地引线键合32与另一个器件部分的接地部分电耦连，另一个器件部分优选的是相邻的器件部分。此外，通过接地引线键合32电耦连在一起的导电部分不需要是相同类型的导电部分。例如，接地引线键合32可以将一个器件部分的接地键合焊垫电耦连于另一个器件部分的键合焊垫。然而，耦连不同类型的导电部分会增加处理的复杂性，因此不是理想的。
图10图解了屏蔽EMI和/或电磁辐射的另一个实施例。在该实施例中，接地引线61电耦连于接地平面，并且形成一个延伸到封装外部的环。封装50包括引线框52，该引线框包括键合焊垫51和标签53，作为引线框52的一部分。在一个实施例中，封装50包括一个传感器件。在标签53上形成第一半导体单元片54，其包括一个执行ASIC功能的电路，例如传感器或传感单元片。第一半导体单元片54通过第一引线键合58电耦连于键合焊垫51。然后在第一半导体单元片54上形成隔件55，从而允许在第一半导体单元片54上堆叠一个更大的半导体单元片(第二半导体单元片57)。隔件55允许使更大的半导体单元片，其在一个实施例中是一个传感单元片，位于第一半导体单元片54的引线键合58的上面。如果器件寄生效应成为问题，隔件55还能够增加第一半导体单元片54和更大的半导体单元片之间的分离。第二半导体单元片57通过第二引线键合59电耦连于第一半导体单元片54。在图10所示的实施例中，第二半导体单元片57是一个传感单元片，并用硅帽晶片通过玻璃粉焊接加以保护。该焊接是在将半导体单元片57切割成位于晶片上的彼此分离的单个单元片之前，在晶片水平上实现的。第三引线键合60将第二半导体单元片57的第一部分耦连于第二半导体单元片57的第二部分。如果将第二半导体单元片57和第一单元片55整合成一个同时具有例如ASIC和传感功能的单元片，则不需要隔件55。图10中半导体单元片的配置是例证性的。封装50可以具有一个或多个单元片，这些单元片位于标签上，处于相同的平面内或者彼此堆叠。在第三半导体单元片57上形成接地引线键合61，并使之形成一个环。所有的引线键合都能够是任何材料，并具有前述引线键合的所有特征。
在半导体单元片、引线框52和引线键合上方形成模制密封剂62，其能够是任何模制密封剂，例如上面所提到的。在形成模制密封剂62之后，执行去覆盖(deflash)或清洗以暴露接地引线键合61。可以采用任何传统的去覆盖或清洗处理。去覆盖处理可以包括无处理、化学处理、高压水处理或机械处理。
在暴露接地引线键合61的一部分之后，在模制密封剂62和接地引线键合61暴露部分的上面形成导电层64，其能够是上面关于导电层42讨论的任何材料。换言之，保持接地的导电层和标签52形成MEI或电磁屏蔽，其取决于用于导电层62的材料。从而，接地引线键合61耦连导电层64，借此实现接地。图10所示的半导体封装50通过在形成导电层64之后将封装切单而形成。
其它的实施例也能够用于形成EMI和/或电磁屏蔽。例如，能够将具有已成形引线的金属标板(metallic tab)通过粘合剂附着到封装的上表面。在一个实施例中，金属标板完全覆盖封装的顶部，并且金属标板上形成的引线与接地引线连接在一起。根据本实施例，印刷电路板(PCB)可以延长一些，用于容纳即将接地的金属标板的已成形引线。用于金属标板的材料能够和用于导电层42和64的相同。
在另一个实施例中，在附着到引线框标签上的半导体单元片上形成金属化的表面，其在一个实施例中用标准倒装晶片处理加以执行。金属化的基片应当完全覆盖半导体单元片。换言之，半导体单元片具有第一宽度和第一长度，金属化的基片具有第二宽度和第二长度，其中第二宽度等于或大于第一宽度，第二长度等于或大于第一长度。
提供隔件用于消除金属化基片与引线框键合焊垫之间的引线键合。不消除金属化基片与键合焊垫之间的引线键合可能会干扰或者接触到半导体单元片与键合焊垫之间的引线键合。从而，利用堆叠于半导体单元片顶部的接地金属化基片形成内部屏蔽，其中内部屏蔽覆盖半导体单元片上的电路以及，任选地，覆盖键合焊垫上的电路。半导体单元片可以包括任何类型的电路，包括MRAM，RF，微控制器，EPROM和DRAM。如上面所讨论的，如果半导体单元片包括MRAM，那么理想的是，使金属化基片屏蔽磁辐射。另外理想的是，使金属化基片屏蔽EMI，并且在本实施例中，金属化基片可以包括两种不同的同时具有电和磁屏蔽能力的材料。
到现在应当意识到，我们提供了一种处理，其用于在元件水平上形成EMI和/或电磁屏蔽。该处理是理想的，特别是对于QFN，因为该处理的执行可以不需要附加的处理设备。而且，该处理，特别是图1-9中说明的处理，是一种成本效率较高的在元件水平上防止EMI和/或电磁辐射的方法。如果使用接地的引线，则导电层对于成阵列布置的(也就是既没有预先模制也没有单独模制的)封装，例如QFN，是特别有用的。与用各种陶瓷层制造的陶瓷无引线芯片载体(CLCC)相似，预先模制的封装能够通过使上金属帽接地并通过一个通孔(via)将其焊接在下地平面上来防止EMI。在WFN或者其它的在第一侧面上暴露引线框并在第二侧面上模制多个阵列封装(MAP)的封装中，模制化合物覆盖整个第二侧面。因为MAP模制引线框中的各个器件彼此接近，所以在模制处理期间不能够为每一个器件设置单独的帽，并且不能将帽固定在其位置上。如果在模制之前增加相邻器件之间的距离并使用单独的帽，则除了技术上的挑战之外，还会变得非常昂贵。因为设置和固定单独的帽是很困难的，并且会妨碍模制处理本身。由于非预模制封装的处理流程，所以不能使用金属帽。而且，用于在CLCC中设置通孔(via)的处理与在用于形成QFN，BGA等类型封装的模制处理中设置通孔的处理不同。例如，为了在QFN型封装中形成通孔，通孔必须在模制密封剂中形成，这会增加制造成本和复杂性。
因为实现本发明的装置的大部分是由本领域技术人员已知的电子部件和电路构成的，所以除了上面叙述的我们认为是理解本发明的隐含概念所必需的解释之外，不再对电路的细节进行更详细的解释，以免使本发明显得混乱或者使人分心。
在前面的说明书中，我们已经参考特殊的实施例对本发明进行了说明。然而，本领域的普通技术人员会意识到，在不背离由下文权利要求提出的本发明范围的前提下，可以进行各种修饰和改变。因此，说明书和附图应当只看作是举例，而没有限制性意义，并且所有这些修饰都包含在本发明的范围之内。
尽管本发明是参考具有特殊导电类型或者极性的事物说明的，但是本领域技术人员会意识到，导电类型和电压极性可以是相反的。
上面参考特殊实施例说明了本发明的优点、其它优势和解决问题的方法。然而，这些优点、优势、或解决问题的方法以及任何可以导致任何其它优点、优势、解决方法出现或者更加明了的因素都不应当理解认为是任何或全部权利要求重要的、必需的或基本的特征或元素。如本文所使用的，术语“包括”、“由......构成”或其任何其它的变化都试图覆盖非排它性的内涵，例如处理、方法、物件或装置，它们所包含的元素的列表并不只是包括这些元素，而是可以包括其它没有表达列举的元素或者属于该处理、方法、物件或装置固有的元素。本文使用的术语“一个”或“某一个”都定义为一个或超过一个。本文使用的术语“多个”定义为两个或超过两个。本文所用的术语“另一个”定义为至少第二个或者更多个。本文使用的术语“耦连”定义为连接，其不必是直接地，也不必是是机械地。而且，说明书和权利要求中的术语“前”、“后”、“上”、“下”、“上方”、“下方”等都是出于描述的目的，并不是说明将永久地处于该相对位置。应当理解，如此使用的术语在合适的情况下是可以互换的，例如这里所说明的本发明的实施例能够以这里没有图解的或者相反的方位工作。

Claims (9)

1.一种半导体封装，包括：
引线框，其具有标签和键合焊垫；
半导体单元片，其附着到标签上并与键合焊垫电耦连；
模制密封剂，其位于半导体单元片之上，其中模制密封剂具有凹槽；
导电层，其位于模制密封剂之上；以及
引线，其将引线框电耦连于凹槽中的导电层。
2.根据权利要求1的半导体封装，其中导电层包含铁磁材料。
3.根据权利要求1的半导体封装，其中引线通过半导体单元片和引线键合耦连于引线框。
4.根据权利要求1的半导体封装，其中引线通过焊垫耦连于引线框。
5.根据权利要求1的半导体封装，其中导电层是一个电磁屏蔽。
6.一种形成半导体封装的方法，该方法包括：
提供引线框，该引线框具有标签、第一接地焊垫、和第二接地焊垫；
将半导体单元片附着到标签；
在半导体单元片之上形成模制密封剂；
在模制密封剂之上形成导电层；以及
使用引线将引线框电耦连于导电层，
其中，使用引线将引线框电耦连于导电层的步骤进一步包括：
提供具有第一端和第二端的引线；
将第一端电耦连于第一接地焊垫，将第二端电耦连于第二接地焊垫；以及
除去模制密封剂的一部分以暴露引线的一部分；
其中，形成导电层的步骤进一步包括：
将导电层电耦连于引线。
7.根据权利要求6的方法，其中，在半导体单元片之上形成模制密封剂的步骤进一步包括在引线上形成模制密封剂。
8.根据权利要求7的方法，其中，除去模制密封剂的一部分以暴露引线的一部分的步骤进一步包括在模制密封剂中形成凹槽，其中凹槽具有侧壁。
9.根据权利要求8的方法，其中，形成导电层的步骤进一步包括在凹槽的侧壁之上形成导电层。
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