CN100553136C - Circuit for controlling and allocating embryonic hardware reconfiguration - Google Patents
Circuit for controlling and allocating embryonic hardware reconfiguration Download PDFInfo
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- CN100553136C CN100553136C CNB2007100218266A CN200710021826A CN100553136C CN 100553136 C CN100553136 C CN 100553136C CN B2007100218266 A CNB2007100218266 A CN B2007100218266A CN 200710021826 A CN200710021826 A CN 200710021826A CN 100553136 C CN100553136 C CN 100553136C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
Abstract
The present invention relates to a kind of circuit for controlling and allocating embryonic hardware reconfiguration, with MUX tree MuxTree is that basic primitive unit cell constitutes the embryonic array circuit, and wherein the basic primitive unit cell of each MUX tree MuxTree is made up of programmable functions module (FU), switch module (SB) and memory cell (CREG).Programmable functions module (FU) comprises that mainly 2 select MUX and a D flip-flop (F) of realizing the behavior of clock sequential of 1; Switch module (SB) provides the interconnection between the output bus of the output (NOUT) of the input bus of all directions four directions, basic primitive unit cell and all directions four direction.Circuit for controlling and allocating embryonic hardware reconfiguration of the present invention can be configured to the configuration bit string in the corresponding array element like clockwork, realized the logic function of mould 4 countings, and spended time is few, satisfies the real-time requirement of configuration fully.
Description
Technical field
The present invention relates to a kind of Reconfigurable Control configuration circuit, more particularly relate to a kind of circuit for controlling and allocating embryonic hardware reconfiguration, belong to areas of information technology.
Background technology
The complexity of digital system increases, but its controllability and reliability are not improved accordingly, and therefore, people have proposed fault is carried out the requirement of dynamic self-checking survey, selfreparing, and strive to find new fault tolerant systems design method.Be subjected to the inspiration of biological characteristics such as the growth development, organism selfreparing of embryonic cell, individual study, population genetic evolutionary mechanism, scholars have proposed a kind of novel hardware of many cells organizational framework structure of mimic biology body, i.e. embryonic hardware.And as an important component part of embryonic hardware, be that reconstruct control configuration circuit plays control core configuration effect in the embryonic hardware restructuring procedure, be mainly used to realize and correctly be configured in corresponding embryo's array element through the chromosome (configuration bit string) that evolution algorithm obtains, thereby finally realize the selfreparing of embryonic hardware, the fault tolerance of self-replication.Both at home and abroad for having carried out some more deep researchs based on the circuit architecture of the embryonic hardware of the heuristic thought of bionical biology, the formation and the working mechanism of inner main circuit, and obtained certain achievement in research, but for the work of being done with the design studies aspect of the reconstruct control configuration circuit of embryonic circuit main circuit collaborative work and few.When introducing the internal structure of on-site programmable gate array FPGA, the Jonathan Rose assistant professor of University of Toronto's electrical engineering and Alberto professor Sangiovanni-Vincentilli of University of California's electrical engineering and computer science study with regard to aufbauprinciple aspect of its control configuration circuit.CornellUniversity university John Teifel and Rajit Manohar electric and computer engineering institute discuss with regard to the security reliability problem that how to guarantee FPGA configuration data bit stream.At home, the research to embryo's electronics still is in the starting stage.Some better simply researchs are being done by colleges and universities such as Wuhan University, Xian Electronics Science and Technology University and Northeastern University aspect the structural design of on-site programmable gate array FPGA and control circuit, but do not obtain substantial progress.School of Information Technology of Shenzhen University EDA center has been done some preliminary researchs to functional module based on the Reconfigurable Control configuration principle of internal structure, operation principle and the FPGA of the embryonic array of MUX structure.Do not provide in the existing in a word document a kind of in embryonic hardware practicable reconstruct control configuration circuit, all be only to have done some preliminary researchs, can not obtain good effect in actual applications.
Summary of the invention
The object of the present invention is to provide a kind of in embryonic hardware practicable reconstruct control configuration circuit, for the embryonic hardware towards abominable applied environments such as deep spaces provides a kind of accurately real-time reconstruct control configuration circuit that has.
For achieving the above object, the present invention is achieved by the following technical solutions:
Circuit for controlling and allocating embryonic hardware reconfiguration of the present invention is on the basis to the functional study of orderly binary decision diagram OBDD and MUX tree MuxTree, be subjected to the inspiration of binary decision diagram OBDD design feature, having invented with MUX tree MuxTree is the circuit for controlling and allocating embryonic hardware reconfiguration of basic primitive unit cell.
A kind of circuit for controlling and allocating embryonic hardware reconfiguration, with MUX tree MuxTree is that basic primitive unit cell constitutes the embryonic array circuit, and wherein the basic primitive unit cell of each MUX tree MuxTree is made up of programmable functions module FU, switch module SB and memory cell CREG; Described programmable functions module FU comprises test module TB, memory module MB, link block CB, output module OB, link block CB comprises two 8 and selects 1 MUX M3 and M4, under the control of three control variables LEFT2:0 and RIGHT2:0 was selected, each chose the left and right sides branch that a signal output offers the main MUX M0 among the test module TB in 8 input signals respectively for it; Described 8 input signals are respectively from left to right: constant logical value 0, constant logical value 1, basic primitive unit cell input SIN in the south, the input EIN of the basic primitive unit cell of the southeast, the input WIN of the basic primitive unit cell of southwest face, the output of D flip-flop F, long apart from connecting line SIB and long apart from connecting line SOB.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration, it is characterized in that described test module TB comprises main MUX M0 and MUX M1, described MUX M1 selects a bus signals to control main MUX M0 as control signal from east bus EOBUS and EIBUS.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration is characterized in that described output module OB comprises one 2 and selects 1 MUX M2, and it links to each other with the output of main MUX M0, also links to each other with D flip-flop F output northwards.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration, it is characterized in that described 2 select the input that also is connected with field-programmable configuration signal REG on the 1 MUX M2, it controls the combination or the sequential behavior of basic primitive unit cell: the output NOUT of this basic primitive unit cell selects one for use in two sources, this depends on that 2 among the output module OB selects the value of the field-programmable configuration signal REG of 1 MUX M2, if this basic primitive unit cell is combinational circuit purely, then field-programmable configuration signal REG equals 0, and output NOUT 2 selects the output of 1 MUX; On the other hand, if this basic primitive unit cell needs the performance of a sequential, then field-programmable configuration signal REG equals 1, and output NOUT is the output of D flip-flop F.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration is characterized in that described memory module MB includes D flip-flop F, selects the output of 1 MUX in the rising edge of work clock CK storage 2, and its clock signal period is determined by Application Design itself.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration is characterized in that described memory module MB also is connected with field-programmable position PRESET input, and its decision initialize signal INIT carries out asynchronous set PR or reset operation CLR to D flip-flop.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration is characterized in that described switch module SB provides input bus EIBUS, SIBUS, WIBUS and the NIBUS of all directions four directions, the output NOUT of basic primitive unit cell and output bus EOBUS, the SOBUS of all directions four direction, the interconnection between WOBUS, the NOBUS.
Aforesaid circuit for controlling and allocating embryonic hardware reconfiguration is characterized in that the output NOUT of described basic primitive unit cell always links to each other with four output buss, and it selects 1 MUX to realize by four 4; Described 4 select 1 MUX, and each is controlled with two configuration signal, selects a signal output from the output NOUT of the input bus of other three directions and basic primitive unit cell.
The invention has the beneficial effects as follows: design circuit of the present invention has been realized disposing bit string practically and has been configured to like clockwork in the corresponding array element, has realized the logic function of mould 4 countings, and satisfies the real-time requirement of configuration.
Description of drawings
Fig. 1 is the basic structure block diagram of the basic primitive unit cell of MUX tree MuxTree among the present invention;
Fig. 2 is the structured flowchart that the MUX among the present invention is set the programmable functions module FU in the basic primitive unit cell of MuxTree;
Fig. 3 is the structured flowchart of the switch module SB of the basic primitive unit cell medium and long distance connection of MUX tree MuxTree among the present invention;
Fig. 4 is the inside realization figure of switch module SB shown in Figure 3.
Embodiment
Describe the present invention with reference to the accompanying drawings in detail:
Circuit for controlling and allocating embryonic hardware reconfiguration of the present invention is to set the embryonic array circuit (for example 3 * 4 arrays) that MuxTree is basic primitive unit cell formation with MUX, and wherein the basic primitive unit cell of each MuxTree mainly is made of three parts.Fig. 1 is the basic structure block diagram of the basic primitive unit cell of MUX tree MuxTree among the present invention, and as shown in Figure 1, the basic structure of the basic primitive unit cell of MUX tree MuxTree mainly comprises: programmable functions module FU; Switch module SB, it provides the input bus EIBUS of all directions four directions, SIBUS, WIBUS, NIBUS, the output NOUT of basic primitive unit cell (or cell unit) and the output bus EOBUS of all directions four direction, SOBUS, WOBUS, the interconnection between the NOBUS; Store the memory cell CREG of basic primitive unit cell configuration information.
Fig. 2 is the structured flowchart that the MUX among the present invention is set the programmable functions module FU in the basic primitive unit cell of MuxTree, as shown in Figure 2, programmable functions module FU comprises that mainly one 2 is selected MUX (at the bottom of test module TB) and a D flip-flop (in memory module MB) of realizing the behavior of clock sequential of 1 in the basic primitive unit cell of each MUX tree MuxTree of the present invention.Programmable functions module FU selects 1 MUX M3 and M4 to realize being connected with the input of main MUX M0 by two 8 among the link block CB.MUX M1 in test module TB selects a bus signals to control main MUX M0 as control signal from east bus EOBUS and EIBUS.Among the output module OB 2 selects 1 MUX M2 to link to each other with the output of main MUX M0, and in addition, it can also link to each other with trigger output NOUT northwards.
In addition, field-programmable configuration signal REG among the output module OB among Fig. 2 controls the combination or the sequential behavior of basic primitive unit cell, and the decision of the field-programmable position PRESET among memory module MB initialize signal INIT carries out asynchronous set PR or reset operation CLR to trigger.
This basic primitive unit cell output NOUT northwards can select one for use in two sources, this depends on the value of the field-programmable configuration signal REG of the MUX M2 among the output module OB.If this elementary cell is combinational circuit purely, then REG equals 0, and NOUT is the output of MUX.On the other hand, if this elementary cell needs the performance of a sequential, then REG equals 1, and NOUT is the output of D flip-flop F.
As shown in Figure 2, the D flip-flop F among the programmable functions module FU is used to realize the behavior of clock sequential, and its effect is in the output of the rising edge of work clock CK storage MUX, realizes specific logic function.This clock signal period is determined by Application Design itself.Field-programmable position PRESET allows the default value of user definition D flip-flop F, and this value is kept among the initialize signal INIT.
Again as shown in Figure 2, two 8 in link block CB are selected 1 MUX M3 and M4, under the control of three control variables LEFT2:0 and RIGHT2:0 was selected, each chose the left and right sides branch that a signal output offers the main MUX M0 among the test module TB in 8 input signals respectively.8 signals of among the link block CB this are respectively from left to right: constant logical value 0, constant logical value 1, basic primitive unit cell input SIN in the south, the input EIN of the basic primitive unit cell of the southeast, the input WIN of the basic primitive unit cell of southwest face, the output of D flip-flop F, long apart from connecting line SIB and long apart from connecting line SOB.This basic primitive unit cell also comprises the output EOUT of the basic primitive unit cell of the southeast and the output WOUT of the basic primitive unit cell of southwestern face in addition.
In order to realize remote connection, in the basic primitive unit cell of each MUX tree MuxTree, comprise a switch module SB.Fig. 3 is the structured flowchart of the switch module SB of the basic primitive unit cell medium and long distance connection of MUX tree MuxTree among the present invention, and switch module SB provides the annexation between embryo's array element, has realized the telecommunication between the cell unit.Fig. 3 is the schematic diagram of four inputs and four output interconnection, and all connections all are possible among the figure, except the U type connects.Fig. 4 is the inside realization figure of switch module SB shown in Figure 3.As can be seen from Figure 3, basic primitive unit cell output NOUT northwards always links to each other with four output buss, selects 1 MUX to realize with four 4.Each MUX (is selected a signal output with two configuration signal E1:0 controls of basic primitive unit cell from these four possible inputs the output NOUT of the input bus of other direction and basic primitive unit cell.
In the basic primitive unit cell of MUX tree MuxTree, have two to overlap independently connection line.A fixedly short distance connection line (the heavy black line part among Fig. 1) that communicates usefulness between adjacent elementary cell, one is the able to programme remote connection line (the lead fine rule part among Fig. 1) that communicates usefulness between elementary cell far away.Obviously, (can not be changed by the configuration signal of basic primitive unit cell) of fixing short distance has connected net structure definite communication structure: each elementary cell can have access to its south, the southeast, the output of southwestern adjacent cells, and its output is sent to its north, northeast, the adjacent cells of northwest.
The linkage function that fixing short distance syndeton can realize is very limited, in order to realize carrying out telecommunication with the fixed outside network, adopted remote connection network, this connection line (lead fine rule part among Fig. 1) fully and first kind connection line separately, it makes the output of elementary cell can be sent in its other adjacent elementary cell of getting along well and goes.
Should connect network at a distance provides an incoming line and an output line respectively on four basic orientation, i.e. SIB in Fig. 1, NIB, four incoming lines of EIB, WIB and SOB, NOB, four output lines of EOB, WOB.Determine by switch module SB that by the signal that these transmission lines transmitted this switch module is by the configuration signal control of elementary cell.
This switch module itself is made of simply four multiplexing: each output all is the output valve of being selected a circuit by four of two configuration signal controls.Each output (for example EOB) can be one of incoming line from other three basic orientation (being WIB, SIB or NIB), or the output NOUT of this basic primitive unit cell.Connection between any two basic primitive unit cells in array can be handled by intervenient switch module, can connect at a distance when keeping the array homogeneity like this.The purposes of remote connection line be the output signal NOUT with basic primitive unit cell be sent to those by the short range network inaccessible to the target primitive unit cell in.These values can be as the input signal (by SIB and SOB) of MUX, perhaps as the control variables (by EIB and EOB circuit) of MUX.
The method for designing of utilizing VHDL language and circuit diagram to combine in Xilinx Foundation FPGA development system has been carried out emulation to this Array Model.Simulation result shows that embryo's electronics reconstruct control configuration circuit of the present invention can be configured to the configuration bit string in the corresponding array element like clockwork, has realized the logic function of mould 4 countings.From starting array element configuration beginning is finished until whole configurations, only use takes the time of 2.44 μ s, satisfies the real-time requirement of configuration fully.
The foregoing description does not limit the present invention in any form, and all technical schemes that mode obtained of taking to be equal to replacement or equivalent transformation all drop in protection scope of the present invention.
Claims (8)
1, circuit for controlling and allocating embryonic hardware reconfiguration is that basic primitive unit cell constitutes the embryonic array circuit with the MUX tree, and wherein each MUX is set basic primitive unit cell and is made up of programmable functions module, switch module and memory cell; Described programmable functions module comprises: test module, memory module, link block, output module, link block comprises that two 8 are selected 1 MUX, under the control of three control variables was selected, each chose the left and right sides branch that a signal output offers the main MUX in the test module in 8 input signals respectively for it; Described 8 input signals are respectively from left to right: constant logical value 0, and constant logical value 1, basic primitive unit cell input in the south, the input of the basic primitive unit cell of the southeast, the input of the basic primitive unit cell of southwestern face, the output of D flip-flop, two are long apart from connecting line.
2, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 1, it is characterized in that described test module comprises main MUX and MUX, described MUX selects a bus signals to control main MUX as control signal the bus in the east from two.
3, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 1 is characterized in that described output module comprises that one 2 is selected 1 MUX, and it links to each other with the output of main MUX, also links to each other with D flip-flop output northwards.
4, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 3, it is characterized in that described 2 select the input that also is connected with the field-programmable configuration signal on 1 MUX, it controls the combination or the sequential behavior of basic primitive unit cell: the output of this basic primitive unit cell is selected one for use in two sources, this depends on that 2 in the output module selects the value of the field-programmable configuration signal of 1 MUX, if this basic primitive unit cell is combinational circuit purely, then the field-programmable configuration signal equals 0, and output is 2 to select the output of 1 MUX; On the other hand, if this basic primitive unit cell needs the performance of a sequential, then the field-programmable configuration signal equals 1, and output is the output of D flip-flop.
5, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 1, it is characterized in that described memory module includes D flip-flop, select the output of 1 MUX in the rising edge of work clock storage 2, its clock signal period is determined by Application Design itself.
6, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 1 or 5 is characterized in that described memory module also is connected with field-programmable position input, and its decision initialize signal is that D flip-flop is carried out asynchronous set or reset operation.
7, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 1 is characterized in that described switch module provides the interconnection between the output bus of the output of the input bus of all directions four directions, basic primitive unit cell and all directions four direction.
8, circuit for controlling and allocating embryonic hardware reconfiguration according to claim 7 is characterized in that the output of described basic primitive unit cell always links to each other with four output buss, and it selects 1 MUX to realize by four 4; Described 4 select 1 MUX, and each is controlled with two configuration signal, selects a signal output from the output of the input bus of other three directions and basic primitive unit cell.
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| CNB2007100218266A CN100553136C (en) | 2007-04-30 | 2007-04-30 | Circuit for controlling and allocating embryonic hardware reconfiguration |
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| CNB2007100218266A CN100553136C (en) | 2007-04-30 | 2007-04-30 | Circuit for controlling and allocating embryonic hardware reconfiguration |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101383188B (en) * | 2008-07-16 | 2011-02-16 | 南京航空航天大学 | Embryo electronic system |
| CN102522979A (en) * | 2011-12-12 | 2012-06-27 | 南京航空航天大学 | Reconfigurable hardware-oriented active fault-tolerant switch block |
| CN106951955B (en) * | 2017-03-09 | 2019-12-17 | 中国人民解放军军械工程学院 | Method for selecting electronic cell number in bus embryo electronic cell array |
| CN113921068B (en) * | 2021-09-28 | 2023-07-14 | 合肥大唐存储科技有限公司 | Register protection circuit |
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