CN100552940C - The lap connected structure of semiconductor component-buried loading board - Google Patents
The lap connected structure of semiconductor component-buried loading board Download PDFInfo
- Publication number
- CN100552940C CN100552940C CNB2005101259067A CN200510125906A CN100552940C CN 100552940 C CN100552940 C CN 100552940C CN B2005101259067 A CNB2005101259067 A CN B2005101259067A CN 200510125906 A CN200510125906 A CN 200510125906A CN 100552940 C CN100552940 C CN 100552940C
- Authority
- CN
- China
- Prior art keywords
- loading
- loading plate
- semiconductor component
- buried
- connected structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The lap connected structure of semiconductor component-buried loading board of the present invention comprises: two loading plates respectively are formed with at least one opening at this loading plate; At least two semiconductor elements are installed in the opening of this loading plate; At least one dielectric layer, be formed at the acting surface of this semiconductor element and surface and at least one conductive blind hole of loading plate, be formed in the perforate of this dielectric layer, at least one line layer is to be formed at this dielectric layer surface, and this line layer is to be electrically connected to the electronic pads of this semiconductor element by this conductive blind hole; The lap connected structure of semiconductor component-buried loading board of the present invention can become the modular construction of a three-dimensional combination, significantly to promote storage volume, and semiconductor element is incorporated in the loading plate to dwindle module size effectively, and can change combination according to user demand elasticity, to form required storage volume.
Description
Technical field
A kind of lap connected structure of semiconductor component-buried loading board is particularly imbedded loading plate about a kind of earlier with semiconductor element, the structure of this loading plate that splices again.
Background technology
Flourish along with electronic industry, electronic product also progresses into multi-functional, high performance R﹠D direction, to satisfy the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), and for asking performance and the capacity that promotes single semiconductor package part, to meet the trend of miniaturization of electronic products, big capacity and high speed, prior art is with multi-chip moduleization (Multi Chip Module with semiconductor package part; MCM) form presents, and this packaging part also can reduce overall package part volume and promote electrical functionality, has become a kind of main flow of encapsulation at present.It is to connect to put at least two semiconductor chips (semiconductor chip) on the chip bearing member of single packaging part, and all be to connect in storehouse (stack) mode to put between each semiconductor chip and the bearing part, this stack type chip package structure has seen the U.S. the 6th, in 798, No. 049 patent cases.
Shown in Figure 1 promptly is the U.S. the 6th; 798; the CDBGA packaging part cutaway view of No. 049 patent case announcement; it is to have on the circuit board 10 of line layer 11 one to be formed with an opening 101; and form a line layer 11 with electric connection pad 11a and wire bond pad 11b (boundpad) in the one side at least of this circuit board 10; in this opening 101 in conjunction with two stacked semiconductor chips 121; 122; and this semiconductor chip 121; be to electrically connect between 122 with weld layer 13 (bounding layer); this semiconductor chip 122 is electrically connected to the wire bond pad 11b of line layer 11 with the electric installation 14 as gold thread again; insert the opening 101 of circuit board 10 again with packing colloid 15; and coating semiconductor chip 121; 122 and electric installation 14; and on the line layer 11 of this circuit board, be formed with an insulating protective layer 16; on this insulating protective layer 16, be formed with a plurality of opening 16a so as to manifesting this electric connection pad 11a; and to form one at the opening 16a of this insulating protective layer 16 be conducting element 17 as the tin ball, to finish packaging process.
Yet, for this type of packaging part, the semiconductor chip 121 and 122 of this storehouse is to engage (Wire bond) mode with routing to be electrically connected to line layer 11, and the structure that routing engages so promptly can't realize compact purpose because of the bank height makes packaging height increase.And must electrically connect with the weld layer 13 that chip-scale connects between this semiconductor chip 121 and 122, promptly this semiconductor chip 121 and 122 must be made the operation of splicing of electric connection earlier in the chip factory, and then deliver to the encapsulation factory encapsulate, make operation comparatively complicated, increased manufacturing cost.
And increase the mode of electrical functionality and modular capability by the mode of storehouse, if will improve performance again, then must carry out storehouse again, thus, except increasing package thickness, and also increase the complexity of line layer 11, and also must increase the quantity of the wire bond pad 11b of line layer 11, in limited or fixing usable floor area, to improve the quantity of line density and wire bond pad 11b, then the circuit board in order to bearing semiconductor chip 121 and 122 must reach the fine rule road, can reach the requirement of thin little encapsulation.But it is limited to reach the effect of dwindling board area by the fine rule road, and the mode by direct stacked semiconductor chip 121,122 increases electrical functionality and modular capability, then limited because of the number of chips of storehouse, and can't expand increase continuously, and also can't reach the purpose of thin little encapsulation.
For asking the raising multi-chip moduleization to connect the density of putting on multilayer circuit board, reduce semiconductor chip and connect the area of putting on multilayer circuit board, and then dwindle the purpose of encapsulation volume, improve storage volume, become the important topic of circuit board industry.
Summary of the invention
For overcoming the disappearance of above-mentioned prior art, main purpose of the present invention is to provide a kind of lap connected structure of semiconductor component-buried loading board, can be with semiconductor component-buried loading board to become a modular construction.
Another purpose of the present invention is to provide a kind of lap connected structure of semiconductor component-buried loading board, and the quantity of elastic registration semiconductor element has combined transformation elasticity preferably according to need.
Another object of the present invention is to provide a kind of lap connected structure of semiconductor component-buried loading board, can dwindle modular volume.
For reaching above-mentioned and other purpose, the lap connected structure of semiconductor component-buried loading board of the present invention comprises: two loading plates respectively be formed with at least one opening at this loading plate, and this loading plate are to splice by an articulamentum to be integral; At least two semiconductor elements are installed in the opening of this loading plate, and wherein, this semiconductor element comprises that the acting surface with a plurality of electronic padses reaches the non-acting surface with respect to this acting surface; At least one dielectric layer is formed at the surface of the acting surface and the loading plate of this semiconductor element, and wherein, at least one perforate is to be formed at this dielectric layer to correspond to this electronic pads top; And at least one conductive blind hole, being formed in the perforate of this dielectric layer, at least one line layer is to be formed at this dielectric layer surface, this line layer is to be electrically connected to the electronic pads of this semiconductor element by this conductive blind hole.Be to splice with an articulamentum between these loading plates, to form a modular structure, different semiconductor element and the quantity of conversion combination to realize the user demand of different conversion, has preferable conversion combined elastic according to need.
Because semiconductor element is connect the opening that places loading plate, this loading plate then splices, form a dielectric layer, line layer and conductive blind hole on the acting surface and the loading plate surface of this semiconductor element again, and this conductive blind hole is electrically connected to the electronic pads of this semiconductor element, become a modular construction of splicing, can exempt in the prior art directly that storehouse causes thickness to increase, and can exempt the disappearance that routing engages (wire bounding), so can reduced volume to realize thin little application target.
Run through at least one plating via (PTH) at this dielectric layer, line layer, articulamentum and at least two loading plates again, the semiconductor element at least two loading plates is electrically connected by line layer and plating via.
The present invention further can form a circuit layer reinforced structure on the surface of this dielectric layer, line layer, and is formed with a plurality of conductive blind holes in this circuit layer reinforced structure being electrically connected to this line layer, and is formed with connection gasket on this circuit layer reinforced structure surface; Have a welding resisting layer on this circuit layer reinforced structure surface again, and this welding resisting layer surface has a plurality of openings, appearing the connection gasket of circuit layer reinforced structure, and form the conducting element that electrically connects this connection gasket at the opening of this welding resisting layer.To constitute one semiconductor element is encapsulated in board structure of circuit in the loading plate.
Wherein this circuit layer reinforced structure comprises dielectric layer, is stacked in the line layer on this dielectric layer and is formed at conductive blind hole in this dielectric layer.
Because this semiconductor element is embedded in the loading plate, and form a dielectric layer, line layer on the acting surface of semiconductor element and loading plate surface and electrically connect the electronic pads of this semiconductor element, become a modular construction, form the circuit layer reinforced structure more thereon, can change combination to form required storage volume according to user demand elasticity.
Description of drawings
Fig. 1 is a United States Patent (USP) the 6th, 798, No. 049 cutaway view;
Embodiment 1 cutaway view of the lap connected structure of Fig. 2 A to Fig. 2 D semiconductor component-buried loading board of the present invention;
Fig. 3 A and Fig. 3 B are embodiment 2 cutaway views of the lap connected structure of semiconductor component-buried loading board of the present invention;
Fig. 4 A and Fig. 4 B are embodiment 3 cutaway views of the lap connected structure of semiconductor component-buried loading board of the present invention;
Fig. 5 A to Fig. 5 D is embodiment 4 cutaway views of the lap connected structure of semiconductor component-buried loading board of the present invention; And
Fig. 6 is embodiment 5 cutaway views of the lap connected structure of semiconductor component-buried loading board of the present invention.
Embodiment
Embodiment 1
See also Fig. 2 A to Fig. 2 C, it is the generalized section of the lap connected structure of semiconductor component-buried loading board of the present invention.
See also Fig. 2 A, at least two loading plates 21 have first surface 21a and second surface 21b, on this loading plate 21, be formed with at least one first and second surperficial 21a that runs through, the opening 21c of 21b, this loading plate 21 is an insulation board or the circuit board with circuit, in these openings 21c, connect and be equipped with at least one semiconductor element 22, it can anchor at semiconductor element 22 in the opening 21c of loading plate 21 by a sticky material (not marking), this semiconductor element 22 is for example formed a kind of in the group by active member or passive device, wherein this active member for example is a memory, this passive device for example is a resistance, electronic component such as electric capacity or inductance, and this semiconductor element 22 has an acting surface 22a and with respect to the non-acting surface 22b of this acting surface, have a plurality of electronic pads 22c on this acting surface 22a, the acting surface 22a of these semiconductor elements 22 is installed among the opening 21c of same loading plate 21 with equidirectional.
See also Fig. 2 B, on the first surface 21a of the acting surface 22a of this semiconductor element 22 and loading plate 21, form a dielectric layer 23, and be formed with a line layer 24 on these dielectric layer 23 surfaces, and this line layer 24 has the conductive blind hole 24a that is formed in the dielectric layer 23, and this conductive blind hole 24a is the electronic pads 22c that is electrically connected to this semiconductor element 22.
See also Fig. 2 C and Fig. 2 D, this is embedded with between at least two loading plates 21 of semiconductor element 22 is to splice with an articulamentum 25, this articulamentum 25 can be an organic adhesion coating, this loading plate 21 is with the splice second surface 21b of another loading plate 21 of second surface 21b, becoming splices up and down in the other direction is integral, shown in Fig. 2 C; Or this loading plate 21 is similarly the structure (figure does not mark) that splices up and down in the other direction with the splice first surface 21a of another loading plate 21 of first surface 21a; Or these loading plates 21 are to splice at the second surface 21b of another loading plate with dielectric layer on the first surface 21a 23 and line layer 24, become equidirectional splicing up and down, shown in Fig. 2 D; And this dielectric layer 23, line layer 24, articulamentum 25 and two loading plates 21 are to run through therebetween with at least one plating via 26, and make this plating via 26 electrically connect line layer 24, make between these semiconductor elements 22 that are embedded in the loading plate 21 and can electrically connect, can become a modular construction.
This semiconductor element 22 is to be embedded among the opening 21c of loading plate 21, can bury a plurality of semiconductor elements 22 in loading plate 21 underground, connects the quantity of putting at loading plate 21 so as to increasing semiconductor element 22, increases its storage volume.Form dielectric layer 23 again and have the line layer 24 of conductive blind hole 24a at the first surface 21a of the acting surface 22a of this semiconductor element 22 and loading plate 21 again, and this conductive blind hole 24a is electrically connected to the electronic pads 22c of this semiconductor element 22, again at least two loading plates 21 are spliced with articulamentum 25 and be integral, and to electroplate via 26 these line layers 24 of connection, can electrically connect the semiconductor element 22 of greater number, and can dwindle whole volume, and can exempt the disappearance of existing directly splice chip and routing joint.
And semiconductor element 22 is embedded in the loading plate 21, and then the loading plate 21 that splices, can does different combinations and change according to need, needing, thereby conversion elasticity is preferably arranged in response to different uses.
Embodiment 2
See also Fig. 3 A and Fig. 3 B, it is the generalized section of the lap connected structure embodiment 2 of semiconductor component-buried loading board of the present invention, difference from Example 1 is that the acting surface of this semiconductor element is to be embedded in the opening of loading plate with different directions in same loading plate.
See also Fig. 3 A, in a plurality of opening 31c of this loading plate 31, insert semiconductor element 32 respectively, it can not anchor at semiconductor element 32 in the opening 31c of loading plate 31 by a sticky material (figure marks), and the acting surface 32a of this semiconductor element 32 is first surface 31a and second surface 31b that selectivity is formed at loading plate 31, makes first and second surface of this loading plate 31 divide 31a, 31b not to have the acting surface 32a of semiconductor element 32.
See also Fig. 3 B, form dielectric layer 33 respectively and have the line layer 34 of conductive blind hole 34a at first and second surperficial 31a, 31b of this loading plate 31 again, and make this conductive blind hole 34a be electrically connected to the electronic pads 32b of this semiconductor element 32, so can make the upper and lower surface of this loading plate 31 have line layer 34 respectively, circuit can be dispersed in the two sides of this loading plate 31.
31 of the loading plates that this two sides has circuit can splice according to need, again to electroplate the line layer 34 that via 36 connects each layer, so as to improving the quantity that semiconductor element 32 electrically connects, improve electrical functionality or increase modular capability, and can dwindle whole volume to realize thin little purpose, and bigger conversion combined elastic can be arranged, to need in response to different uses.
Embodiment 3
See also Fig. 4 A and Fig. 4 B, it is the generalized section of the lap connected structure embodiment 3 of semiconductor component-buried loading board of the present invention, be with the foregoing description difference, the opening 41c of this loading plate 41 is non-running through, and the direction of this opening 41c is first surface 41a or second surface 41b that selectivity is formed at loading plate 41, can in this opening 41c, connect and put semiconductor element 42, make the acting surface 42a of this semiconductor element 42 can be all in the same direction or towards different directions, can be at the acting surface 42a and the loading plate 41 surperficial line layers 44 that form dielectric layers 43 and have conductive blind hole 44a of this semiconductor element 42, and make this conductive blind hole 44a be electrically connected to the electronic pads 42b of this semiconductor element 42, the above-mentioned volume purpose of dwindling integral body of same realization, and bigger conversion combined elastic can be arranged, to need in response to different uses.
Embodiment 4
See also Fig. 5 A to Fig. 5 C, it is the generalized section of the lap connected structure embodiment 4 of semiconductor component-buried loading board of the present invention, be that with the foregoing description difference the opening of this loading plate is non-running through, and alternative first surface and the second surface that is formed at loading plate.
See also Fig. 5 A, on at least two loading plates 51, respectively be formed with at least one nonpenerative opening 51c, and the opening direction of this opening 51c is first surface 51a and second surface 51b that selectivity is formed at loading plate 51, in this opening 51c, connect and be equipped with semiconductor element 52, and the acting surface 52a that this semiconductor element 52 has an electronic pads 52b is that to be exposed to the opening 51c of this loading plate 51 outer and be fixedly arranged in it, makes the upper and lower surface of this loading plate 51 all have the acting surface 52a of semiconductor element 52.
See also Fig. 5 B, form a dielectric layer 53 respectively at first and second surperficial 51a, the 51b of this loading plate 51 and the acting surface 52a of this semiconductor element 52, and be formed with a line layer 54 on these dielectric layer 53 surfaces, and this line layer 54 has the conductive blind hole 54a that is formed in the dielectric layer 53, this conductive blind hole 54a is electrically connected to the electronic pads 52b of this semiconductor element 52, makes first and second surperficial 51a, 51b of this loading plate 51 have line layer 54.
See also Fig. 5 C and Fig. 5 D, this is embedded with between at least two loading plates 51 of semiconductor element 52 is to splice with an articulamentum 55, with with this loading plate 51 with the splice side of second surface 51b of another loading plate 51 of the side of first surface 51a, become equidirectional splicing (shown in Fig. 5 C) up and down; Or with loading plate 51 with the splice side of second surface 51b of another loading plate 51 of the side of second surface 51b, become splice up and down (shown in Fig. 5 D) in the other direction; And this dielectric layer 53, line layer 54, articulamentum 55 and at least two loading plates 51 are to run through therebetween with at least one plating via 56, can electroplate via 56 by this and electrically connect each line layer 54, make between these semiconductor elements 52 that are embedded in the loading plate 51 to electrically connect to become a modular construction.
Embodiment 5
See also Fig. 6, it is the generalized section of the lap connected structure embodiment 5 of semiconductor component-buried loading board of the present invention, be provided with opening 61a at loading plate 61, in this opening 61a, be embedded with semiconductor element 62, and acting surface 62a and loading plate 61 surfaces at semiconductor element 62 are formed with a dielectric layer 63, reach the line layer 64 that has conductive blind hole 64a in the 63 table formation one of this dielectric layer, and this conductive blind hole 64a is electrically connected to the electronic pads 62b of this semiconductor element 62, and, electrically connect these line layers 64 with at least one plating via 66 again with at least one articulamentum 65 loading plate 61 that splices.Structure as shown in the figure provides explanation and uses, but not as limit, becomes above-mentioned various lap connected structure.
Form at least one circuit layer reinforced structure 67 at this line layer 64 and dielectric layer 63 surfaces again, this circuit layer reinforced structure 67 includes dielectric layer 67a, be stacked in the line layer 67b on this dielectric layer 67a and be formed at conductive blind hole 67c among this dielectric layer 67a, and this conductive blind hole 67c is electrically connected to this line layer 64; Has a welding resisting layer 68 on these circuit layer reinforced structure 67 surfaces again, and be positioned at this lap connected structure edge on these welding resisting layer 68 surfaces and have at least one opening 68a, with the line layer 67b that appears circuit layer reinforced structure 67 as the electric connection pad 67d that connects with extraneous conducting element (figure does not mark).
This semiconductor element 62 is embedded among the opening 61a of loading plate 61, and form dielectric layer 63 and line layers 64 at the acting surface 62a of this semiconductor element 62 and loading plate 61 surfaces, splicing then and being formed by connecting with plating via 66 is a modular construction, form circuit layer reinforced structure 67 more thereon, semiconductor element 62 can be encapsulated in the loading plate 61, exempt in the prior art and must engage and the sealing operation by routing, so can reduce manufacturing cost, and semiconductor element 62 directly is embedded in the loading plate 61, can dwindles overall volume to realize thin little purpose.The lap connected structure of semiconductor component-buried loading board of the present invention is semiconductor element to be connect put in the opening of loading plate, this loading plate then splices, form a dielectric layer, line layer and conductive blind hole on the acting surface and the loading plate surface of this semiconductor element again, and this conductive blind hole is electrically connected to the electronic pads of this semiconductor element, become a modular construction of splicing, can exempt in the prior art directly that storehouse causes thickness to increase, and can exempt that routing engages and encapsulation cause can't reduced volume disappearance.Run through at least one plating via (PTH) at this dielectric layer, line layer, articulamentum and at least two loading plates again, the semiconductor element at least two loading plates is electrically connected by line layer and plating via, increase its storage volume.And can change combination to form required storage volume according to user demand elasticity.
Claims (11)
1. the lap connected structure of a semiconductor component-buried loading board is characterized in that, the lap connected structure of this semiconductor component-buried loading board comprises:
Two loading plates respectively are formed with at least one opening at this loading plate, and this loading plate is to splice by an articulamentum to be integral;
At least two semiconductor elements, corresponding respectively and be fixedly installed in the opening of this loading plate respectively, wherein, this semiconductor element comprises acting surface with a plurality of electronic padses and with respect to the non-acting surface of this acting surface;
At least one dielectric layer is formed at the surface of the acting surface and the loading plate of this semiconductor element, and wherein, at least one perforate is to be formed at this dielectric layer to correspond to this electronic pads top; And
At least one conductive blind hole, be formed in the perforate of this dielectric layer, at least one line layer is to be formed at this dielectric layer surface, this line layer is to be electrically connected to the electronic pads of this semiconductor element by this conductive blind hole, at least one plating via runs through this dielectric layer, line layer, articulamentum and two loading plates, to electrically connect described semiconductor element.
2. the lap connected structure of semiconductor component-buried loading board as claimed in claim 1 is characterized in that, this loading plate is an insulation board or the circuit board with circuit.
3. the lap connected structure of semiconductor component-buried loading board as claimed in claim 1 is characterized in that, the opening of this loading plate is one non-ly to run through or run through opening.
4. the lap connected structure of semiconductor component-buried loading board as claimed in claim 3 is characterized in that, this loading plate has first surface and second surface.
5. the lap connected structure of semiconductor component-buried loading board as claimed in claim 4 is characterized in that, the opening of this loading plate is first surface and/or the second surface that is formed at loading plate.
6. the lap connected structure of semiconductor component-buried loading board as claimed in claim 5 is characterized in that, these loading plates are with the splice second surface of another loading plate of a side of first surface, become equidirectional splicing up and down.
7. the lap connected structure of semiconductor component-buried loading board as claimed in claim 5 is characterized in that, these loading plates are that becoming up and down, rightabout splices with the splice side of second surface of another loading plate of a side of second surface.
8. the lap connected structure of semiconductor component-buried loading board as claimed in claim 5 is characterized in that, these loading plates are that becoming up and down, rightabout splices with the splice side of first surface of another loading plate of a side of first surface.
9. the lap connected structure of semiconductor component-buried loading board as claimed in claim 1 is characterized in that, this articulamentum is that an organic sticky material constitutes.
10. the lap connected structure of semiconductor component-buried loading board as claimed in claim 1, it is characterized in that, the surface that the lap connected structure of this semiconductor component-buried loading board also is included in this dielectric layer, line layer forms at least one circuit layer reinforced structure, this circuit layer reinforced structure comprises dielectric layer, be stacked in the line layer on this dielectric layer and be formed at conductive blind hole in this dielectric layer, and this conductive blind hole is electrically connected to this line layer, and is formed with connection gasket on this circuit layer reinforced structure surface.
11. the lap connected structure of semiconductor component-buried loading board as claimed in claim 10, it is characterized in that, the lap connected structure of this semiconductor component-buried loading board also is included in this circuit layer reinforced structure surface and has a welding resisting layer, and this welding resisting layer surface is positioned at this lap connected structure edge and has at least one opening, with the line layer that appears this circuit layer reinforced structure surface as the electric connection pad that connects with other conducting element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101259067A CN100552940C (en) | 2005-11-25 | 2005-11-25 | The lap connected structure of semiconductor component-buried loading board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101259067A CN100552940C (en) | 2005-11-25 | 2005-11-25 | The lap connected structure of semiconductor component-buried loading board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1971904A CN1971904A (en) | 2007-05-30 |
| CN100552940C true CN100552940C (en) | 2009-10-21 |
Family
ID=38112616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101259067A Active CN100552940C (en) | 2005-11-25 | 2005-11-25 | The lap connected structure of semiconductor component-buried loading board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100552940C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI438882B (en) * | 2011-11-01 | 2014-05-21 | Unimicron Technology Corp | Package substrate having embedded capacitors and fabrication method thereof |
| CN103646880A (en) * | 2013-09-29 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging technology based on board-level functional substrate and packaging structure |
| CN107463193B (en) * | 2017-08-30 | 2022-09-09 | 中国医科大学附属第一医院 | Low temperature tissue embedding temperature control system |
-
2005
- 2005-11-25 CN CNB2005101259067A patent/CN100552940C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN1971904A (en) | 2007-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100966684B1 (en) | Semiconductor device and semiconductor module using the same | |
| CN100411172C (en) | Semiconductor device | |
| CN102067310B (en) | Stacking of wafer-level chip scale packages having edge contacts and manufacture method thereof | |
| JP5153099B2 (en) | Laminated structure of support plate with embedded semiconductor element | |
| KR101329355B1 (en) | stack-type semicondoctor package, method of forming the same and electronic system including the same | |
| US20010020735A1 (en) | Semiconductor device | |
| US6469376B2 (en) | Die support structure | |
| KR20010060343A (en) | Semiconductor apparatus and method of fabricating semiconductor apparatus | |
| CN103620778A (en) | Flip-chip, face-up and face-down centerbond memory wirebond assemblies | |
| CN101211901A (en) | Electronic component contained substrate | |
| JP2004505451A (en) | Method for distributed shielding and decoupling of electronic devices with steric interconnections, device thus obtained and method for manufacturing the device | |
| CN101192544B (en) | Semiconductor component buried loading plate splicing structure and its manufacture method | |
| CN102254890A (en) | Stacked semiconductor package and method for manufacturing the same | |
| CN100524736C (en) | A stacking type wafer packaging structure | |
| CN100552940C (en) | The lap connected structure of semiconductor component-buried loading board | |
| KR20080027586A (en) | Semiconductor die module and package and fabricating method of semicondctor package | |
| US6798055B2 (en) | Die support structure | |
| JP5022042B2 (en) | Laminated structure of semiconductor element embedded support substrate and manufacturing method thereof | |
| US20090206460A1 (en) | Intermediate Bond Pad for Stacked Semiconductor Chip Package | |
| JP4083376B2 (en) | Semiconductor module | |
| KR100884986B1 (en) | Semiconductor device and method of fabricating the same | |
| KR100498470B1 (en) | Multi chip package and method for manufacturing the same | |
| KR100947146B1 (en) | Semiconductor package | |
| KR20150116526A (en) | Device of package stacking | |
| CN100539102C (en) | Circuit board is embedded with the electric connection structure of semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |