CN100541458C - The input/output interface of integrated device electronics - Google Patents

The input/output interface of integrated device electronics Download PDF

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Publication number
CN100541458C
CN100541458C CNB2004100348321A CN200410034832A CN100541458C CN 100541458 C CN100541458 C CN 100541458C CN B2004100348321 A CNB2004100348321 A CN B2004100348321A CN 200410034832 A CN200410034832 A CN 200410034832A CN 100541458 C CN100541458 C CN 100541458C
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signal
base level
terminal
base
level coding
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CN1551224A (en
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张星珍
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

The present invention relates to integrated circuit fields.Technical matters to be solved comprises: prior art occupies bigger device area unfriendly in interpolation any aspect the number of data pin, and has also increased power consumption and the noise relevant with power supply.The invention provides a kind of integrated circuit, it comprises: M the first terminal and N second terminal, M and N are positive integers, and M＞N＞1.This circuit also comprises: converter, and it receives M A base level input signal from M the first terminal respectively, and coding is by each A of M A base level input signal MThe different K base value of value for being represented by N K base level output signal, A and K are positive integers, and K＞A＞1.Then, converter is exported N K base level output signal respectively to N second terminal.According to the present invention, the data pin of integrated circuit is reduced, and the occupied area of circuit arrangement can reduce, thereby has also reduced power consumption and the noise relevant with power supply.

Description

The input/output interface of integrated device electronics
Technical field
The present invention relates generally to integrated device electronics, the invention particularly relates to a kind of I/O (I/O) interface of integrated device electronics.
Background technology
Usually wish on I/O (I/O) interface of integrated circuit (IC) equipment, to improve data transfer bandwidth.But, be that the increase aspect transmission bandwidth is attended by the increase of the data pin number of this IC equipment lamentedly.Many data pin have occupied very big device area unfriendly, and have also increased the power consumption noise relevant with power supply.
Fig. 1 is the block scheme of a conventional memory circuit.Address signal ADDR1-ADDRi is stored by an address buffer 10 temporarily, and clock signal clk and external command signal/CS ,/RAS ,/CAS and/WE is applied in a command decoder 20.Select in the timing of this clock signal clk, this external command signal of this command decoder decodes is internal command signal PR, PC, PREAD and PWRITE.Respond described internal command PR, row decoder 30 is according to one or more row that are stored in the address selection memory cell array 50 in this address buffer 10.Similarly, respond described internal command PC, column decoder 40 is according to the one or more row that are stored in this memory cell array 50 of this address selection in this address buffer 10.To be write within this memory cell array 50 or read from this memory cell array 50 be respectively by this internal command PWRITE and PREAD control to data actually.The data that read from this memory cell array are transmitted by an I/O interface circuit 55, and put on data pin DQ1 to DQn, and the data of writing within this memory cell array 50 are received to DQn from this data pin DQ1 via this I/O interface circuit 55.
Fig. 2 is the detailed block scheme of interface circuit 55 illustrated in fig. 1.Under the situation of read operation, first DATA1 of this n bit parallel output data is temporarily stored among the output buffer 55-1, puts on this data pin DQ1 then.Similarly, second and the 3rd DATA2 and the DATA 3 of this n bit parallel output data are temporarily stored among output buffer 55-3 and the 55-5, put on this data pin DQ2 and DQ3 then respectively.All the other positions of this parallel output data similarly are temporarily stored in the corresponding n-3 impact damper (not shown), put on the data pin DQ4 to DQn of Fig. 1 then.
Under the situation of write operation, first of these n bit parallel input data on data pin DQ1 is temporarily stored among the input buffer 55-2, puts on this memory cell array as DATA1 then.Similarly, second and the 3rd of these n bit parallel input data on data pin DQ2 and DQ3 is temporarily stored among input buffer 55-4 and the 55-6, puts on this memory cell array as DATA2 and DATA3 then.All the other positions of this parallel input data on the data pin DQ4 to DQn of Fig. 1 also are temporarily stored in the corresponding n-3 input buffer (not shown), put on this memory cell array then.
The voltage level that depends on it, these data DATA1, DATA2 or the like are considered to logic high (H) or low (L).Fig. 3 is the synoptic diagram of two level signal schemes of an I/O interface circuit that is used for interpretation routine.If the input data voltage level greater than a reference voltage REF, these input data are considered to logic high (VIH) so, and if the voltage level of output data greater than this reference voltage REF, this output data also is considered to logic high (VOH) so.On the other hand, if the voltage level of input data is less than this reference voltage REF, these input data are considered to logic low (VIH) so, and if the voltage level of output data less than this reference voltage REF, this output data also is considered to logic low (VOL) so.
In the equipment of aforesaid routine, the number of data pin DQ1 to DQn equals to read and write into from this memory cell array the number of the position of the parallel I/O data within this memory cell array.Therefore, will cause must be in addition being equipped with this equipment in any increase aspect the number of the position of the data transfer rate of this I/O interface with the data pin of equal number.Propose as previous, occupy bigger device area unfriendly, and also increased power consumption and the noise relevant with power supply in interpolation any aspect the number of data pin.
Summary of the invention
According to a first aspect of the invention, provide an integrated circuit, it comprises: M the first terminal and N second terminal, and wherein M and N are positive integers, and M＞N＞1 wherein; First converter, it receives M A base level input signal from described M the first terminal respectively, it is encoded to M+1 A base level coding signal with described M A base level input signal, and generate N K base level output signal in response to this M+1 A base level coding signal, and it exports this N K base level output signal respectively and arrive individual second terminal of N, wherein A and K are positive integers, and, K＞A＞1 wherein, wherein, described N second terminal is pin terminal.
According to another aspect of this invention, an integrated circuit is provided, it comprises: N the first terminal and M second terminal, M and N are positive integers here, and M＞N＞1 here; A converter, it receives N K base level input signal from this N the first terminal respectively, and each K base value that its decoding is represented by this N K base level input signal is the A of M A base level output signal MDifferent one of value, and it exports this M A base level output signal respectively to individual second terminal of described M, A and K are positive integers here, and K＞A＞1 here.
According to a further aspect of the invention, provide an integrated circuit, it comprises: M the first terminal and N second terminal, and M and N are positive integers here, and M＞N＞1 here; One first converter, it receives M A base level output signal from this M the first terminal respectively, each A of its this M A base level output signal of encoding MThe different K base value of value for representing, and it exports N K base level output signal respectively and arrive individual second terminal of N by N K base level output signal, A and K are positive integers here, and K＞A＞1 here; With one second converter, it receives N K base level input signal from this N the first terminal respectively, and each K base value that its decoding is represented by this N K base level input signal is the A of M A base level input signal MDifferent one of value, and it exports this M A base level input signal respectively to individual second terminal of this M.
According to a further aspect of the invention, provide an integrated circuit, it comprises: the memory devices that comprises memory cell array, address decoder and command decoder; A plurality of pin terminals; And be connected interface circuit between this memory devices and a plurality of pin terminal, described interface circuit comprises: (a) first converter, its three corresponding signal lines from this memory devices receive three binary-level input signals, its described three binary-level input signals of encoding become four binary-level coded signals, and generate two three-shift level output signals in response to these four binary-level coded signals, and it exports two pin terminals of these two three-shift level output signals in described a plurality of pin terminals respectively, (b) second converter, it receives two three-shift level input signals from described two pin terminals respectively, its in response in described two three-shift level input signals each and generate two binary-level coded signals, thereby generate four binary-level coded signals, and these four binary-level coded signals of decoding become three binary-level output signals, and it exports described three corresponding signal lines of these three binary-level output signals to this memory devices respectively.
The method of the lead-out terminal of a kind of internal circuit that is used to connect integrated device electronics and this integrated device electronics is provided according to a further aspect of the invention.This method comprises: M terminal from described internal circuit receives M A base level input signal respectively; Described M the A base level input signal of encoding becomes M+1 A base level coding signal; With export the basic level output signal of N K in response to described M+1 A base level coding signal; Export N the lead-out terminal of described N K base level output signal respectively to described integrated device electronics, wherein M, N, A and K are positive integers, wherein M＞N＞1, wherein K＞A＞1, and a wherein said N lead-out terminal is the pin terminal of this integrated device electronics.
The method of the input terminal of a kind of internal circuit that is used to connect integrated device electronics and this integrated device electronics is provided according to a further aspect of the invention.This method comprises: N input terminal from this integrated device electronics receives N K base level input signal respectively, and each K base value that decoding is represented by this N K base level input signal is the A of M A base level input signal MDifferent one and export M the terminal that this M A base level input signal arrives this internal circuit respectively of value.Here, M, N, A and K are positive integers, M＞N＞1, and K＞A＞1.
The method of the input/output terminal of a kind of internal circuit that is used to connect integrated device electronics and this integrated device electronics is provided according to a further aspect of the invention.This method comprises: first and second signal conversion processes.This first signal conversion processes comprises: M terminal from this internal circuit receives M A base level output signal respectively, and each A that is represented by this M A base level input signal encodes MValue is for the different K base value represented by N K base level output signal and export N the input/output terminal of the basic level output signal of this N K to this integrated device electronics respectively.This secondary signal conversion process comprises: N input/output terminal from this integrated device electronics receives N K base level input signal respectively, and each K base value that decoding is represented by this N K base level input signal is the A of M A base level input signal MDifferent one and export M the terminal that this M A base level input signal arrives this internal circuit respectively of value.Here, M, N, A and K are positive integers, M＞N＞1, and K＞A＞1.
The method of the I/O pin terminal of a kind of internal circuit that is used to connect integrated circuit memory equipment and this integrated circuit memory equipment is provided according to another aspect of the present invention.This method comprises: first and second signal conversion processes.This first signal conversion processes comprises: receive three binary-level output signals from three corresponding signal lines of this internal circuit, the binary value that coding is represented by three binary-level output signals is for the value of the three-state represented by two ternary level output signals and export level output signal to the two I/O pin terminal of these two three-states respectively.This secondary signal conversion process comprises: the level input signal that receives two three-states respectively from two I/O pin terminals, the ternary value that decoding is represented by the level input signal of two three-states is for the binary value represented by three binary-level input signals and export three signal wires of these three binary-level input signals to this internal circuit respectively.
Description of drawings
From the detailed description below with reference to the accompanying drawing of following, it is more obvious that the features and advantages of the present invention will become, wherein:
Fig. 1 is the block scheme of the memory devices of routine;
Fig. 2 is the block scheme of I/O interface circuit of memory devices of the routine of Fig. 1;
Fig. 3 is the block scheme of signaling plan of two level of I/O interface of the routine of key diagram 2;
Fig. 4 is the block scheme of an I/O interface according to an embodiment of the invention;
Fig. 5 is the block scheme of memory devices of the I/O interface of the Fig. 4 of comprising according to an embodiment of the invention;
Fig. 6 is the block scheme of bit pad of the I/O interface of a Fig. 4 according to an embodiment of the invention;
Fig. 7 is a figure who illustrates three level signal schemes according to an embodiment of the invention;
Fig. 8 is the synoptic diagram of a scrambler according to an embodiment of the invention and output buffer;
Fig. 9 is the synoptic diagram of an input buffer according to an embodiment of the invention and demoder;
Figure 10 is the block scheme of an I/O interface according to an embodiment of the invention;
Figure 11 is the table of the logic input and output state of a scrambler that Fig. 8 is shown and output buffer; With
Figure 12 is the table of the logic input and output state of this input buffer that Fig. 9 is shown and demoder.
Embodiment
Preferred embodiment referring now to several non-limiting is described the present invention.
Fig. 4 is the block scheme of I/O according to an embodiment of the invention (I/O) interface.The I/O interface 200 of present embodiment comprises a converter 210, its respectively from M the first terminal receive M A base level input signal (DATA1, DATA2, DATA3), and each A that represents by the basic level input signal of M A that encodes MThe different K base value of value for representing by N K base level output signal.Then, this converter 210 export respectively this N K base level output signal to this N second terminal (DQ1, DQ2).Here, M＞N, and K＞A＞1, and M, N, K and A are positive integer all.
In the example of Fig. 4, M=3 and A=2, therefore, these data DATA1, DATA2 and DATA3 are 2 basic level (scale-of-two) signals, that is to say, are received on three input terminals of this converter 210 respectively.In addition, in this example, N=2 and K=3, therefore, the output of this converter 210 is two 3 basic level (three-shift) signals that put on lead-out terminal DQ1 and DQ2.In other words, the converter 210 of Fig. 4 be one have that the input of three scale-of-two and two three-shifts export 2 3The position is to 3 2Bit pad.
The I/O interface of Fig. 4 also comprises a converter 220, (DQ1 DQ2) receives N K base level input signal, and each K base value of being represented by N K base level input signal of decoding is M A base level output signal (DATA1 from N the first terminal respectively for it, DATA2, A DATA3) MDifferent one of value.Then, this converter 220 is exported this M A base level output signal respectively to M second terminal.As previously mentioned, M＞N, and K＞A＞1, and M, N, K and A are positive integer all.
In the example of Fig. 4, N=2 and K=3, therefore, the input of this converter 220 is two 3 basic level signals from terminal DQ1 and DQ2 reception.In addition, in this example, M=3 and A=2, therefore, these data DATA1, DATA2 and DATA3 are by the 2 basic level signals of exporting from three terminals of this converter 220 respectively, and in other words, this converter 220 of Fig. 4 is one and has 3 of two three-shift inputs and three scale-of-two outputs 2The position is to 2 3The converter of position.
This 2 basic level signal (A=2) was before combined description with Fig. 3.This 3 basic level signal (K=3) is illustrated with respect to input data (output data is differentiated in the same way) in Fig. 7.If the voltage level that should import data is greater than a reference voltage REF1, these input data are considered to logic high (VIH).If the voltage level that should import data is less than this reference voltage REF1, and greater than this voltage level REF2, these input data are considered to (VIM) in the logic.If the voltage level that should import data is less than this reference voltage REF2, these input data are considered to logic low (VIL).As obviously as seen, each of the multi-level signal of Fig. 7 carries more information than each of the 2 basic level signals of Fig. 3.
The more detailed example of the I/O equipment of Fig. 6 key diagram 4.As shown, this I/O interface normally is made up of an encoder/decoder circuitry 70 and an input/output circuitry 60.
More particularly, the converter 210 of this I/O interface comprises a scrambler 71 and an output buffer 61,63, this scrambler 71 receives M A base level input signal and exports the signal of M+1 A base level coding at least, and this output buffer 61,63 receives this signal and N K base of output level output signal of the level coding of M+1 A base at least.
As previously mentioned, the example of Fig. 6 shows N=2, K=3, the situation of M=3 and A=2.Therefore, this scrambler 71 receives three (M) 2 basic level (scale-of-two) internal data D1, D2 and D3, and the data of this reception of encoding are four (M+1) 2 basic level (scale-of-two) data DO1, DO2 and DO3, DO4.Described data DO1 and DO2 are applied in an output buffer 61, and it changes above-mentioned data is 3 basic level (three-shift) signals that put on terminal DQ1.Described data DO3 and DO4 are applied in an output buffer 63, and it changes above-mentioned data is 3 basic level (three-shift) signals that put on terminal DQ2.Notice that here these three 2 basic level data D1, D2 and D3 in general can have 2 3(=8) individual admissible state, and two 3 basic level datas on terminal DQ1 and DQ2 can have 3 2(=9) individual admissible state.Therefore, this binary data D1, D2 and D3 can be encoded as the ternary data on terminal DQ1 and the DQ2.
Still with reference to figure 6, the converter 220 of this I/O interface circuit comprises 62,64 and demoders 72 of an input buffer.Described input buffer 62,64 receives N K base level input signal and exports the signal of M+1 A base level coding at least, and described demoder 72 receives the signal of M+1 A base level coding at least and exports this M A base level output signal.
Equally, the example of Fig. 6 shows N=2, K=3, the situation of M=3 and A=2.As shown, input buffer 62 and 64 receives two (N) 3 basic level (three-shift) input signals from terminal DQ1 and DQ2 respectively.The three-shift input signal of described input buffer 62 this terminal of conversion DQ1 is binary signal DI1 and DI2, and the three-shift input signal of described input buffer 64 this terminal of conversion DQ2 is binary signal DI3 and DI4.Like this, these two (N) ternary signals (DQ1, DQ2) be converted into four (M+1) binary signals (DI1, DI2, DI3, DI4).Subsequently, these four binary signals are decoded as three (M) 2 basic level signal D1, D2 and D3 by described demoder 72.
With reference now to Fig. 5,, it is the block scheme of the memory devices of an I/O interface circuit that adopts one embodiment of the invention.Described address buffer 10, command decoder 20, row decoder 30, column decoder 40 and memory cell array 50 all turn round in the mode identical with the equipment of routine in Fig. 1.Therefore, for fear of repetition, reference number just makes an explanation to these previous parts in this instructions.
In the memory devices of Fig. 5, I/O interface of the present invention is inserted between this memory cell array and the data pin terminal DQ1 to DQk.As above described in conjunction with Fig. 6, the I/O interface 200 of an embodiment comprises an encoder/decoder circuitry 70 and an input/output (i/o) buffer circuit 60.In this example, during read operation, sent to this I/O interface circuit 200 from this memory cell array 50 with the data (DATA) of the form of a n bit parallel binary output signal.Per three of this n position output signal are encoded as two ternary signals, and it is applied in this data pin DQ1 two in the DQk.Therefore, the number of data pin k equals from 2/3rds of the number of the carry-out bit n of this memory cell array 50.Therefore, as can be seen, compare 1/3rd data pin does not need with routine configuration.These unwanted data pin are designated as pin PIN1 to PINj in Fig. 5, and can be used for other application.
Fig. 8 illustrates this scrambler 71 shown in Figure 6 and output buffer 61 and 63 detailed examples, and Figure 11 is a logic coding table that is used for the operation of key drawing 8.This scrambler 71 receives scale-of-two input data D1, D2 and D3, and to be equipped with logical circuit be binary coded data DO1, DO2, DO3 and DO4 with these scale-of-two input data of encoding.In this specific example, described scrambler 71 comprises NOR gate NR1 and the NR2 that fully all connects as shown in Figure 8, NOT-AND gate ND1 and ND2, AND gate AND1 to AND3, OR-gate OR1 and OR2 and not gate 11 and 12.
Mutual relationship between scale-of-two input data D1, D2, D3 and binary coded data DO1, DO2, DO3, DO4 is shown in Figure 11.For example, be under the situation of " 011 " in the input data, this coded data becomes " 0100 ".
Described encoded data D O1 and DO2 are applied in an output buffer 61, are the ternary signal that a confession puts on terminal DQ1 to change this coded data.In this example, this output buffer 61 is equipped with a p transistor npn npn P1 and a N transistor npn npn N1.Binary coded signal DO1 is applied in the grid of transistor P1, and binary coded signal DO2 is applied in the grid of transistor N1.For simplicity, suppose that transistor P1 and N1 are the desirable transistors of identical current capability, as DO1 and DO2 both when being high, the output of this impact damper 61 will be VSS (low) so; When DO1 is low and DO2 when being high, the output of this impact damper 61 will be VDD/2 (in); When being low as DO1 and DO2 both, the output of this impact damper 61 will be VDD (height).This is by shown in row DO1, the DO2 and DQ1 of the table of Figure 11, and 0 expression here is low, and 1 expression is high, and during M represents.
This impact damper 63 works in the same way, is the ternary signal that a confession puts on this terminal DQ2 with conversion binary signal DO3 and DO4.
Therefore, shown in the table of Figure 11, this scrambler 71 and output buffer 61,63 play this scale-of-two output data of coding D1, D2, D3 are the three-shift output data that puts on terminal DQ1 and DQ2.For example, be under the situation of " 011 " in the scale-of-two output data, this three-shift coding output data is " M1 ".
Fig. 9 illustrates this input buffer 62 shown in Figure 6 and 64 detailed examples, and Figure 12 is a logical decode table that is used for the operation of key drawing 9.As shown, input buffer 62 is equipped with first and second comparer 62-1 and the 62-2, this ternary signal and first and second reference voltage REF1 and the REF2 that it relatively receives on terminal DQ1, and this comparative result is as binary-coded data DI1 and DI2 output.In this example, as shown in figure 12, if this ternary signal is " 0 ", DI1 and DI2 both are " 0 " so; If this ternary signal is " M ", DI1 is that " 0 " and DI2 are " 1 " so; And if this ternary signal is " 1 ", DI1 and DI2 both are " 1 " so.
This second input buffer 64 is equipped with comparer 64-1 and 64-2 similarly, and exports binary-coded data DI3 and DI4 based on the ternary signal of this terminal DQ2.
Described demoder 72 receives binary-coded data DI1, DI2, DI3 and DI4, and to be equipped with logical circuit be binary decoded data D1, D2 and D3 with the described binary-coded data of decoding.In this specific example, this demoder 72 comprises the AND gate AND4 to AND7 that connects fully as shown in Figure 9, OR-gate OR3 and OR4 and not gate 13 to 16.
In data D1, the D2 of described binary-coded data DI1, DI2, DI3, DI4 and binary decoded, mutual relationship between the D3 by shown in Figure 12.For example, be under the situation of " 0100 " in coded data, the data of this decoding become " 100 ".
Therefore, shown in the table of Figure 12, it is scale-of-two input data D1, D2, D3 that this input buffer 62,64 and demoder 72 play this three-shift input data that decoding puts on terminal DQ1 and DQ2.For example, the input data of encoding in this three-shift are under the situation of " M1 ", and these scale-of-two input data are " 011 ".
Figure 10 is another block scheme according to the I/O interface of the embodiment of the invention.This synoptic diagram is different from the synoptic diagram of Fig. 6, that is, it is conceptive to illustrate a kind of scheme with a plurality of lead-out terminal DQ1 to DQk, and it not necessarily proposes the binary to ternary conversion.In output function, the M position of scale-of-two output data is received by the I/O interface with encoder/decoder circuitry 700 and buffer circuits 600.Described scrambler 710 and output buffer 610-1 to 610-k this scale-of-two output data of encoding is P base level output signal (P here K〉=2 M), and apply these signals respectively to this terminal DQ1 to DQk.In input operation, the P of terminal DQ1 to DQk base level input signal is decoded as the scale-of-two input data of M position by input buffer 620-1 to 620-k and demoder 720.Notice, under the situation of K terminal DQ1 to DQk, will provide K group input/output (i/o) buffer.
In these drawing and description, the typical preferred embodiment of the present invention is disclosed, though proposed specific example, they only are used to meaning general and explanation, rather than the purpose that is used to limit.For example, the present invention is not limited to the main herein binary to ternary conversion of describing.
In addition, with reference to figure 5, the I/O interface of the embodiment of the invention can be inserted between the order pin terminal of command decoder 20 and memory devices 300, and/or is inserted between this address buffer 10 and the address pin terminal.
Therefore, should be appreciated that scope of the present invention is to be explained by appended claim, rather than explain by the embodiment that demonstrates.

Claims (35)

1. integrated circuit comprises:
M the first terminal and N second terminal, wherein M and N are positive integers, and M＞N＞1 wherein;
First converter, it receives M A base level input signal from described M the first terminal respectively, it is encoded to M+1 A base level coding signal with described M A base level input signal, and generate N K base level output signal in response to this M+1 A base level coding signal, and it exports this N K base level output signal respectively to N second terminal, and wherein A and K are positive integers, and, K＞A＞1 wherein
Wherein, described N second terminal is pin terminal.
2. integrated circuit as claimed in claim 1 also comprises: memory cell array, wherein, a described M the first terminal is connected to this memory cell array, and wherein said N second terminal is the data pin terminals.
3. integrated circuit as claimed in claim 1, also comprise: memory cell array and an address decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to this address decoder, and wherein said N second terminal is the address pin terminal.
4. integrated circuit as claimed in claim 1, also comprise: memory cell array and the command decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to this command decoder, and wherein said N second terminal is the order pin terminal.
5. integrated circuit as claimed in claim 1 also comprises:
Memory cell array, with command decoder that is connected to this memory cell array and address buffer, wherein, a described M the first terminal is connected in described memory cell array, command decoder and the address buffer, and individual second terminal of wherein said N is one in data pin terminal, order pin terminal and the address pin terminal.
6. integrated circuit as claimed in claim 1, wherein A=2.
7. integrated circuit as claimed in claim 6, M=3 wherein, N=2, and K=3.
8. integrated circuit as claimed in claim 1, wherein said first converter comprises:
Scrambler, it is converted to described M+1 A base level coding signal with described M A base level input signal; With
Output buffer, it receives described M+1 A base level coding signal, and exports described N K base level output signal.
9. integrated circuit as claimed in claim 8, wherein, A=2, M=3, N=2, and K=3;
Described scrambler comprises:
First logical circuit, when first and second signals in described M the A base level input signal were " 0 ", this first logical circuit generated described M+1 first signal in the A base level coding signal and is " 1 ";
Second logical circuit, first, second signal in described M A base level input signal is " 00 ", " 01 " or " 10 ", and when first, second in described M A base level input signal and the 3rd signal be not " 101 ", it was " 1 " that this second logical circuit generates described M+1 the secondary signal in the A base level coding signal;
The 3rd logical circuit, first and second signals in described M A base level input signal are " 10 ", when first, second in perhaps described M the A base level input signal and the 3rd signal were " 000 ", the 3rd logical circuit generated described M+1 the 3rd signal in the A base level coding signal and is " 1 "; And
The 4th logical circuit, when the second and the 3rd signal in described M the A base level input signal was not " 11 ", the 4th logical circuit generated described M+1 the 4th signal in the A base level coding signal and is " 1 "; And
Described output buffer comprises:
First impact damper, it comprises: a PMOS transistor, it is connected between power supply and the first node, and the conducting in response to first signal in described M+1 the A base level coding signal; With first nmos pass transistor, it is connected between first node and the ground voltage, and the conducting in response to the secondary signal in described M+1 the A base level coding signal; And
Second impact damper, it comprises: the 2nd PMOS transistor, it is connected between power supply and the Section Point, and the conducting in response to the 3rd signal in described M+1 the A base level coding signal; With second nmos pass transistor, it is connected between Section Point and the ground voltage, and the conducting in response to the 4th signal in described M+1 the A base level coding signal.
10. integrated circuit as claimed in claim 1 also comprises:
Second converter, it receives N K base level input signal from described N second terminal respectively, in response in this N K base level input signal each and generate 2 A base level coding signals, thereby generate M+1 the 2nd A base level coding signal, and this second converter is a M A base level output signal with described M+1 the 2nd A base level coding signal decoding, and exports this M A base level output signal respectively to a described M the first terminal.
11. integrated circuit as claimed in claim 10 also comprises: memory cell array, wherein, a described M the first terminal is connected to described memory cell array, and wherein said N second terminal is the data pin terminals.
12. integrated circuit as claimed in claim 10, also comprise: memory cell array and the address decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to described address decoder, and wherein said N second terminal is the address pin terminal.
13. integrated circuit as claimed in claim 10, also comprise: memory cell array and the command decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to this command decoder, and wherein said N second terminal is the order pin terminal.
14. integrated circuit as claimed in claim 10, wherein A=2.
15. integrated circuit as claimed in claim 14, M=3 wherein, N=2, and K=3.
16. integrated circuit as claimed in claim 10, wherein said second converter comprises:
Input buffer, it receives described N K base level input signal, and exports described M+1 the 2nd A base level coding signal; With
Demoder, it is decoded to described M+1 the 2nd A base level coding signal, and exports described M A base level output signal.
17. as the integrated circuit of claim 16, A=2 wherein, M=3, N=2, and K=3.
18. integrated circuit as claimed in claim 17, wherein
Described input buffer comprises:
First input buffer, it comprises: first comparer compares first signal and first reference voltage in described N the K base level input signal, to generate described M+1 first signal in the 2nd A base level coding signal; With second comparer, first signal and second reference voltage in described N the K base level input signal are compared, to generate described M+1 the secondary signal in the 2nd A base level coding signal;
Second input buffer, it comprises: the 3rd comparer compares the secondary signal and first reference voltage in described N the K base level input signal, to generate described M+1 the 3rd signal in the 2nd A base level coding signal; With the 4th comparer, the secondary signal and second reference voltage in described N the K base level input signal are compared, to generate described M+1 the 4th signal in the 2nd A base level coding signal;
Described demoder comprises:
First logical circuit, first signal in described M+1 the 2nd A base level coding signal is " 1 ", when the first, second, third and the 4th signal in individual the 2nd A base of the perhaps described M+1 level coding signal was " 0100 ", this first logical circuit generated described M first signal in the A base level output signal and is " 1 ";
Second logical circuit, when the second and the 4th signal in described M+1 the 2nd A base level coding signal was " 1 ", this second logical circuit generated described M the secondary signal in the A base level output signal and is " 1 ";
The 3rd logical circuit, the 3rd signal in described M+1 the 2nd A base level coding signal is " 1 ", the second and the 4th signal in individual the 2nd A base of the perhaps described M+1 level coding signal is " 01 ", when the first and the 4th signal in individual the 2nd A base of the perhaps described M+1 level coding signal was " 10 ", the 3rd logical circuit generated described M the 3rd signal in the A base level output signal and is " 1 ".
19. integrated circuit as claimed in claim 18 also comprises: memory cell array, wherein, a described M the first terminal is connected to this memory cell array, and wherein said N second terminal is the data pin terminals.
20. integrated circuit as claimed in claim 18, also comprise: memory cell array and the address decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to this address decoder, and wherein said N second terminal is the address pin terminal.
21. integrated circuit as claimed in claim 18, also comprise: memory cell array and the command decoder that is connected to this memory cell array, wherein, a described M the first terminal is connected to this command decoder, and wherein said N second terminal is the order pin terminal.
22. integrated circuit as claimed in claim 10, wherein,
Described first converter comprises: scrambler, and it is converted to M+1 A base level coding signal with described M A base level input signal; And output buffer, it receives described M+1 A base level coding signal, and exports described N K base level output signal; With
Described second converter comprises: input buffer, and it receives N K base level input signal, and exports described M+1 the 2nd A base level coding signal; And demoder, it is decoded to described M+1 the 2nd A base level coding signal, and it exports described M A base level output signal.
23. integrated circuit as claimed in claim 22, A=2 wherein, M=3, N=2, and K=3.
24. an integrated circuit comprises:
The memory devices that comprises memory cell array, address decoder and command decoder;
A plurality of pin terminals; With
Be connected the interface circuit between this memory devices and a plurality of pin terminal, described interface circuit comprises:
(a) first converter, its three corresponding signal lines from this memory devices receive three binary-level input signals, its described three binary-level input signals of encoding become four binary-level coded signals, and generate two three-shift level output signals in response to these four binary-level coded signals, and its export respectively these two three-shift level output signals in described a plurality of pin terminals two pin terminals and
(b) second converter, it receives two three-shift level input signals from described two pin terminals respectively, its in response in described two three-shift level input signals each and generate two binary-level coded signals, thereby generate four binary-level coded signals, and these four binary-level coded signals of decoding become three binary-level output signals, and it exports described three corresponding signal lines of these three binary-level output signals to this memory devices respectively.
25. integrated circuit as claimed in claim 24, wherein, described interface circuit is connected between described memory cell array and the pin terminal, and wherein said pin terminal is the data pin terminals.
26. integrated circuit as claimed in claim 24, wherein, described interface circuit is connected between described address decoder and the pin terminal, and wherein said pin terminal is the address pin terminal.
27. integrated circuit as claimed in claim 24, wherein, described interface circuit is connected between described command decoder and this pin terminal, and wherein said pin terminal is the order pin terminal.
28. integrated circuit as claimed in claim 24,
Wherein, described first converter comprises: (a) scrambler, it receives described three binary-level input signals, and it exports four binary-level coded signals, (b) output buffer, it receives four binary-level coded signals by described scrambler output, and exports described two three-shift level output signals; And
Wherein, described second converter comprises: (a) input buffer, it receives two three-shift level input signals, and export four binary-level coded signals, (b) demoder, it receives four binary-level coded signals by described input buffer output, and exports described three binary-level output signals.
29. the method for the lead-out terminal of an internal circuit that connects integrated device electronics and this integrated device electronics, this method comprises:
M terminal from described internal circuit receives M A base level input signal respectively;
Described M the A base level input signal of encoding becomes M+1 A base level coding signal; With
Export N K base level output signal in response to described M+1 A base level coding signal;
Export N the lead-out terminal of described N K base level output signal respectively to described integrated device electronics,
Wherein M, N, A and K are positive integers, M＞N＞1 wherein, and K＞A＞1 wherein, and a wherein said N lead-out terminal is the pin terminal of this integrated device electronics.
30. method as claimed in claim 29, wherein, the internal circuit of described integrated device electronics is a memory cell array, and a wherein said N lead-out terminal is the data pin terminals.
31. method as claimed in claim 29,
Wherein, described integrated circuit comprises memory cell array and is connected to the command decoder and the address buffer of this memory cell array, wherein, described internal circuit is in this memory cell array, this command decoder and this address buffer, and a wherein said N lead-out terminal is one in data pin terminal, order pin terminal and the address pin terminal.
32. method as claimed in claim 29 also comprises:
N input terminal from described integrated device electronics receives N K base level input signal respectively;
In response in described N K base level input signal each and generate 2 A base level coding signals, thereby generate M+1 the 2nd A base level coding signal;
With described M+1 the 2nd A base level coding signal decoding is M A base level output signal; With
Export M the terminal of described M A base level output signal respectively to described internal circuit,
Wherein M, N, A and K are positive integers, M＞N＞1 wherein, and K＞A＞1 wherein, and a wherein said N input terminal is the pin terminal of this integrated device electronics.
33. method as claimed in claim 29,
Wherein, A=2, M=3, N=2, and K=3;
Described M the A base level input signal of encoding becomes M+1 A base level coding signal and comprises:
When described M A base level input signal is " 000 ", generate described M+1 A base level coding signal and be " 1111 ", when described M A base level input signal is " 001 ", generate described M+1 A base level coding signal and be " 1101 ", when described M A base level input signal is " 010 ", generate described M+1 A base level coding signal and be " 0101 ", when described M A base level input signal is " 011 ", generate described M+1 A base level coding signal and be " 0100 ", when described M A base level input signal is " 100 ", generate described M+1 A base level coding signal and be " 0111 ", when described M the defeated input signal of A base level is " 101 ", generate described M+1 A base level coding signal and be " 0011 ", be " 0001 " when described M A base level input signal generates described M+1 A base level coding signal during for " 110 ", and be " 0000 " when described M A base level input signal generates described M+1 the basic level coding signal of an A during for " 111 ";
Exporting described N K base level output signal in response to described M+1 A base level coding signal comprises:
When described M+1 A base level coding signal is " 1111 ", generate described N K base level output signal and be " 00 ", when described M+1 A base level coding signal is " 1101 ", generate described N K base level output signal and be " 0M ", wherein M represents level signal between signal " 1 " and the signal " 0 ", when described M+1 A base level coding signal is " 0101 ", generate described N K base level output signal and be " MM ", when described M+1 A base level coding signal is " 0100 ", generate described N K base level output signal and be " M1 ", when described M+1 A base level coding signal is " 0111 ", generate described N K base level output signal and be " M0 ", when described M+1 A base level coding signal is " 0011 ", generate described N K base level output signal and be " 10 ", be " 1M " when described M+1 A base level coding signal generates described N K base level output signal during for " 0001 ", and be " 11 " when described M+1 A base level coding signal generates the basic level output signal of described N K during for " 0000 ".
34. method as claimed in claim 32,
Wherein, described integrated device electronics comprises memory cell array and is connected to the command decoder and the address buffer of this memory cell array, wherein, described internal circuit is in described memory cell array, this command decoder and this address buffer, and a wherein said N input terminal is one in data pin terminal, order pin terminal and the address pin terminal.
35. method as claimed in claim 32,
Wherein, A=2, M=3, N=2, and K=3;
In response in described N K base level input signal each and generate 2 the 2nd A base level coding signals, comprise thereby generate described M+1 the 2nd A base level coding signal:
When described N K base level input signal is " 00 ", generate described M+1 the 2nd A base level coding signal and be " 0000 ", when described N K base level input signal is " 0M ", generate described M+1 the 2nd A base level coding signal and be " 0001 ", wherein M represents level signal between " 0 " and " 1 ", when described N K base level input signal is " M1 ", generate described M+1 the 2nd A base level coding signal and be " 0101 ", when described N K base level input signal is " M1 ", generate described M+1 the 2nd A base level coding signal and be " 0111 ", when described N K base level input signal is " M0 ", generate described M+1 the 2nd A base level coding signal and be " 0100 ", when described N K base level input signal is " 10 ", generate described M+1 the 2nd A base level coding signal and be " 1100 ", be " 1101 " when described N K base level input signal generates described M+1 the 2nd A base level coding signal during for " 1M ", and be " 1111 " when described N K base level input signal generates described M+1 the basic level coding signal of the 2nd A during for " 11 "; And
With described M+1 the 2nd A base level coding signal decoding is that M A base level output signal comprises:
When described M+1 the 2nd A base level coding signal is " 0000 ", generate described M A base level output signal and be " 000 ", when described M+1 the 2nd A base level coding signal is " 0001 ", generate described M A base level output signal and be " 001 ", when described M+1 the 2nd A base level coding signal is " 0101 ", generate described M A base level output signal and be " 010 ", when described M+1 the 2nd A base level coding signal is " 0111 ", generate described M A base level output signal and be " 011 ", when described M+1 the 2nd A base level coding signal is " 0100 ", generate described M A base level output signal and be " 100 ", when described M+1 the 2nd A base level coding signal is " 1100 ", generate described M A base level output signal and be " 101 ", be " 110 " when described M+1 the 2nd A base level coding signal generates described M A base level output signal during for " 1101 ", and be " 111 " when described M+1 the 2nd A base level coding signal generates the basic level output signal of described M A during for " 1111 ".
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