CN100539101C - The high-frequency integrated circuit encapsulation structure of unification projection jointing altitude and manufacture method - Google Patents
The high-frequency integrated circuit encapsulation structure of unification projection jointing altitude and manufacture method Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to a kind of high-frequency integrated circuit encapsulation structure and manufacture method of unification projection jointing altitude, this high-frequency integrated circuit encapsulation structure mainly comprises a substrate, sticking crystal layer, a projection wafer and a plurality of external terminal of a multistage.This multistage, sticking crystal layer was formed on this substrate, with the active face of bonding this wafer.A plurality of projections are arranged at this active face.When above-mentioned projection is bonded to the projection connection pad of this substrate, this active face that simultaneously should sticking bonding this wafer of crystal layer of multistage.Therefore, jointing altitude that can the above-mentioned projection of unification, projection can be and primaryly be configured on the chip bonding pads or for non-arranged does not need reconfiguration line layer, and short electrical bang path can be provided, to meet high-frequency integrated circuit encapsulation cheaply.
Description
Technical field
The present invention relates to a kind of high-frequency integrated circuit encapsulation technology, particularly relate to a kind of high-frequency integrated circuit encapsulation structure and manufacture method thereof of unification projection jointing altitude.
Background technology
The integrated circuit encapsulation technology is to wish to protect more high frequency, arithmetic speed integrated circuit (IC) wafer faster with the processing procedure more simplified and lower packaging cost.It is to adopt routing to be connected individually or the flip-chip bonded technology that right present method for packing electrically connects between wafer and substrate, routing is connected with electrical transmission range, can't be for the use of high-frequency integrated circuit, flip-chip bonded then need form a reconfiguration line layer (Redistribution layer on the surface of flip chip, RDL), so that the required projection of flip chip is an arranged, but the cost height especially is not suitable for the memory body encapsulation of low pin position.
See also Fig. 1, a kind of existing known IC circuit packing structure 100 mainly comprises a substrate 110, a wafer 120, one sticking crystal layer 130, a plurality of bonding wire 140, an adhesive body 150 and a plurality of external terminal 160.The first surface 111 of this substrate 110 is as sticking brilliant surface, and the second surface 112 of this substrate 110 is as planting sphere.Usually this substrate 110 is hard printed circuit board and has a slotted eye 113, passes through for routing.Should glue the active face 121 that crystal layer 130 is formed on this wafer 120, with the active face 121 of bonding this wafer 120.This active face 121 of this wafer 120 is to be formed with a plurality of weld pads 122.The bonding wire 140 that utilizes routing to form electrically connects the above-mentioned weld pad 122 and this substrate 110 of this wafer 120.And with this adhesive body 150 sealings this wafer 120 and above-mentioned bonding wire 140.Above-mentioned external terminal 160 as soldered ball is these second surfaces 112 that are engaged in this substrate 110, but outer surface engages (SMT) to an external printed circuit board.Yet the length of above-mentioned bonding wire 140 is unfavorable for the signal transmission of high frequency IC.In addition, in the high-frequency integrated circuit encapsulating products, wish more thinning and more lightweight.
This shows that above-mentioned existing integrated circuits packaging structure obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel IC circuit packing structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing integrated circuits packaging structure exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of novel IC circuit packing structure, can improve general existing integrated circuits packaging structure, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the existing integrated circuits packaging structure exists, and provide a kind of novel IC circuit packing structure, technical problem to be solved is to make it carry out flip-chip bonded with the low cost wafer of non-arranged projection, reach and reduce process complexity and increase volume production speed, and have electrical conducting path short, prevent the effect of breasting the tape and encapsulating thinning, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.The high-frequency integrated circuit encapsulation structure of a kind of unification projection jointing altitude that proposes according to the present invention, it comprises: a substrate, it is to have a first surface and a second surface, wherein is formed with a plurality of projection connection pads on this first surface; One multistage was glued crystal layer, and it is formed on this first surface of this substrate; One wafer, it has an active face and a plurality of projection on this active face, and this wafer is that upside-down mounting is arranged on this first surface of this substrate, and above-mentioned projection is bonded to above-mentioned projection connection pad, and should glue this active face of bonding this wafer of crystal layer the multistage; And a plurality of external terminals, it is arranged at this second surface of this substrate, and wherein said each projection connection pad has a depressed area.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said these projections are Solder Bumps, and above-mentioned projection connection pad is formed with a nickel-gold layer.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said these projections are golden projections, and above-mentioned projection connection pad is formed with a solder layer.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said these external terminals comprise soldered ball.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said substrate are circuit films.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said substrate is a printed circuit board (PCB).
The object of the invention to solve the technical problems also realizes by the following technical solutions.The high-frequency integrated circuit method for packing of a kind of unification projection jointing altitude that proposes according to the present invention, it comprises following steps: a substrate is provided, and it has a first surface and a second surface, wherein is to be formed with a plurality of projection connection pads on this first surface; Form sticking crystal layer of a multistage on this first surface of this substrate; Upside-down mounting is provided with a wafer on this first surface of this substrate, and this wafer has an active face and a plurality of projection on this active face, and above-mentioned projection is bonded to above-mentioned projection connection pad, and should glue this active face of bonding this wafer of crystal layer the multistage; And a plurality of external terminals this second surface at this substrate is set.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said each projection connection pad has a depressed area.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said these projections are Solder Bumps, and above-mentioned projection connection pad is formed with a nickel-gold layer.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said these projections are golden projections, and above-mentioned projection connection pad is to be formed with a solder layer.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said these external terminals comprise soldered ball.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said substrate are circuit films.
The high-frequency integrated circuit method for packing of aforesaid unification projection jointing altitude, wherein said substrate are printed circuit board (PCB)s.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The high-frequency integrated circuit encapsulation structure of a kind of unification projection jointing altitude that proposes according to the present invention, it comprises: a substrate, have a first surface and a second surface, wherein be formed with a plurality of projection connection pads on this first surface; One multistage was glued crystal layer, was formed on this first surface of this substrate; One wafer has an active face and a plurality of projection on this active face, and this flip-chip is arranged on this first surface of this substrate, and described projection is bonded to described projection connection pad, and should glue this active face of bonding this wafer of crystal layer the multistage; And a plurality of external terminals, it is arranged at this second surface of this substrate; Wherein on described projection connection pad, be formed with a solder layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said external terminal comprises soldered ball.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said substrate are circuit films.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said substrate are printed circuit board (PCB)s.
The high-frequency integrated circuit encapsulation structure of aforesaid unification projection jointing altitude, wherein said projection are golden projections.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude of the present invention and manufacture method thereof have following advantage at least: can carry out flip-chip bonded with the low cost wafer of non-arranged projection, reach and reduce process complexity and increase volume production speed, and have electrical conducting path short, prevent the effect of breasting the tape and encapsulating thinning.
In sum, the invention relates to a kind of high-frequency integrated circuit encapsulation structure and manufacture method thereof of unification projection jointing altitude, this high-frequency integrated circuit encapsulation structure mainly comprises a substrate, sticking crystal layer, a projection wafer and a plurality of external terminal of a multistage.This multistage, sticking crystal layer was to be formed on this substrate, with the active face of bonding this wafer.A plurality of projections are to be arranged at this active face.When above-mentioned projection is bonded to the projection connection pad of this substrate, should sticking crystal layer of multistage be this active face of bonding this wafer simultaneously.Therefore, jointing altitude that can the above-mentioned projection of unification, projection can be and primaryly be configured on the chip bonding pads or for non-arranged does not need reconfiguration line layer, and short electrical bang path can be provided, to meet high-frequency integrated circuit encapsulation cheaply.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and the outstanding effect that has enhancement than the existing integrated circuits packaging structure, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of schematic cross-section that has known IC circuit packing structure now.
Fig. 2 is according to first specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure of unification projection jointing altitude.
Fig. 3 A to 3C figure is according to first specific embodiment of the present invention, the substrate schematic cross-section of this high-frequency integrated circuit encapsulation structure in processing procedure.
Fig. 4 is according to second specific embodiment of the present invention, the schematic cross-section of the high-frequency integrated circuit encapsulation structure of another kind of unification projection jointing altitude.
Fig. 5 is according to second specific embodiment of the present invention, and schematic cross-section is amplified in the part of a wherein projection of this high-frequency integrated circuit encapsulation structure.
100: IC circuit packing structure 110: substrate
111: first surface 112: second surface
113: slotted eye 120: wafer
121: active face 122: weld pad
130: sticking crystal layer 140: bonding wire
150: adhesive body 160: external terminal
200: high-frequency integrated circuit encapsulation structure 210: substrate
211: first surface 212: second surface
213: projection connection pad 214: solder layer
215: ball pad 216: the hole electrically conducts
217: line layer 220: the multistage is glued crystal layer
230: wafer 231: active face
232: weld pad 233: projection
240: external terminal 300: high-frequency integrated circuit encapsulation structure
310: substrate 311: first surface
312: second surface 313: the projection connection pad
314: depressed area 315: nickel-gold layer
316: ball pad 317: the hole electrically conducts
318: line layer 320: the multistage is glued crystal layer
330: wafer 331: active face
332: weld pad 333: projection
340: external terminal 350: adhesive body
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, high-frequency integrated circuit encapsulation structure and its embodiment of manufacture method, structure, feature and the effect thereof of the unification projection jointing altitude that foundation the present invention is proposed, describe in detail as after.
See also Fig. 2, in first specific embodiment of the present invention, a kind of high-frequency integrated circuit encapsulation structure 200 of unification projection jointing altitude mainly comprises a substrate 210, sticking crystal layer 220, a wafer 230 and a plurality of external terminal 240 of a multistage.
This substrate 210 has a first surface 211 and a second surface 212, wherein is formed with a plurality of projection connection pads 213 on this first surface 211.This substrate 210 can be printed circuit board (PCB) or circuit film.Preferably, this substrate 210 is the circuit films of COF mantle for example, helps encapsulating thinning, lightweight and reduction thermal resistance.In addition, in the present embodiment, this substrate 210 can be near wafer size.This second surface 212 of this substrate 210 is formed with a plurality of ball pads 215.This substrate 210 includes a line layer 217 and a plurality of holes 216 that electrically conduct that connect at first surface 211 in addition, with above-mentioned projection connection pad 213 and the above-mentioned ball pad 215 that electrically connects this substrate 210.In addition, this first surface 211 of this substrate 210 can be formed with a welding resisting layer (figure does not draw), covers this line layer 217 of this substrate 210 with the part.
This multistage, sticking crystal layer 220 was formed on this first surface 211 of this substrate 210.This multistage, sticking crystal layer 220 included the multi-stage curing resin, for example should can be printed on this substrate 210 in the A stage (A-stage) by sticking crystal layer 220 of multistage, toast this substrate 210 and should the multistage glue 220 to the B stage of crystal layer (B-stage) with local slaking, it has sticking brilliant characteristic and is attached at this substrate 210 with the glued membrane kenel, before the final products shipment, sticking crystal layer 220 of this multistage fully slaking to C stage (C-stage).In addition, in different embodiment changed, the multistage in B stage, sticking crystal layer 220 can further be subdivided into the local slaking state of more multistage variation, as B1, B2, B3 or the like.
This wafer 230 has an active face 231, and has several projections 233 on this active face 231.These wafer 230 upside-down mountings are arranged on this first surface 211 of this substrate 210, so that above-mentioned projection 233 metal bondings are to above-mentioned projection connection pad 213, and should sticking crystal layer 220 of multistage be these active faces 231 of bonding this wafer 230.Utilize sticking crystal layer 220 of this multistage to keep the flip-chip bonded gap and paste wafer, this wafer 230 can not need to make reconfiguration line layer (RDL), above-mentioned projection 233 can be set directly at the top of original a plurality of weld pads 232 of this wafer 230, is positioned at the central or peripheral of this active face 231.In the present embodiment, above-mentioned projection 233 is golden projections, and above-mentioned projection connection pad 213 is formed with a solder layer 214, in order to the molten above-mentioned projection 233 of weldering, reaches the electric connection of flip-chip bonded.Therefore, this wafer 230 is very short with the electrical connection path of this substrate 210, and making the jointing altitude unification of above-mentioned projection 233, the gold thread that can not need routing to form more omits the reconfiguration line layer (RDL) of existing known flip chip, is applicable to high frequency encapsulation cheaply.Preferably, this wafer 230 is DDR3 memory chips, and its frequency surpasses more than the 500MHz.In addition, the back side of this wafer 230 is preferably and appears shape or the fin that is sticked in addition (figure does not draw), to increase radiating effect.
Above-mentioned external terminal 240 is arranged at this second surface 212 of this substrate 210, for to outer engagement.In the present embodiment, above-mentioned external terminal 240 comprises soldered ball (solder ball), and it is arranged on the above-mentioned ball pad 215.In different embodiment, can utilize tin cream, Metal Ball, metal bolt or ACF conducting resinl displacement soldered ball to form above-mentioned external terminal 240.
By sticking crystal layer 220 of the multistage around above-mentioned projection 233, when above-mentioned projection 233 metal bondings to above-mentioned projection connection pad 213, this wafer 230 is difficult for tilting, and to keep the jointing altitude unification of above-mentioned projection 233, does not need to insert underfill (underfillmater ial) again.In addition, the electric connection between this wafer 230 and this substrate 210 is that the routing that omits in the past electrically connects step, has the convenience that processing procedure is simplified.
Cooperate Fig. 3 A to Fig. 3 C, disclose the manufacturing process of this high-frequency integrated circuit encapsulation structure 200.At first, as shown in Figure 3A, at first providing a substrate 210, is to be formed with a plurality of projection connection pads 213 on its first surface 211, is formed with a plurality of ball pads 215 on its second surface 212.Utilize this line layer 217 and the above-mentioned hole 216 that electrically conducts, electrically connect above-mentioned projection connection pad 213 and above-mentioned ball pad 215.On above-mentioned projection connection pad 213, can be formed with a solder layer 214 in addition.Then, shown in Fig. 3 B, can use the steel plate printing to form sticking crystal layer 220 of a multistage on this first surface 211 of this substrate 210, and before sticking crystalline substance, be roasted into the B rank in advance, reach suitable support effect.
Afterwards, shown in Fig. 3 C, upside-down mounting is provided with a wafer 230 on this first surface 211 of this substrate 210, and the projection 233 of this wafer 230 is to be bonded to above-mentioned projection connection pad 213 via this solder layer 214, and should sticking crystal layer 220 of multistage be active faces 231 of bonding this wafer 230.At last, above-mentioned external terminal 240 is arranged at above-mentioned ball pad 215, and slaking should also can be made the high-frequency integrated circuit encapsulation structure 200 that obtains as shown in Figure 2 by sticking crystal layer 220 of multistage.
See also Fig. 4, in second specific embodiment of the present invention, disclose the high-frequency integrated circuit encapsulation structure 300 of another kind of unification projection jointing altitude, mainly comprise a substrate 310, sticking crystal layer 320, a wafer 330 and a plurality of external terminal 340 of a multistage.
This substrate 310 is to have a first surface 311 and a second surface 312, wherein is formed with a plurality of projection connection pads 313 on this first surface 311, and this second surface 312 of this substrate 310 is formed with a plurality of ball pads 316.This substrate 310 includes a plurality of hole 317 and at least one line layers 318 of electrically conducting in addition, to electrically connect above-mentioned projection connection pad 313 and above-mentioned ball pad 316.In the present embodiment, this substrate 310 is to can be a printed circuit board (PCB) or circuit film, helps encapsulating thinning and lightweight.
This multistage, sticking crystal layer 320 was formed on this first surface 311 of this substrate 310.This wafer 330 has an active face 331 and a plurality of projection 333 on this active face 331.
These wafer 330 upside-down mountings are arranged on this first surface 311 of this substrate 310, so that above-mentioned projection 333 is bonded to above-mentioned projection connection pad 313, and should sticking crystal layer 320 of multistage be these active faces 331 of bonding this wafer 330.Preferably, above-mentioned projection 333 is arranged on weld pad 332 tops of this wafer 330, to omit the reconfiguration line layer of existing known flip chip.
Above-mentioned external terminal 340 is these second surfaces 312 that are arranged at this substrate, and above-mentioned external terminal 340 is to comprise soldered ball (solder ball).
Preferably, as shown in Figure 5, each projection connection pad 313 is to have a depressed area 314, with the bonding area of increase to above-mentioned projection 333, and prevents that collapsing of above-mentioned projection 333 is diffusing.In the present embodiment, above-mentioned projection 333 is Solder Bumps, and above-mentioned projection connection pad 313 is formed with a nickel-gold layer 315, reaches metal bonding in the reflow mode.
Because in the present embodiment, this wafer 330 replaces hot pressing with reflow and reaches the flip-chip bonded operation, the quantity delivered of sticking crystal layer 320 fails to seal above-mentioned projection 333 when this multistage, this high-frequency integrated circuit encapsulation structure 300 can include an adhesive body 350 in addition, it is this first surface 311 and salable this wafer 330 that is formed at this substrate 310, more can insert the gap of these wafer 330 belows, to prevent the unreal generation puffed rice of filler (popcorn) phenomenon.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of high-frequency integrated circuit encapsulation structure of unification projection jointing altitude is characterized in that comprising:
One substrate, it has a first surface and a second surface, wherein is to be formed with a plurality of projection connection pads on this first surface;
One multistage was glued crystal layer, and it is formed on this first surface of this substrate;
One wafer, it has an active face and a plurality of projection on this active face, and this flip-chip is arranged on this first surface of this substrate, and above-mentioned projection is bonded to above-mentioned projection connection pad, and should sticking crystal layer of multistage be this active face of bonding this wafer; And
A plurality of external terminals, it is arranged at this second surface of this substrate,
Wherein each projection connection pad has a depressed area.
2, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 1 it is characterized in that wherein said these projections are Solder Bumps, and above-mentioned projection connection pad is formed with a nickel-gold layer.
3, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 1 it is characterized in that wherein said these projections are golden projections, and above-mentioned projection connection pad is formed with a solder layer.
4, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 1 is characterized in that wherein said these external terminals comprise soldered ball.
5, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 1 is characterized in that wherein said substrate is a circuit film.
6, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 1 is characterized in that wherein said substrate is a printed circuit board (PCB).
7, a kind of high-frequency integrated circuit method for packing of unification projection jointing altitude is characterized in that comprising following steps:
One substrate is provided, and it has a first surface and a second surface, wherein is formed with a plurality of projection connection pads on this first surface;
Form sticking crystal layer of a multistage on this first surface of this substrate;
Upside-down mounting is provided with a wafer on this first surface of this substrate, and this wafer has an active face and a plurality of projection on this active face, and above-mentioned projection is bonded to above-mentioned projection connection pad, and should glue this active face of bonding this wafer of crystal layer the multistage; And
A plurality of external terminals this second surface at this substrate is set.
8, the high-frequency integrated circuit method for packing of unification projection jointing altitude according to claim 7 is characterized in that wherein said each projection connection pad has a depressed area.
9, the high-frequency integrated circuit method for packing of unification projection jointing altitude according to claim 7 it is characterized in that wherein said these projections are Solder Bumps, and above-mentioned projection connection pad is formed with a nickel-gold layer.
10, the high-frequency integrated circuit method for packing of unification projection jointing altitude according to claim 7 it is characterized in that wherein said these projections are golden projections, and above-mentioned projection connection pad is formed with a solder layer.
11, the high-frequency integrated circuit method for packing of unification projection jointing altitude according to claim 7 is characterized in that wherein said these external terminals comprise soldered ball.
The high-frequency integrated circuit method for packing of 12 unification projection jointing altitudes according to claim 7 is characterized in that wherein said substrate is a circuit film.
13, the high-frequency integrated circuit method for packing of unification projection jointing altitude according to claim 7 is characterized in that wherein said substrate is a printed circuit board (PCB).
14, a kind of high-frequency integrated circuit encapsulation structure of unification projection jointing altitude is characterized in that it comprises:
One substrate has a first surface and a second surface, wherein is formed with a plurality of projection connection pads on this first surface;
One multistage was glued crystal layer, was formed on this first surface of this substrate;
One wafer has an active face and a plurality of projection on this active face, and this flip-chip is arranged on this first surface of this substrate, and described projection is bonded to described projection connection pad, and should glue this active face of bonding this wafer of crystal layer the multistage; And
A plurality of external terminals, it is arranged at this second surface of this substrate;
Wherein on described projection connection pad, be formed with a solder layer.
15, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 14 is characterized in that wherein said external terminal comprises soldered ball.
16, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 14 is characterized in that wherein said substrate is a circuit film.
17, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 14 is characterized in that wherein said substrate is a printed circuit board (PCB).
18, the high-frequency integrated circuit encapsulation structure of unification projection jointing altitude according to claim 14 is characterized in that wherein said projection is golden projection.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100036319A CN100539101C (en) | 2007-01-18 | 2007-01-18 | The high-frequency integrated circuit encapsulation structure of unification projection jointing altitude and manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100036319A CN100539101C (en) | 2007-01-18 | 2007-01-18 | The high-frequency integrated circuit encapsulation structure of unification projection jointing altitude and manufacture method |
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| CN101226910A CN101226910A (en) | 2008-07-23 |
| CN100539101C true CN100539101C (en) | 2009-09-09 |
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| Country | Link |
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| CN (1) | CN100539101C (en) |
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