CN100524656C - Production of thin-film transistor - Google Patents
Production of thin-film transistor Download PDFInfo
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- CN100524656C CN100524656C CNB2005101081083A CN200510108108A CN100524656C CN 100524656 C CN100524656 C CN 100524656C CN B2005101081083 A CNB2005101081083 A CN B2005101081083A CN 200510108108 A CN200510108108 A CN 200510108108A CN 100524656 C CN100524656 C CN 100524656C
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Abstract
A production method for membrane transistor by offering the first base plank and its frontispiece formed with some cupped design and offering the second base plank. Form amorphous membrane on the second base plank and touches its amorphous membrane with frontispiece of the first base plank. Carry the anneal technology and change amorphous membrane into polycrystalline silicon membrane. Then separate the first and second base plank and design the polycrystalline silicon membrane of the second base plank to an island of polycrystalline silicon. Form insulated layer of bar to overcast the island of polycrystalline silicon and form grid on the insulated layer of bar. It forms fountain pole / drain pole in the island of polycrystalline silicon on the both sides of grid and there are the channels between fountain pole and drain pole. This method reduces the production steps and technology time.
Description
Technical field
The present invention relates to a kind of method of manufacturing thin film transistor, and is particularly related to and a kind ofly grows up (heterogeneous growth) with method that forms polysilicon membrane and the method that adopting said method is made thin-film transistor with heterogeneous nucleation.
Background technology
The communication interface of display behaviour and information is development trend at present with the flat-panel screens.Flat-panel screens mainly contains following several: display of organic electroluminescence (organic electro-luminescencedisplay, OELD), plasma display (plasma display panel, PDP), LCD (liquid crystal display, LCD) and light emitting diode indicator (light emitting diode, LED) etc.
In aforementioned display device, (thin film transistor is TFT) as the driving element of display can to utilize thin-film transistor.Generally speaking, according to the channel layer Material Selection, thin-film transistor can be divided into two kinds of amorphous silicon film transistor (amorphous silicon TFT) and low-temperature polysilicon film transistors (low-temperature polysilicon thin film transistor, LTPS TFT).Wherein, low-temperature polysilicon film transistor is a kind of technology that is better than general traditional amorphous silicon film transistor, because its electron mobility can reach 200cm
2More than/the V-sec, thus can make the thin-film transistor element area occupied littler of meeting the demand of high aperture (aperture), and then promote display brightness and reduce whole power consumption problem.In addition, because the increase of electron mobility, so the part drive circuit can be manufactured on the glass baseplate simultaneously, (chip on glass, COG), thus, the panel manufacturing cost can significantly reduce and the crystal glass structure is covered in formation.
It should be noted that in low-temperature polysilicon film transistor its channel layer is normally with quasi-molecule laser annealing technology (excimer laser annealing, ELA) polysilicon membrane that forms.Therefore, for to obtain having better quality, the polysilicon membrane of less defective (defect) and big crystal grain (grain), must obtain this polysilicon membrane through the grow up mode of (heterogeneous growth) of heterogeneous nucleation usually.
Figure 1A～Fig. 1 E is the manufacturing step flow process profile that a kind of known mode of utilizing heterogeneous nucleation to grow up is carried out polysilicon membrane.Please refer to Figure 1A, substrate 100 at first is provided, and make recess patterns 110 on substrate 100, wherein, the mode of making recess patterns 110 can be known photoengraving carving technology.Then, please refer to Figure 1B, deposition one deck amorphous silicon membrane 120 in recess patterns 110.Continue it, please refer to 1C, carry out quasi-molecule laser annealing technology 130, to change the amorphous silicon membrane in the recess patterns 110 120 (shown in Figure 1B) into polysilicon membrane 140.Come again, please refer to Fig. 1 D, another layer of deposition amorphous silicon membrane 150 on substrate 100.Afterwards, please refer to Fig. 1 E, carry out the quasi-molecule laser annealing technology 160 of another time, make amorphous silicon membrane 150 (shown in Fig. 1 D) be transformed into polysilicon membrane 170.
More specifically, formed polysilicon membrane 140 in recess patterns 110, it is to use as crystal seed layer (seed layer).When the quasi-molecule laser annealing technology 160 of carrying out shown in Fig. 1 E, because the difference of fusing point, amorphous silicon membrane 150 can utilize the polysilicon membrane 140 in the recess patterns 110 to carry out heterogeneous nucleation as crystal seed to grow up.
Yet, the method of above-mentioned formation polysilicon membrane 170, must on substrate 100, carry out the photoengraving carving technology to produce recess patterns 110 earlier, and in recess patterns 110, make polysilicon membrane 140 as crystal seed layer, so, therefore the method for above-mentioned formation polysilicon membrane 170 need, will increase manufacturing step and process time through twice quasi-molecule laser annealing technology.
Summary of the invention
The purpose of this invention is to provide a kind of method of manufacturing thin film transistor, it is suitable for reducing the manufacturing step and the process time of thin-film transistor.
The present invention proposes a kind of method of manufacturing thin film transistor, it provides first substrate earlier, has been formed with a plurality of recess patterns on the front of this first substrate, and the material of this first substrate is to be selected from a kind of in silicon material, metal material and the combination thereof, wherein, this silicon material comprises the polysilicon material.Then, provide second substrate, and form amorphous silicon membrane on second substrate, the coefficient of heat conduction of this first substrate is greater than the coefficient of heat conduction of this amorphous silicon membrane.Come again, the amorphous silicon membrane on second substrate is contacted with the front of first substrate.Continue it, carry out annealing process, make amorphous silicon membrane be transformed into polysilicon membrane.Then, first substrate is separated on second substrate.Polysilicon membrane on patterning second substrate is to form polysilicon island thing.Come again, form gate insulation layer to cover polysilicon island thing.Continue it, on gate insulation layer, form grid.Afterwards, in the polysilicon island thing of grid both sides, form source/drain, and promptly be channel region between the source/drain.
In one of the present invention preferred embodiment, above-mentioned metal material comprises nickel or aluminium.
In one of the present invention preferred embodiment, the material of above-mentioned second substrate comprises glass or quartz.
In one of the present invention preferred embodiment, above-mentioned annealing process can be a quasi-molecule laser annealing technology.
In one of the present invention preferred embodiment, on be set forth in first substrate the front method that forms recess patterns comprise the following steps.At first, on first substrate, form photoresist layer.Then, photoresist layer is carried out photoetching process, to form the patterning photoresist with photo etched mask.Afterwards, be mask etching first substrate with the patterning photoresist, and form recess patterns.
In one of the present invention preferred embodiment, above-mentioned method of manufacturing thin film transistor also comprises the following steps.At first, form protective layer cover polysilicon island thing with grid.Then, this protective layer of patterning is to expose source/drain.Afterwards, form the source/drain metal layer on protective layer, wherein the source/drain metal layer can be electrically connected with the source/drain that exposes.
First substrate that the present invention has recess patterns because of employing is as crystal seed layer, and utilizes the characteristic of the coefficient of heat conduction of first substrate greater than the coefficient of heat conduction of amorphous silicon membrane, makes the amorphous silicon membrane that is formed on second substrate change polysilicon membrane into.Therefore, with the manufacture method of known polysilicon membrane Comparatively speaking, the manufacture method of polysilicon membrane of the present invention can only be utilized quasi-molecule laser annealing technology one time, can finish the manufacturing of polysilicon membrane.In addition, can also reuse, and then reduce manufacturing cost and the process time that on the photoengraving carving technology, is spent as first substrate of crystal seed layer.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A～Fig. 1 E is the steps flow chart profile that a kind of known mode of utilizing heterogeneous nucleation to grow up is carried out the manufacturing of polysilicon membrane.
Fig. 2 A～Fig. 2 F is the step of manufacturing flow process profile of a kind of polysilicon membrane in the present invention's the preferred embodiment.
Fig. 3 A～Fig. 3 C is the steps flow chart generalized section that forms recess patterns in the front of first substrate.
Fig. 4 A～Fig. 4 I is the steps flow chart generalized section of a kind of method of manufacturing thin film transistor in the present invention's the preferred embodiment.
Fig. 5 A～Fig. 5 C is a kind of steps flow chart generalized section that forms protective layer and source/drain metal layer on thin-film transistor in the present invention's the preferred embodiment.
The main element description of symbols
100: substrate
110: recess patterns
120: amorphous silicon membrane
130,160: quasi-molecule laser annealing technology
140,170: polysilicon membrane
150: amorphous silicon membrane
200,500: the first substrates
202,502: the front
210,510: recess patterns
220,520: the second substrates
230,530: amorphous silicon membrane
240,540: annealing process
250,550: polysilicon membrane
260,506: contact position
300: photoresist layer
310: photo etched mask
312: transparent area
314: non-transparent area
320: the patterning photoresist
560: polysilicon island thing
570: gate insulation layer
580: grid
590: source/drain
595: channel region
598: ion implantation technology
600: protective layer
610: the source/drain metal layer
Embodiment
Fig. 2 A～Fig. 2 F is the step of manufacturing flow process profile of a kind of polysilicon membrane in the present invention's the preferred embodiment.
The manufacture method of polycrystal silicon film for example comprises the following steps more than the present invention.At first, please refer to Fig. 2 A, first substrate 200 is provided, and the front 202 of first substrate 200 has been formed with a plurality of recess patterns 210.
In one of the present invention embodiment, the method that forms recess patterns 210 in the front 202 of first substrate 200 comprises the step shown in Fig. 3 A～Fig. 3 C.At first, please refer to Fig. 3 A, on first substrate 200, form photoresist layer 300.Then, please refer to Fig. 3 B, carry out photoetching process, to form patterning photoresist 320 with 310 pairs of photoresist layers of photo etched mask 300.This photo etched mask 310 has a plurality of transmission regions 312 and non-transmission region 314, when photoresist layer 300 is the eurymeric photoresist, photoresist layer 300 through illumination and development can be removed, therefore form the patterning photoresist 320 shown in Fig. 3 B, certainly, photoresist layer 300 also can be a negative photoresist.Afterwards, please continue the C with reference to Fig. 3, be mask etching first substrate 200 with patterning photoresist 320, and form recess patterns 210.Then, remove patterning photoresist layer 320, promptly can obtain first substrate 200 shown in Fig. 2 A with recess patterns 210.
In addition, in a preferred embodiment, the material of first substrate 200 is to be selected from a kind of in silicon material, metal material and the combination thereof, and wherein, the silicon material can be polysilicon or wafer silicon material, and metal material can be nickel or aluminium.
Then, please continue B, second substrate 220 is provided with reference to Fig. 2.It should be noted that second substrate 220 that is provided must be a transparency carrier,, and carry out the backside laser annealing process so that laser can be by (being shown among Fig. 2 E).In a preferred embodiment, the material of second substrate 220 for example comprises glass or quartz.
Come again, please refer to Fig. 2 C, on second substrate 220, form amorphous silicon membrane 230.In one of the present invention embodiment, the method that on second substrate 220, forms amorphous silicon membrane 230 can be chemical vapour deposition technique (chemical vapor deposition, CVD) or plasma-enhanced chemical vapor deposition PECVD (PECVD) method.
Continue it, please the amorphous silicon membrane 230 on second substrate 220 be contacted with the front 202 of first substrate 200 simultaneously with reference to Fig. 2 D and Fig. 2 E.And shown in Fig. 2 E, carry out annealing process 240, make amorphous silicon membrane 230 be transformed into polysilicon membrane 250.In one of the present invention preferred embodiment, this annealing process 240 can be a quasi-molecule laser annealing technology, and the coefficient of heat conduction of first substrate 200 is greater than the coefficient of heat conduction of amorphous silicon membrane 230.
More specifically, first substrate 200 with recess patterns 210 is to use as crystal seed layer substrate (seed layer substrate) at this, because the coefficient of heat conduction of first substrate 200 is greater than the coefficient of heat conduction of amorphous silicon membrane 230, so when carrying out annealing process 240, the contact position 260 of the amorphous silicon membrane 230 of first substrate 200 and second substrate 220 will have temperature gradient, and make be positioned at contact position 260 amorphous silicon membrane 230 with first substrate 200 as crystal seed, and carry out the crystallization process that heterogeneous nucleation is grown up.The process of this crystallization is by recess patterns 210 growths of contact position 260 toward both sides, finishes the manufacturing of whole polysilicon membrane 250 to the end.
Afterwards, please refer to Fig. 2 F, first substrate 200 and second substrate 220 are separated.It should be noted that, between first substrate 200 and the polysilicon membrane 250 on second substrate 220 as crystal seed layer, if in long brilliant process, have the situation of cohering mutually to take place, then may when separating first substrate 200 and second substrate 220, cause peeling off of polysilicon membrane 250.Therefore, by the Material Selection of above-mentioned first substrate 200, can make that formed polysilicon membrane 250 separates easily on first substrate 200 and second substrate 220.More specifically, the material of first substrate 200 is good with metal material.In addition, first substrate 200 as crystal seed layer can be reused, therefore, compare with processes well known, the manufacture method of this polysilicon membrane can not need to carry out the technology as Figure 1A～1C, thus, the manufacture method of this polysilicon membrane can be omitted photoengraving carving technology (shown in Figure 1A) and reduce a laser annealing technique (shown in Fig. 1 C), and then reduces manufacturing step of the present invention and process time.
In sum, the manufacture method utilization of polycrystal silicon film is as first substrate of crystal seed layer more than the present invention, and then omission photoengraving carving technology, and only need carry out one time quasi-molecule laser annealing technology, can finish the manufacturing of polysilicon membrane, above-mentioned first substrate as crystal seed layer can also be reused, and therefore, the present invention's manufacturing step and process time can significantly reduce.
The manufacture method of above-mentioned polysilicon membrane can be applicable in the manufacturing of low-temperature polysilicon film transistor.Fig. 4 A～Fig. 4 I is the steps flow chart generalized section of a kind of method of manufacturing thin film transistor in the present invention's the preferred embodiment.
Please refer to Fig. 4 A, it provides first substrate 500 earlier, has been formed with a plurality of recess patterns 510 on the front 502 of this first substrate 500.In one of the present invention embodiment, the material of first substrate 500 is to be selected from a kind of in silicon material, metal material and the combination thereof, wherein, the silicon material can be polysilicon or wafer silicon material, and metal material can be nickel or aluminium, the method and the photoengraving carving technology described in above-mentioned Fig. 3 A～Fig. 3 C that wherein form recess patterns 510 are similar, will no longer be repeated at this.
Then, please refer to Fig. 4 B, second substrate 520 is provided, and on second substrate 520, form amorphous silicon membrane 530.In one of the present invention embodiment, the material of second substrate 520 can be glass or quartz, and the method for formation amorphous silicon membrane 530 for example is chemical vapour deposition technique or plasma-enhanced chemical vapor deposition PECVD method.
Come again, please the amorphous silicon membrane 530 on second substrate 520 be contacted with the front 502 of first substrate 500, and proceed annealing process 540, make amorphous silicon membrane 530 be transformed into polysilicon membrane 550 simultaneously with reference to Fig. 4 C and Fig. 4 D.In one embodiment, this annealing process 540 can be a quasi-molecule laser annealing technology, and because the coefficient of heat conduction of first substrate 500 is greater than the coefficient of heat conduction of amorphous silicon membrane 530, so the contact position 506 of the amorphous silicon membrane 530 of first substrate 500 and second substrate 520 will have temperature gradient, and make be positioned at contact position 506 amorphous silicon membrane 530 with first substrate 500 as crystal seed, carry out the crystallization process that heterogeneous nucleation is grown up.Then, please refer to Fig. 4 E, first substrate 500 is separated on second substrate 520.
Come, please refer to Fig. 4 F, the polysilicon membrane 550 on patterning second substrate 520 is to form polysilicon island thing 560, wherein, the method of patterning is general photoengraving carving technology, and the person of ordinary skill in the field should implement according to this, will not given unnecessary details at this.
Then, please refer to Fig. 4 G, form gate insulation layer 570 to cover polysilicon island thing 560.In one of the present invention embodiment, the method that forms this gate insulation layer 570 can be chemical vapour deposition technique or plasma-enhanced chemical vapor deposition PECVD method, and the material of gate insulation layer 570 can be silica or silicon nitride.
Continue it, please refer to Fig. 4 H, on gate insulation layer 570, form grid 580.The mode that forms grid 580 for example is after depositing one deck gate metal layer (not shown) all sidedly earlier, carry out general photoengraving carving technology again, or utilize shady shade (not shown) to cooperate the mode of coating process, directly deposition forms grid 580 on gate insulation layer 570, the person of ordinary skill in the field should implement according to this, at this in detail step of technology will be described in detail.
Afterwards, please refer to Fig. 4 I, in the polysilicon island thing 560 of grid 580 both sides, form source/drain 590, and promptly be channel region 595 between the source/drain 590.The method that forms source/drain 590 for example is to be alignment mask voluntarily with grid 580, carries out ion implantation technology 598, dopant ion is injected in the polysilicon island thing 560.
In one of the present invention preferred embodiment, above-mentioned method of manufacturing thin film transistor for example also comprises the step shown in Fig. 5 A～Fig. 5 C.At first, please refer to Fig. 5 A, form protective layer 600 cover polysilicon island things 560 with grid 580.The method that forms this protective layer 600 for example is chemical vapour deposition technique or plasma-enhanced chemical vapor deposition PECVD method, and the material of protective layer 600 for example is a silicon nitride.Then, please refer to Fig. 5 B, this protective layer 600 of patterning is to expose source/drain 590.This Patternized technique is general photoengraving carving technology, is not described in detail at this.Afterwards, please refer to Fig. 5 C, form source/drain metal layer 610 on protective layer 600, wherein source/drain metal layer 610 can be electrically connected with the source/drain 590 that exposes.
In sum, polycrystal silicon film and method of manufacturing thin film transistor have following advantage more than the present invention:
First substrate as crystal seed layer can also be reused, and then reduces manufacturing cost and the process time that is spent on the photoengraving carving technology.In addition, compare with the manufacture method of known polysilicon membrane, the manufacture method of polycrystal silicon film can only be utilized quasi-molecule laser annealing technology one time more than the present invention, promptly can finish the manufacturing of polysilicon membrane.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (6)
1. method of manufacturing thin film transistor is characterized in that comprising:
First substrate is provided, has been formed with a plurality of recess patterns on the front of this first substrate, the material of this first substrate is to be selected from a kind of in silicon material, metal material and the combination thereof, and wherein, this silicon material comprises the polysilicon material;
Second substrate is provided, and forms amorphous silicon membrane on this second substrate, the coefficient of heat conduction of this first substrate is greater than the coefficient of heat conduction of this amorphous silicon membrane;
This amorphous silicon membrane on this second substrate is contacted with this front of this first substrate;
Carry out annealing process, make this amorphous silicon membrane be transformed into polysilicon membrane;
This first substrate is separated on this second substrate;
This polysilicon membrane on this second substrate of patterning is to form polysilicon island thing;
Form gate insulation layer to cover this polysilicon island thing;
On this gate insulation layer, form grid; And
In this polysilicon island thing of these grid both sides, form source/drain, and promptly be channel region between this source/drain.
2. method of manufacturing thin film transistor according to claim 1 is characterized in that this metal material comprises nickel or aluminium.
3. method of manufacturing thin film transistor according to claim 1 is characterized in that the material of this second substrate comprises glass or quartz.
4. method of manufacturing thin film transistor according to claim 1 is characterized in that this annealing process comprises quasi-molecule laser annealing technology.
5. method of manufacturing thin film transistor according to claim 1 is characterized in that the method that forms above-mentioned these recess patterns in this front of this first substrate comprises:
On this first substrate, form photoresist layer;
With photo etched mask this photoresist layer is carried out photoetching process, to form the patterning photoresist; And
With this patterning photoresist is this first substrate of mask etching, and forms above-mentioned these recess patterns.
6. method of manufacturing thin film transistor according to claim 1 is characterized in that also comprising:
Form protective layer, cover this polysilicon island thing and this grid;
This protective layer of patterning is to expose this source/drain; And
Form the source/drain metal layer on this protective layer, wherein this source/drain metal layer can be electrically connected with this source/drain that exposes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101081083A CN100524656C (en) | 2005-09-29 | 2005-09-29 | Production of thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101081083A CN100524656C (en) | 2005-09-29 | 2005-09-29 | Production of thin-film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941298A CN1941298A (en) | 2007-04-04 |
| CN100524656C true CN100524656C (en) | 2009-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101081083A Expired - Fee Related CN100524656C (en) | 2005-09-29 | 2005-09-29 | Production of thin-film transistor |
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| Country | Link |
|---|---|
| CN (1) | CN100524656C (en) |
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2005
- 2005-09-29 CN CNB2005101081083A patent/CN100524656C/en not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| Thermal Conductivity of Amorphous Silicon. H.J.Goldsmid, M.M.Kaila, G.L.Paul.physica status solidi (a),Vol.76 No.1. 1983 |
| Thermal Conductivity of Amorphous Silicon. H.J.Goldsmid, M.M.Kaila, G.L.Paul.physica status solidi (a),Vol.76 No.1. 1983 * |
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| Publication number | Publication date |
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| CN1941298A (en) | 2007-04-04 |
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