CN100518450C - Method for producing substrates - Google Patents

Method for producing substrates Download PDF

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Publication number
CN100518450C
CN100518450C CNB2005800007813A CN200580000781A CN100518450C CN 100518450 C CN100518450 C CN 100518450C CN B2005800007813 A CNB2005800007813 A CN B2005800007813A CN 200580000781 A CN200580000781 A CN 200580000781A CN 100518450 C CN100518450 C CN 100518450C
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CN
China
Prior art keywords
layer
ground floor
conversion
deviation
ftrans
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Expired - Fee Related
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CNB2005800007813A
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Chinese (zh)
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CN1860835A (en
Inventor
托马斯·奎克
乌韦·梅特卡
罗兰德·施蒂策
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Via Mechanics Ltd
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Hitachi Via Mechanics Ltd
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Publication date
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Publication of CN1860835A publication Critical patent/CN1860835A/en
Application granted granted Critical
Publication of CN100518450C publication Critical patent/CN100518450C/en
Expired - Fee Related legal-status Critical Current
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679Aligning added circuit layers or via connections relative to previous circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0269Marks, test patterns or identification means for visual or optical inspection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

The invention relates to a method for producing substrates (200) which are produced by successive planar process steps and which comprise a first layer (210) and at least one second layer (220) suited to the first layer (210). In a first step, a plurality of marks (211) is measured on the first layer (210) and a deviation of the actual position from the desired position is determined for every mark (211). These deviations are used to determine a transformation FTrans 1 for the position deviation from any grid point of the first layer (210) and a transformation FTrans 2 for any position deviation from grid points of the second layer (220). The transformation FTrans 2 is determined while taking into account known marginal conditions for a possible warping behavior of the second layer. When the second layer (220) is treated, a combined transformation from the two previously determined transformations FTrans 1 and FTrans 2 is taken into account. The inventive method allows for a reliable contacting of strip conductors despite different degrees of warping of the two layers (210, 220), thereby reducing the portion of refuse of defect circuit boards in the production of multilayer circuit boards.

Description

The manufacture method of substrate
Technical field
The present invention relates to the manufacture method of MULTILAYER SUBSTRATE, wherein by continuous two-dimensional process step with ground floor and at least one second layer manufacturing MULTILAYER SUBSTRATE with the ground floor coupling.
Background technology
In the construction process of multilayer circuit board, each of circuit board be mutual extrusion layer repeatedly.The temperature and the compression that are applied during this is handled cause unnecessary deformation at the material that is used for circuit board, for example shrink or elongation.In different extrusion operations, circuit board can change their size several times before completion status.According to the layout of circuit board, just the printed circuit cable structure that is realized by the copper surface in single layer nonlinear deformation may occur equally, and wherein the elongation of different directions or contraction cause varying strength.
For the different printing conductor structure that can will form in different layers in the mode of selecting in the circuit board of multi-ply construction is electrically connected each other, when being necessary when making circuit board and when applying the different joint face of plating different printing conductor structure perpendicular to layer plane ground through hole at coat, the distortion that occurs in the tracking initiation layer.In order to follow the tracks of these distortion, on initiation layer, apply or the mark that exhumes usually, mark is by optical system measuring.According to the physical location of these marks and the deviation between the ideal position, obtain the distortion of initiation layer.In order to determine this distortion for all grid points of initiation layer, determine mathematic(al) manipulation according to previous resulting deviation, can calculate distortion for any grid point of initiation layer by means of this mathematic(al) manipulation.Here, the term grid point refers to any point of initiation layer, in other words, is not the Chosen Point that only refers to be positioned on the discrete grid block.
Conversion from the ideal position to the physical location can determined in the x-y coordinate system according to following equation 1:
x actual=a 1+b 1·x desired+c 1·y desired+d 1·x desired·y desired
y actual=a 2+b 2·y desired+c 2·x desired+d 2·x desired·y desired
During this process, parameter a1 and a2 have described linear deformation, and parameter b 1, b2, c1 and c2 have described elongation or shunk and rotation, and parameter d 1, d2 have been described the shearing of contingent initiation layer.Because this equation system comprises four parameter a to be determined, b, c and d for each coordinate, so must measure four marks altogether to determine these parameters fully, this just means, resulting equation system can be found the solution uniquely by using altogether eight unknown parameters.
It should be noted that for many application scenarios, the shearing of initiation layer can be left in the basket, thereby coefficient d 1 and d2 can be set to zero.In this case, measure three marks and just be enough to determine uniquely remaining parameter a1, a2, b1, b2, c1 and c2.
But different layers show different deformation characteristics usually, and perhaps owing to technical matters process aspect, layer afterwards can not be followed the tracks of the certain variations of following layer.In this case, when using equation 1 described conversion, the joint face of different printing conductor structure usually each other skew ground arrange, thereby make must in conjunction with joint face between the overlapping reliable electric connection that often can not realize corresponding joint face inadequately greatly.Therefore, the circuit board of Zhi Zaoing is normally defective by this way, and must pick out from manufacturing process.
Summary of the invention
Therefore, the purpose of this invention is to provide the manufacture method of MULTILAYER SUBSTRATE, even wherein deform, also can guarantee the reliable connection between the selection area of different layers, thereby can obtain lower discarded rate in the circuit board made from layer formal construction.
This purpose realizes by the method that comprises independent claims 1 feature, is used to make the substrate of constructing in layer mode.
According to the present invention, at first, added a plurality of these layers that are marked at are gone up measuredly on the ground floor, and determine deviation between the ideal position of measured physical location and previously known for each mark subsequently.According to determined deviation, be identified for determining two different conversion of the position deviation of ground floor grid point, wherein in determining these two conversion at least one the time, consider constraints for the previously known of the possible position deviation of the grid point of the second layer.Here, constraints is by using the corresponding relation between parameter a, b, c and the d in the above-mentioned equation 1, stipulating by rights.Then, resulting two conversion are combined, and process ground floor by the conversion of considering combination.
The present invention is based on following understanding, during the processing of the second layer, is not the distortion of only considering initiation layer promptly, but has considered in advance at least in part that when applying the second layer possible technical process limits when this distortion of compensation.Therefore, when the processing ground floor, have a mind to accept the non-optimal compensation of initiation layer distortion.This in most of the cases obvious defective when applying the second layer by full remuneration.
Should be noted that for example, camera can be used for measurement markers, camera just existed during making the substrate of constructing in layer mode originally, and was commonly used to determine the position of substrate to be made.
According to claim 2,, bore some holes and pass through ground floor by considering the conversion of combination.Then, indirectly by the consideration bore position, or, then the second layer is coated on the ground floor of process boring processing directly by considering the conversion of combination.The different joint faces of boring-can be blind hole or through hole-be used for especially in the different layers combine.Here, be electrically connected by respective bore is metallized and realize.
According to claim 3, preferably come manufacturing hole by laser beam.This is favourable, because during use is used for MULTILAYER SUBSTRATE being carried out the modern laser process equipment of laser drill, can realize high yield, just time per unit gets out a large number of hole.In addition, it is fully little that the bulk in hole can keep, and makes the high packaging density that can realize electronic building brick on the circuit board of constructing in layer mode.
According to claim 4, when processing ground floor (210),, between the ground floor (210) and the second layer (220), form the intermediate layer by considering the conversion of combination.This is favourable, because perpendicular to aspect, always can realize maximum overlapping between the selection area of all layers.
According to claim 5, the number of measured mark can change.Therefore, only measuring between two mark phases,, can only consider that deviation adds elongation or shrinks or rotation by means of these two conversion.Measuring between three mark phases, except the deviation of initiation layer, it is also conceivable that elongation or contraction, and rotation.When measuring four marks, compare with the measurement of three marks, can additionally consider by the caused shearing of the effect of shearing force.
It should be noted, obviously can measure mark to be measured respectively more than minimal amount.Therefore, can set up the equation system of the excessive identification (overidentification) that comprises transformation parameter, this system can be used to determine more accurately each transformation parameter (especially, by asking average) by favourable mode.For this process, can expect solving the conventional method of the equation system of excessive identification.
According to the method for claim 6, wherein for the second layer, got rid of shearing force, have the important significance of putting into practice, comprise exposure usually because construct substrate in layer mode, be used to form the printed circuit cable structure.The exposure of this technical matters process normally by using mask to carry out, wherein can only be considered (may be different in the x and y direction) elongation or contraction of ground floor.But the interior angle of the mask of quadrature is defined as 90 ° regularly usually.Therefore, above-mentioned parameter d1 of this conversion-wherein and the d2 so-called orthogonal transform that equals zero-also be known as.
According to claim 7, the weighted superposition of these two conversion is used as combination., use weighting factor z here, this factor is determined the ratio of second conversion in total conversion.Preferably, divided by using with the surface size of the selection area of ground floor respectively and being used for the surface size sum of the selection area of the second layer, obtain weighting factor z by the surface size of the selection area that is respectively applied for ground floor.Especially, selection area is the joint face that forms on the ground floor and/or the second layer, is used for forming between each layer being electrically connected.
According to Claim 8, selection area is the joint face that is used for ground floor is connected to the second layer, makes by the connection perpendicular to the aspect execution, can be optionally in conjunction with the printed circuit cable structure that forms on the different layers.
Description of drawings
Can find out further advantage of the present invention and feature by the exemplary illustration of preferred embodiment hereinafter.
Fig. 1 comprises two different printing conductor structures that connect by laser drill by illustrating known circuit board in the technology of having, and
Fig. 2 illustrates the manufacturing of circuit board according to an embodiment of the invention, and wherein the reliable connection between the different printing conductor structure is that laser drill by the bore position place realizes that these bore positions are to be determined by the combination of different conversion.
Herein, the identifier that is noted that respective element among the figure only is different on first digit.
Embodiment
Fig. 1 a and Fig. 1 b illustrate the manufacturing according to the circuit board 100 of constructing in layer mode of prior art.The structure of circuit board 100 starts from the ground floor 110 that has added four marks 111.The position of these marks is measured, and according to the definite conversion according to equation 1 of the deviation between physical location and the ideal position separately, determines the distortion of all grid points of ground floor 110 by this conversion.Usually, for all grid points, can obtain this distortion at an easy rate.
According to the embodiment that illustrates now, the printed circuit cable structure that forms on the ground floor 110 comprises six first joint faces 112 altogether, and these six joint faces are divided into two groups, and each group comprises three first joint faces 112.Joint face 112 in this each group of two groups connects by two first printed circuit cables 113.
Because the distortion of each grid point of ground floor 110 can be easy to be calculated under the situation of using equation 1, so can make and make boring 114,114a substantially at the middle part of illustrated first joint face 112 by corresponding activation laser drilling machine (not shown) to ground floor 110 borings.Therefore, by on purpose selecting bore position to have compensated the distortion of ground floor 110 near optimal mode.
Hereinafter, the second layer 120 is applied on the ground floor, and the ground floor 110 and the second layer 120 separate by the insulating barrier (not shown).According to the embodiment that illustrates now, the second layer 120 comprises 12 joint faces 122,122a altogether, and these joint faces have been formed the printed circuit cable structure of the second layer 120 with second printed circuit cable 123.Use the exposure method (not shown), be used for constructing this printed circuit cable structure, wherein use exposed mask, wherein can optionally select elongation or contraction, but the corner region of mask is set at 90 ° of angles regularly.Therefore, only by be offset 130, the elongation of ROT13 1 and the mask that is used to expose or shrink (not shown), can adjust the second layer 120 to be fit to the printed circuit cable structure of ground floor 110.Therefore, boring 114a is special only to be formed in the perimeter of joint face 122a, thereby only forms connection bad between the joint face 112 of mutual offset alignment and the 112a or even the connection that is interrupted.
It should be noted, for passing through modern laser drilling machine little connecting hole in the cards, nuance between second distortion of undesirable first distortion of ground floor 110 and the hope of the second layer 120 may cause big deviation like this between the joint face to be connected, to such an extent as to no longer may perpendicular to the connection of aspect.
Fig. 2 a and Fig. 2 b illustrate the manufacture process of the circuit board of constructing in layer mode of according to a present invention currently preferred embodiment.This manufacture process and different being of known fabrication shown in Fig. 1 a and Fig. 1 b, bore position 214,214a not only optimize the joint face 212 of ground floor 210.On the contrary, the limited distortion possibility of the second layer 220 is also considered in the selection of bore position in addition.Existing in an illustrated embodiment, be subjected to the distortion possibility of the second layer 220 of the orthogonality restriction of exposed mask in the selection of bore position 214,214a, to obtain considering.This just means, the selection of bore position 214,214a has a mind to have abandoned optimal placed in the middle with respect to joint face 212.Under any circumstance, by the joint face 222 that has boring 214, the second layer 220 of 214a, better overlapping this generally only obvious defective that compensates of 222a.
Use total conversion G to determine not to be positioned at usually the boring 214 at joint face 212 centers, particularly determine boring 214a, this conversion is described by following equation 2:
x y actual = G · x y desired = ( 1 - z ) · F trans 1 x y desired + z · F trans 2 x y desired
Here, F Trans1Be to use above-mentioned transformation parameter a 1, a 2, b 1, b 2, c 1, c 2, d 1And d 2A kind of conversion.F Trans2In consider the orthogonality of exposed mask in the following manner, i.e. this conversion only comprises transformation parameter a 1, a 2, b 1, b 2, c 1And c 2By these two conversion F Trans1And F Trans2Set of weights incompatiblely determine total conversion G, and weighting factor z can select between 0 and 1.Weighting factor z=1 represents only according to orthogonal transform F Trans2Carry out manufacture process.If select weighting factor z=0, that is just only represented according to algorithm F Trans1Carry out manufacture process.Under the situation of z=0.5, conversion F Trans1And F Trans2In total conversion G is impartial weighting.
If determine weighting factor z according to following equation 3, the ideal effect of the joint face that is just reliably connected, wherein equation 3 is:
z = tolerance layer 1 tolerance layer 1 + tolerance layer 2
Here, the tolerance of layer 1 and layer 2 is determined by the size of corresponding joint face in layer 1 and the layer 2 respectively.Therefore, for example the joint face of ground floor 1 than the second layer 2 under the big a lot of situation of joint face, only be slightly less than 1 numerical value z.This just means that total conversion is mainly by conversion F Trans2Determine.
In a word, can draw as drawing a conclusion: the invention provides a kind of manufacture method of substrate 200, wherein this substrate is made by continuous two-dimentional processing step, to comprise ground floor 210 and at least one second layer 220 of adjusting according to this ground floor.At first, on ground floor 210, measure some marks 211, and be the deviation that each mark 211 is determined physical location and ideal position.According to these deviations, determine the conversion F of position deviation of the arbitrary mess point of ground floor 210 Trans1, and the conversion F of the possible position deviation of the grid point of definite second layer 220 Trans2As definite conversion F Trans2The time, considered constraints to the previously known of the possible deformation characteristic of the second layer.During processing the second layer 220 subsequently, consider previous two conversion F that determine Trans1And F Trans2Combined transformation.Therefore,, also can guarantee the reliable connection of printed circuit cable, thereby make during the manufacturing of multilayer circuit board, produce less defectiveness circuit board waste product even these two layers 210,220 have different distortion.
Reference numerals list
100 circuit boards
110 ground floors
111 marks
112 first joint faces
113 first printed circuit cables
114 borings
114a boring
120 second layers
122 second joint faces
The joint face of the bad connection of 122a
123 second printed circuit cables
130 skews
131 rotations
200 circuit boards
210 ground floors
211 marks
212 first joint faces
213 printed circuit cables
214 borings
214a is not in the boring at center
220 second layers
222 second joint faces
The reliable joint face that connects of 222a
223 printings
230 skews
231 rotations

Claims (3)

1. method that is used to make substrate (200), described substrate are to make with ground floor (210) and at least one second layer (220) of being coated to described ground floor by continuous two-dimentional processing step, wherein
Upward measure a plurality of marks (211) that are applied on the described ground floor (210) at described ground floor (210),
Determine the deviation between the ideal position of physical location and previously known for each mark (211), the ideal position of wherein said previously known is predetermined by the layout designs of described ground floor (210),
Determine first conversion according to the previous deviation of determining, be used for the position deviation of the arbitrary mess point of definite described ground floor (210),
Determine second conversion according to the previous deviation of determining, be used for the possible position deviation of the grid point of definite described second layer (220),
The weighting factor that utilization is determined according to the tolerance of the described ground floor (210) and the described second layer (220), with described two conversion combination, and
By calculating the conversion of described combination, process described ground floor (210).
2. method according to claim 1, the weighted superposition of wherein said two conversion is used as combination, and the two-dimensional measurement of wherein passing through the selection area of described two layers (210,220) obtains corresponding weighting factor.
3. method according to claim 1 and 2, wherein said selection area comprise joint face (212,222,222a), be used for described ground floor (210) is connected to the described second layer (220).
CNB2005800007813A 2004-02-17 2005-01-18 Method for producing substrates Expired - Fee Related CN100518450C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004007625 2004-02-17
DE102004007625.1 2004-02-17

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CN1860835A CN1860835A (en) 2006-11-08
CN100518450C true CN100518450C (en) 2009-07-22

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CN (1) CN100518450C (en)
WO (1) WO2005081603A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102971674B (en) 2010-02-26 2015-07-15 密克罗尼克麦达塔公司 Method and apparatus for performing pattern alignment
CN111579561B (en) * 2020-05-07 2021-02-19 维嘉数控科技(苏州)有限公司 Position point compensation method, device, equipment and storage medium

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432037A (en) * 1980-12-02 1984-02-14 Siemens Aktiengesellschaft Multi-layer printed circuit board and method for determining the actual position of internally located terminal areas
DE3642926A1 (en) * 1986-12-16 1988-06-30 Siemens Ag Arrangement and method for identifying displacement of the internal layers of multilayer printed circuit boards
US4915981A (en) * 1988-08-12 1990-04-10 Rogers Corporation Method of laser drilling fluoropolymer materials
EP0506217A3 (en) * 1991-03-27 1993-01-13 Klaus Schneider Method for measuring deviations of the layers in a multilayer device and apparatus to realise this method
US5529441A (en) * 1994-02-28 1996-06-25 Cybernetics Products, Inc. Drill coordinate optimization for multi-layer printed circuit board
DE19534313A1 (en) * 1995-09-15 1997-03-20 Imr Electronic Gmbh & Co Kg Method for determining the position and offset of layers on multilayer boards

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432037A (en) * 1980-12-02 1984-02-14 Siemens Aktiengesellschaft Multi-layer printed circuit board and method for determining the actual position of internally located terminal areas
DE3642926A1 (en) * 1986-12-16 1988-06-30 Siemens Ag Arrangement and method for identifying displacement of the internal layers of multilayer printed circuit boards
US4915981A (en) * 1988-08-12 1990-04-10 Rogers Corporation Method of laser drilling fluoropolymer materials
EP0506217A3 (en) * 1991-03-27 1993-01-13 Klaus Schneider Method for measuring deviations of the layers in a multilayer device and apparatus to realise this method
US5529441A (en) * 1994-02-28 1996-06-25 Cybernetics Products, Inc. Drill coordinate optimization for multi-layer printed circuit board
DE19534313A1 (en) * 1995-09-15 1997-03-20 Imr Electronic Gmbh & Co Kg Method for determining the position and offset of layers on multilayer boards

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JP2007522662A (en) 2007-08-09
WO2005081603A1 (en) 2005-09-01
CN1860835A (en) 2006-11-08

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