CN100514651C - Semiconductor device and method of making semiconductor devices - Google Patents
Semiconductor device and method of making semiconductor devices Download PDFInfo
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- CN100514651C CN100514651C CNB2006100095647A CN200610009564A CN100514651C CN 100514651 C CN100514651 C CN 100514651C CN B2006100095647 A CNB2006100095647 A CN B2006100095647A CN 200610009564 A CN200610009564 A CN 200610009564A CN 100514651 C CN100514651 C CN 100514651C
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- E—FIXED CONSTRUCTIONS
- E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
- E05B—LOCKS; ACCESSORIES THEREFOR; HANDCUFFS
- E05B1/00—Knobs or handles for wings; Knobs, handles, or press buttons for locks or latches on wings
- E05B1/003—Handles pivoted about an axis perpendicular to the wing
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
An SOI forming region (R1) for forming an SOI structure and a bulk region (R2) for forming a bulk structure are provided on a semiconductor substrate (11). In the SOI forming region (R1), a semiconductor layer (14) is formed on the semiconductor substrate (11) by epitaxial grow through an insulation layer (13), the sidewall of the semiconductor layer (14) is exposed, and a gate electrode (17a) is formed to be extended on the sidewall of the semiconductor layer (14). In the bulk region (R2), a semiconductor layer (15) is formed on the semiconductor substrate (11) and a gate electrode (17b) is arranged on the semiconductor layer (15). Therefor, an SOI structure and a bulk structure form on the same substrate without employing an SOI substrate, and reduce a layout area of an SOI transistor.
Description
Technical field
The present invention relates to the manufacture method of a kind of semiconductor device and semiconductor device, particularly relate to a kind of being applicable to soi structure and the manufacture method that becomes piece (bulk) structure to mix to be loaded in the semiconductor device and the semiconductor device of the method on the same substrate.
Background technology
Being formed on FET on the SOI substrate has easiness, latch-up-free, source/drain junction electric capacity that element separates former thereby its serviceability such as little and receives much concern.Particularly, depletion type SOI transistor can be realized low consumpting power and high speed motion fully, carries out low voltage drive easily, therefore carries out energetically in order to move the transistorized research of SOI down with complete depletion-mode.At this, for example disclosed such in patent documentation 1,2 as the SOI substrate, adopted SIMOX (Separationby Implanted Oxgen) substrate or adhesive base plate etc.
At this, adopting the SOI transistor to constitute under the situation of CMOS (Complementally Metal OxideSemiconductor) circuit, P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn adjoin each other on same 2 dimensional planes and dispose, and are formed on simultaneously and hold { on the semiconductor surface in 100} face orientation.
On the one hand, current driving capability is big and need high withstand voltage field-effect transistor to be difficult to be formed on the SOI substrate that limits the thickness that silicon layer is arranged, and is expected to be formed on on piece (bulk) substrate.
In addition, following method is for example disclosed in patent documentation 3: for the silicon thin film that forms crystallinity and have good uniformity on large-area dielectric film, by on noncrystalline on the dielectric film or polysilicon layer, ultraviolet beam being shone into pulse type in film forming, be formed on the dielectric film approaching the polysilicon film that foursquare single die is aligned to lattice-like, and planarization carried out on the surface of this polysilicon film with CMP (chemical formula mechanical polishing).
Patent documentation 1: the spy opens communique 2002-No. 299591;
Patent documentation 2: the spy opens communique 2000-No. 124092;
Patent documentation 3: the spy opens flat 10-No. 261799 communiques.
But, when making the SIMOX substrate, need inject the oxygen of high concentration to the silicon wafer ion.In addition, when making adhesive base plate, after bonding 2 silicon wafers, the surface that needs to grind silicon wafer.Therefore in the SOI transistor be formed on into block semiconductor in FET compare the problem that has the increase that causes cost.
In addition,, make soi layer carry out filming, the problem of the stability of characteristicsization of FET then occurs being difficult to making in order to make complete depletion type SOI transistor if inject or to grind the deviation of thickness of soi layer big at ion.
In addition,, the required area of cmos circuit then occurs being used to form and increase, become the problem of the integrated obstacle of high density if P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn are configured on same 2 dimensional planes.In addition, occur the required length of arrangement wire that is connected of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn is also increased, propagation delay becomes big problem.And, if { form cmos circuit on the semiconductor surface in 100} face orientation, then need the channel width of P-channel field-effect transistor (PEFT) transistor npn npn to be set at 2～3 times of channel width of N channel field-effect transistor npn npn holding from the difference of the degree of excursion in electronics and hole.Therefore, the configuration balance that occurs between P-channel field-effect transistor (PEFT) transistor npn npn and the N channel field-effect transistor npn npn is broken, and becomes the problem of the highly integrated obstacle of element.
In addition, in being formed on silicon thin film on the dielectric film, the method for utilizing patent documentation 3 has paddy boundary, two miniature etc. tiny flaw.Therefore be formed on the transistor that the transistor AND gate on this silicon thin film is formed on the complete crystal silicon film and compare the problem that its characteristic variation occurs.And under the stacked situation that is formed on the FET on the silicon thin film, FET is positioned at lower floor.Therefore the flatness deterioration of basic dielectric film of the silicon thin film on upper strata occurs forming, the heat-treat condition when forming the silicon thin film on upper strata etc. relates to restriction simultaneously, and the crystallinity of the silicon thin film on upper strata is than the problem of the crystallinity difference of the silicon thin film of lower floor.
Therefore, in semiconductor device in the past, the device of holding the soi structure that is made of flawless monocrystalline can not mixed and be loaded in on the piece silicon.In addition, can not realize holding stacked the device of 3 dimension structures of complete crystal silicon film with various thickness.
Summary of the invention
Therefore, the object of the present invention is to provide and a kind ofly do not use the SOI substrate and soi structure and blocking architecture are formed on the same substrate, can reduce the semiconductor device of the transistorized configuration area of SOI and the manufacture method of semiconductor device simultaneously.
In order to solve above-mentioned problem, the semiconductor device according to a relevant mode of the present invention is characterized in that, possesses: semiconductor substrate, and its zone in a part has formed insulating barrier; Semiconductor layer, it is configured on the above-mentioned insulating barrier and with epitaxial growth and comes film forming; The 1st gate electrode, it to be to cross over the mode of the part of above-mentioned semiconductor layer across the 1st gate insulating film ground, extend to the side walls of above-mentioned semiconductor layer and form; The 1st source/drop ply, it is formed on the above-mentioned semiconductor layer and is configured in the side of above-mentioned the 1st gate electrode respectively; The 2nd gate electrode, it is formed on the above-mentioned semiconductor substrate across the 2nd gate insulating film; The 2nd source/drop ply, it is formed on the semiconductor layer on the above-mentioned semiconductor substrate, and is configured in the side of above-mentioned the 2nd gate electrode respectively; The side of above-mentioned semiconductor layer of holding above-mentioned the 1st gate electrode is by { 110} face or { the 100} face constitutes, and the surface of above-mentioned semiconductor substrate of holding above-mentioned the 2nd gate electrode is by { the 100} face constitutes.
Thus, do not use the SOI substrate and can form soi structure in a part of zone of semiconductor substrate, simultaneously can be at the sidewall configuration channel region of semiconductor layer.Therefore can suppress the increase of cost and soi structure and blocking architecture are formed on the same semiconductor substrate, can improve the transistorized integrated level of SOI simultaneously, suppress the increase of chip size, and can realize SOC (SystemOn Chip).
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that, the side of semiconductor layer of holding above-mentioned the 1st gate electrode is by { 110} face or { the 100} face forms, and the surface of semiconductor substrate of holding above-mentioned the 2nd gate electrode is by { the 100} face forms.
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that, possesses:
Semiconductor substrate, its zone in a part has formed insulating barrier; The the 1st and the 2nd semiconductor layer, it is laminated on the above-mentioned insulating barrier and with epitaxial growth and comes film forming; The P-channel field-effect transistor (PEFT) transistor npn npn, its sidewall at above-mentioned the 1st semiconductor layer has disposed channel region; N channel field-effect transistor npn npn, its sidewall at above-mentioned the 2nd semiconductor layer has disposed channel region; P raceway groove or N channel field-effect transistor npn npn, its be formed on the above-mentioned semiconductor substrate and in the surface configuration of above-mentioned semiconductor substrate channel region, the above-mentioned the 1st and the sidewall of the 2nd semiconductor layer be { 100} face or { 110} face orientation.
Thus, can carry out 3 dimension configurations to P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, and can constitute CMOS inverter, NAND circuit or NOR circuit etc., high pressure-resistant apparatus can be mixed being loaded on the same plane simultaneously.Therefore suppress the increase of chip size, the element with various functions can be formed on the same chip, suppress the increase of cost simultaneously, and can hold good characteristic.
In addition, semiconductor device according to a relevant mode of the present invention, it is characterized in that possessing: gate electrode, it is configured in the above-mentioned the 1st and the sidewall of the 2nd semiconductor layer and jointly being formed on above-mentioned P-channel field-effect transistor (PEFT) transistor npn npn and the above-mentioned N channel field-effect transistor npn npn; The 1st source/drop ply, its mode with the both sides that are configured in above-mentioned gate electrode is formed on above-mentioned the 1st semiconductor layer; The 2nd source/drop ply, its mode with the both sides that are configured in above-mentioned gate electrode is formed on above-mentioned the 2nd semiconductor layer.
Thus, can form channel region, need not gate electrode is configured in the surface of semiconductor layer and can constitutes FET at the side of semiconductor layer.Therefore, even under the situation that has formed FET on the semiconductor layer, also can guarantee the flatness of the face side of semiconductor layer, the crystalline deterioration that can suppress semiconductor layer, and can stacked P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn.Its result, with low voltage, high-speed action P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, and it is integrated to seek the high density of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn.
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that, the above-mentioned the 1st and the sidewall of the 2nd semiconductor layer be that { 100} face, the thickness of above-mentioned the 1st semiconductor layer are in 2～3 times the scope of thickness of above-mentioned the 2nd semiconductor layer.
Thus, compare layout (Layout) area that need not to enlarge the P-channel field-effect transistor (PEFT) transistor npn npn, can be set as the width that makes the P-channel field-effect transistor (PEFT) transistor npn npn width greater than N channel field-effect transistor npn npn with N channel field-effect transistor npn npn.Therefore, even under the P-channel field-effect transistor (PEFT) transistor npn npn situation different with the mobility of N channel field-effect transistor npn npn, also can keep the balance of layout (Layout) configuration between P-channel field-effect transistor (PEFT) transistor npn npn and the N channel field-effect transistor npn npn, and can make the P-channel field-effect transistor (PEFT) transistor npn npn become consistent with the current driving ability of N channel field-effect transistor npn npn.Its result can carry out the layout designs of cmos circuit effectively, relaxes the restriction of signaling rate simultaneously and seek the high density of semiconductor device integrated, can seek the high speed of semiconductor device simultaneously.
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that, the above-mentioned the 1st and the sidewall of the 2nd semiconductor layer be { 110} face orientation.
Thus, need not differently to set the layout area of N channel field-effect transistor npn npn and P-channel field-effect transistor (PEFT) transistor npn npn and make the P-channel field-effect transistor (PEFT) transistor npn npn roughly become consistent with the mobility of N channel field-effect transistor npn npn.Therefore, can access the balance of the parasitic capacitance of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, and obtain the current drives balance of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, the S/N ratio of cmos circuit be can improve, the high speed and the densification of semiconductor device sought simultaneously.
In addition; semiconductor device according to a relevant mode of the present invention; it is characterized in that; on above-mentioned semiconductor substrate, form protection diode, bipolar transistor, analog element or high voltage drive FET, on above-mentioned semiconductor layer, form digital element or low voltage drive FET.
Thus, can seek to be formed on high withstand voltageization of the device on the semiconductor substrate and seek to be formed on the high speed and the low consumption electrification of the device on the semiconductor layer, the device of holding good characteristic and will holding various functions can be mixed being loaded on the same chip.
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that, possesses:
To be formed on the operation of a part on the surface of semiconductor substrate with the 1st semiconductor layer of epitaxial growth film forming; With its rate of etch than also little the 2nd semiconductor layer of above-mentioned the 1st semiconductor layer with the operation of epitaxial growth film forming on above-mentioned the 1st semiconductor layer and semiconductor substrate; Constitute and be formed on the operation of the supporter of above-mentioned the 2nd semiconductor layer of above-mentioned semiconductor substrate upper support than the also little material of above-mentioned the 1st semiconductor layer by its rate of etch; The operation of exposed division of the part of above-mentioned the 1st semiconductor layer is exposed in formation; By the 1st semiconductor layer selectively being carried out etching, the hole portion of having removed above-mentioned the 1st semiconductor layer is formed on operation between above-mentioned semiconductor substrate and above-mentioned the 2nd semiconductor layer by means of above-mentioned exposed division; Formation is embedded in the operation of the buried insulating layer in the portion of above-mentioned hole; The operation of exposing the sidewall of above-mentioned the 2nd semiconductor layer; Formation comprises the 1st transistorized operation of the 1st gate electrode and the 1st source/drop ply, above-mentioned the 1st gate electrode is to cross over the mode of the part of above-mentioned the 2nd semiconductor layer across the 1st gate insulating film ground, extend to the side walls of above-mentioned the 2nd semiconductor layer and form, above-mentioned the 1st source/drop ply is formed on above-mentioned the 2nd semiconductor layer, and is configured in the side of above-mentioned the 1st gate electrode respectively; Comprise the 2nd transistorized operation of the 2nd gate electrode and the 2nd source/drop ply with formation, above-mentioned the 2nd gate electrode is formed on the above-mentioned semiconductor substrate across the 2nd gate insulating film, above-mentioned the 2nd source/drop ply is formed on above-mentioned the 1st semiconductor layer, and is configured in the side of above-mentioned the 2nd gate electrode respectively; And, will hold above-mentioned the 1st gate electrode above-mentioned semiconductor layer the 110} face or the 100} face is as the side of this semiconductor layer, will hold above-mentioned the 2nd gate electrode above-mentioned semiconductor substrate { the 100} face is as the surface of this semiconductor substrate.
Thus, can directly remove the 1st semiconductor layer after residual the 2nd semiconductor layer, can under the 2nd semiconductor layer, form hole portion, under the situation that has formed hole portion under the 2nd semiconductor layer, also can the 2nd semiconductor layer be supported on the semiconductor substrate enough supporters simultaneously.In addition, the exposed division that exposes the part of the 1st semiconductor layer by setting, stacked on the 1st semiconductor layer also can be on the 1st semiconductor layer under the situation of the 2nd semiconductor layer with etching gas or etching solution contact, can directly remove the 1st semiconductor layer after residual the 2nd semiconductor layer, can imbed hole portion under the 2nd semiconductor layer with insulating barrier simultaneously.
Therefore, can reduce the generation of defects of the 2nd semiconductor layer and the 2nd semiconductor layer is configured on the insulating barrier, not damage the quality of the 2nd semiconductor layer and can seek insulation between the 2nd semiconductor layer and the semiconductor substrate.
And, by forming the 1st transistor after the sidewall that exposes the 2nd semiconductor layer, can be at the sidewall configuration channel region of the 2nd semiconductor layer, in the part on the surface by the 1st semiconductor layer being formed on semiconductor substrate, soi structure and blocking architecture can be formed on the same semiconductor substrate simultaneously.Therefore can suppress the increase of chip size, and the element with function of holding good characteristic can be formed on the same chip, simultaneously soi structure and blocking architecture are being mixed the increase that also can suppress cost under the situation about being loaded on the same semiconductor substrate.
In addition, the semiconductor device according to a relevant mode of the present invention is characterized in that,
Above-mentioned supporter is an element separating insulation film.
Thus, under the situation that has formed hole portion under the 2nd semiconductor layer, also the 2nd semiconductor layer can be supported on the semiconductor substrate with separating insulation film.Therefore, need not to be provided with in addition the operation of the supporter that is formed for supporting the 2nd semiconductor layer, need not to guarantee in addition to be used to form the zone of supporter simultaneously.Therefore, can suppress the increase of manufacturing process and soi structure and blocking architecture are formed on the same semiconductor substrate, the high density that can seek simultaneously to be formed on the device on the semiconductor substrate is integrated, the element that can suppress the increase of chip size and will have various functions of holding good characteristic is formed on the same chip, is loaded in the increase that also can suppress cost on the same semiconductor substrate in that soi structure and blocking architecture are mixed simultaneously.
Description of drawings
Fig. 1 is the stereogram that the summary of the semiconductor device of relevant the 1st execution mode of the present invention of expression constitutes.
Fig. 2 is the stereogram that the summary of the semiconductor device of relevant the 2nd execution mode of the present invention of expression constitutes.
Fig. 3 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 4 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 5 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 6 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 7 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 8 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Fig. 9 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Figure 10 is the figure of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention.
Among the figure: R1, R11, R21-SOI forms the zone, R2, R12, R22-one-tenth piece zone, 1,2,31-semiconductor substrate, 12,22,36-element separating insulation film, 13,23a, 23b, 39-insulating barrier, 14,15,24a, 24b, 25-semiconductor layer, 16a, 16b, 26a～26c, 40a, 40b-gate insulating film, 17a, 17b, 27a～27c, 41a, 41b-gate electrode, 18,28-sidewall pad, 19a, 19a ', 19b, 19b ', 29a～29c, 29a '～29c '-source/drop ply, 32-oxide-film, 33-the 1 semiconductor layer, 34-the 2 semiconductor layer, 35-ditch, 37-expose face, 38-hole portion.
Embodiment
Below, with reference to the semiconductor device and the manufacture method thereof of the relevant embodiments of the present invention of description of drawings.
Fig. 1 is the stereogram that the summary of the semiconductor device of relevant the 1st execution mode of the present invention of expression constitutes.
In Fig. 1, semiconductor substrate 11 is provided with the SOI formation region R 1 that forms soi structure and is formed into block structured and becomes piece region R 2.And, in semiconductor substrate 11, imbed SOI formation region R 1 and one-tenth piece region R 2 carried out the element separating insulation film 12 that element separates.In addition, as SOI being formed region R 1 and becoming piece region R 2 to carry out the method that element separates, except STI (Shallow low Trench Isolation) structure, can also use LOCOS (LocalOxidation Of Silicon) structure.And, form in the region R 1 at SOI, on semiconductor substrate 11, be laminated with by the semiconductor layer 14 of insulating barrier 13 with the epitaxial growth film forming.In addition, the material as semiconductor substrate 11 and semiconductor layer 14 for example can use Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe etc., as insulating barrier 12a, 13, for example can use SiO
2, SiON or Si
3N
4, etc. insulating barrier or imbed dielectric film.In addition, be laminated in semiconductor substrate on the insulating barrier 13, for example can use the SOI substrate,, can use SIMOX (Separation by Implanted Oxgen) substrate, adhesive base plate or laser annealing etc. as the SOI substrate as semiconductor layer 14.
And semiconductor layer 14 is to expose the etched processing of mode of sidewall on insulating barrier 13.At this, under the situation of the sidewall that exposes semiconductor layer 14, can be to have the mode etching and processing semiconductor layer 14 of the part that has comprised semiconductor layer 14.In addition, under the situation of the sidewall that exposes semiconductor layer 14, for example also can use the shape of fin (fin) shape, pectination, square shape or mesh-shape etc.And, be formed with gate electrode 17a by gate insulating film 16a at the sidewall of semiconductor layer 14.At this, gate electrode 17a can comprise that the part of semiconductor layer 14 and the mode of extending to the side walls of semiconductor layer 14 dispose with leap.In addition, on semiconductor layer 14, be formed with source/drop ply 19a, the 19a ' of the both sides that are configured in gate electrode 17a respectively.
On the other hand, in becoming piece region R 2, on semiconductor substrate 11, be formed with semiconductor layer 15.And, on semiconductor layer 15, forming gate electrode 17b by gate insulating film 16b, the sidewall at gate electrode 17b is formed with sidewall pad 18 simultaneously.In addition, on semiconductor layer 15, be formed with source/drop ply 19b, the 19b ' of the both sides that are configured in gate electrode 17a respectively.
Thus, can form soi structure in a part of zone of semiconductor substrate 11, simultaneously can be at the sidewall configuration channel region of semiconductor layer 14.Therefore, can suppress the increase of cost and soi structure and blocking architecture are formed on the same semiconductor substrate 11, can improve the transistorized integrated level of SOI simultaneously, suppress the increase of chip size, and can realize SOC (System On Chip).
In addition, forming region R 1 at SOI is preferably formed digital element or low voltage drive FET, is becoming piece region R 2 to be preferably formed protection diode, bipolar transistor, analog element or high voltage drive electric field type transistor.Thus, can seek to be formed on into high withstand voltageization of the device of piece region R 2, and can seek to be formed on high speed and low consumption electrification that SOI forms the device of region R 1, can hold good characteristic, and the device of holding various functions can be mixed and be loaded on the same chip.
Fig. 2 is the stereogram that the summary of the semiconductor device of relevant embodiments of the present invention constitutes.
In Fig. 2, semiconductor substrate 21 is provided with the SOI formation region R 11 that forms soi structure and is formed into block structured and becomes piece region R 12.And, in semiconductor substrate 21, imbed SOI formation region R 11 and one-tenth piece region R 12 carried out the element separating insulation film 22 that element separates.
And, forming in the region R 11 at SOI, configuration is disposed the semiconductor layer 24b with the epitaxial growth film forming by insulating barrier 23b by the semiconductor layer 24a of insulating barrier 23a with the epitaxial growth film forming on semiconductor layer 24a on semiconductor substrate 11.And semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b are to expose the etched processing of mode of sidewall on insulating barrier 23a.At this, under the situation of the sidewall that exposes semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b, can be to have mode etching and processing semiconductor layer 24a, insulating barrier 23b and the semiconductor layer 24b of the part that has comprised semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b.In addition, under the situation of the sidewall that exposes semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b, for example also can use the shape of fin shape, pectination, square shape or mesh-shape etc.And, be formed with gate electrode 27a by gate insulating film 26a, 26b respectively at the sidewall of semiconductor layer 24a, 24b.At this, gate electrode 12a can comprise that the part of semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b and the mode of extending to the side walls of semiconductor layer 24a, insulating barrier 23b and semiconductor layer 24b dispose with leap.Outside two, on semiconductor layer 24a, form source/drop ply 29a, the 29a ' of the both sides that are configured in gate electrode 27a respectively, on semiconductor layer 24b, be formed with source/drop ply 29b, the 29b ' of the both sides that are configured in gate electrode 27a respectively.
On the other hand, in becoming piece region R 22, on semiconductor substrate 21, be formed with semiconductor layer 25.And, on semiconductor layer 25, forming gate electrode 27c by gate insulating film 26c, the sidewall at gate electrode 27c is formed with sidewall pad 28 simultaneously.In addition, on semiconductor layer 25, be formed with source/drop ply 29c, the 29c ' of the both sides that are configured in gate electrode 27c respectively.
Thus, can form channel region at the side of semiconductor layer 24a, 24b, the face side of semiconductor layer 24a, 24b need not to dispose gate electrode 27a and can constitute FET.Therefore, even under situation about FET being respectively formed on semiconductor layer 24a, the 24b, also can guarantee the flatness of the face side of semiconductor layer 24a, 24b, even in the stacked crystalline deterioration that also can suppress semiconductor layer 24a, 24b under the situation of semiconductor layer 24a, 24b.Therefore can suppress the increase of chip size, and can seek the integrated of FET, can reduce the parasitic capacitance of FET simultaneously, and can access dangerously steep sub-threshold value (threshold) characteristic and move with low voltage, high-speed.
In addition, by disposing gate electrode 27a in the mode with the stromatolith quadrature of semiconductor layer 24a, 24b, the occupied area of the gate electrode 27a in can reducing in the chip face can make the length of arrangement wire of gate electrode 27a shorten simultaneously.Therefore, can suppress propagation delay and seek the high density of FET integrated, can dwindle chip size simultaneously and seek high speed, miniaturization and the low price of FET.
In addition, dispose gate electrode 27a by lip-deep mode with the semiconductor layer 27a that crosses over the superiors, even under the situation of having carried out the ion injection from the face side of semiconductor layer 27a, also gate electrode 27a can be formed source/ drop ply 29a, 29a ' and source/ drop ply 29b, 29b ' respectively as mask on semiconductor layer 24a, 24b.Therefore, can form source/ drop ply 29a, 29a ' and source/ drop ply 29b, 29b ' from coupling ground respectively to the gate electrode 27a of the sidewall that is configured in semiconductor layer 24a, 24b, can suppress the complicated and reproducibility of manufacturing process and make the good FET of characteristic well.
In addition, semiconductor layer 25 is made of (100) single-crystal semiconductor layer, and semiconductor layer 24a, 24b can be so that { mode exposed of the side in 100} face orientation constitutes.At this, for example the P-channel field-effect transistor (PEFT) transistor npn npn is being formed on the semiconductor layer 24a, N channel field-effect transistor npn npn is formed under the situation on the semiconductor layer 24b, also can be set as the thickness that makes semiconductor layer 24a thickness greater than semiconductor layer 24b.At this, the Film Thickness Ratio of semiconductor layer 24a and semiconductor 24b is the reciprocal proportion of the mobility of hole and electronics preferably.For example the thickness of semiconductor layer 24a can be made as in 2～3 times the scope of thickness of semiconductor layer 24b.
Thus, compare, need not to enlarge layout (Layout) area of P-channel field-effect transistor (PEFT) transistor npn npn, can be set as the width that makes the P-channel field-effect transistor (PEFT) transistor npn npn width greater than N channel field-effect transistor npn npn with N channel field-effect transistor npn npn.Therefore, even under the P-channel field-effect transistor (PEFT) transistor npn npn situation different with the mobility of N channel field-effect transistor npn npn, also can keep the balance of the layout configurations between P-channel field-effect transistor (PEFT) transistor npn npn and the N channel field-effect transistor npn npn, and can make the P-channel field-effect transistor (PEFT) transistor npn npn become consistent with the current driving ability of N channel field-effect transistor npn npn.Its result can carry out the layout designs of cmos circuit effectively, relaxes the restriction of signaling rate simultaneously and seek the high density of semiconductor device integrated, can seek the high speed of semiconductor device simultaneously.
In addition, semiconductor layer 25 can be made of (100) single-crystal semiconductor layer, and semiconductor layer 24a, 24b can be so that { mode exposed of the side in 100} face orientation constitutes.
Thus, under situation about respectively P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn being formed on semiconductor layer 24a, the 24b, also need not differently to set the layout area of N channel field-effect transistor npn npn and P-channel field-effect transistor (PEFT) transistor npn npn and make the P-channel field-effect transistor (PEFT) transistor npn npn roughly become consistent with the mobility of N channel field-effect transistor npn npn.Therefore, can access the balance of the parasitic capacitance of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, and obtain the current drives balance of P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn, the S/N ratio of cmos circuit be can improve, the high speed and the densification of semiconductor device sought simultaneously.
Fig. 3 (a)～Figure 10 (a) is the plane graph of expression about the manufacture method of the semiconductor device of the 3rd execution mode of the present invention, Fig. 3 (b)～Figure 10 (b) is the profile that A1-A '～A8-A8 ' line cuts off respectively with Fig. 3 (a)～Figure 10 (a), and Fig. 3 (c)～Figure 10 (c) is the profile that B1-B '～B8-B8 ' line cuts off respectively with Fig. 3 (a)～Figure 10 (a).
In Fig. 3, on semiconductor substrate 31, be provided with SOI and form region R 21 and become piece region R 22.And, on the surface of semiconductor substrate 31, form oxide-film 32 by carrying out the thermal oxidation of semiconductor substrate 31.In addition, as the material of semiconductor substrate 1, for example can use Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN or ZnSe etc.And form by using photoetching technique and etching technique that oxide-film 32 is carried out pattern, remove the oxide-film 32 that SOI forms region R 21, expose the surface that SOI forms the semiconductor substrate 31 of region R 21.And, the 1st semiconductor layer 33 is selectively formed on the formation of the SOI on the semiconductor substrate 31 region R 21 by oxide-film 32 is carried out the selective epitaxy growth as mask.
Then, as shown in Figure 4, remove into the oxide-film 32 on the semiconductor substrate 31 of piece region R 22.And by carrying out epitaxial growth, the SOI that the 2nd semiconductor layer 34 is formed on the semiconductor substrate 31 forms on region R 21 and the one-tenth piece region R 22.In addition, the 1st semiconductor layer 33 can use its rate of etch than semiconductor substrate 31 and the also big material of the 2nd semiconductor layer 34, can use the combined material of selection from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN or ZnSe etc. as the material of the 1st semiconductor layer 33 and the 2nd semiconductor layer 34.Be under the situation of Si particularly, as the 1st semiconductor layer 33 preferred SiGe that use, as the 2nd semiconductor layer 34 preferred Si that use at semiconductor substrate 31.Thus, can access the lattice match between the 1st semiconductor layer 33 and the 2nd semiconductor layer 34, and the selection ratio can guarantee etching between the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 time.In addition, as the 1st semiconductor layer 33, except single-crystal semiconductor layer, also can use other polycrystal semiconductor layers, noncrystalline semiconductor layer or porous matter semiconductor layer.In addition, also can use and to replace the 1st semiconductor layer 33 with the metal oxide film of γ-aluminium oxide of epitaxial growth film forming single-crystal semiconductor layer etc.In addition, the thickness of the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 can be set as about 10～200nm.
Then, as shown in Figure 5, the ditch 35 that the mode on semiconductor substrate 31 of will arriving to connect the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 has been set the degree of depth is formed on SOI and forms region R 21 and become piece region R 22 and border and on every side.And by element separating insulation film 36 is embedded in the ditch 35, SOI formation region R 21 is carried out element with one-tenth piece region R 22 separate, be formed on the supporter of semiconductor substrate 31 upper supports the 2nd semiconductor layer 34 simultaneously.
Then, as shown in Figure 6, form by using photoetching technique and etching technique that the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 are carried out pattern, form the end of exposing the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 a part expose face 37.In addition, expose in formation under the situation of exposing face 37 of a part of end of the 1st semiconductor layer 33 and the 2nd semiconductor layer 34, also can stop etching, also can carry out too much etching and on the 1st semiconductor layer 33, form recess the 1st semiconductor layer 33 on the surface of the 1st semiconductor layer 33.Or also can connect the 1st semiconductor layer 33 and the surface of exposing semiconductor substrate 31.
Then, as shown in Figure 7, by by means of expose face 37 with the contact of etching gas or etching solution on the 1st semiconductor layer 33, etching is removed the 1st semiconductor layer 33 and is formed between the semiconductor substrate 31 of region R 21 and the 2nd semiconductor layer 34 at SOI and to form hole portion 38.
At this, by supporting the 2nd semiconductor layer 34 with element separating insulation film 36, even under the situation of having removed the 1st semiconductor layer 33, can prevent that also the 2nd semiconductor layer 34 from being dropped on the semiconductor substrate 31, simultaneously by formation expose the 1st semiconductor layer 33 and the 2nd semiconductor layer 34 the end a part expose face 37, even stacked under the situation of the 2nd semiconductor layer 34 on the 1st semiconductor layer 33, also can be on the 1st semiconductor layer 33 under the 1st semiconductor layer 34 contact etch gas or etching solution.
Therefore, need not to be provided in addition supporting the supporter of the 2nd semiconductor layer 34, reduce the generation of defects of the 2nd semiconductor layer 34 simultaneously, and the 2nd semiconductor layer 34 can be configured on the insulator, do not damage the quality of the 2nd semiconductor layer 34, can seek the insulation between the 2nd semiconductor layer 34 and the semiconductor substrate 31.Therefore, can suppress the increase of manufacturing process, and soi structure and blocking architecture can be formed on the same semiconductor substrate, the element that can suppress the increase of chip size and will have various functions of holding good characteristic is formed on the same chip.
In addition, be Si at semiconductor substrate 31 and the 2nd semiconductor layer 34, the 1st semiconductor layer 33 is under the situation of SiGe, preferably uses hydrogen fluorine nitric acid (mixed liquor of hydrofluoric acid, nitric acid, water) as the etching solution of the 1st semiconductor layer 33.Thus, access about 1:100～1000, can suppress crossing etching and removing the 1st semiconductor layer 33 of semiconductor substrate 31 and the 2nd semiconductor layer 34 as the selection specific energy of Si and SiGe.In addition, also can use the mixed liquor of mixed liquor, ammonia and hydrogen peroxide of hydrofluoric acid nitric acid hydrogen peroxide or mixed liquor of hydrofluoric acid acetic acid hydrogen peroxide etc. as the etching solution of the 1st semiconductor layer 33.
In addition, before 33 etchings of the 1st semiconductor layer are removed, also can carry out porous materialization to the 1st semiconductor layer 33, also can carry out amorphous materialization to the 1st semiconductor layer 33 by the 1st semiconductor layer 33 being carried out the ion injection by methods such as anodic oxidations.Can increase the rate of etch of the 1st semiconductor layer 33 thus and enlarge the etching area of the 1st semiconductor layer 33.
Then, as shown in Figure 8,, form buried insulating layer 39 in the hole portion 10 between semiconductor substrate 31 and the 2nd semiconductor layer 34 by carrying out the thermal oxidation of semiconductor substrate 31 and the 2nd semiconductor layer 34.
Thus, the thickness of the buried insulating layer 39 during by the thickness of the 2nd semiconductor layer 34 when the epitaxial growth and the thermal oxidation at the 2nd semiconductor layer 34 can be stipulated the thickness of the 2nd semiconductor layer 34 after element separates.Therefore can control the thickness of the 2nd semiconductor layer 34 accurately, can reduce the 2nd semiconductor layer 34 thickness deviation and realize the filming of the 2nd semiconductor layer 34.
In addition, after hole portion 38 has formed buried insulating layer 39, also can carry out the high annealing more than 1000 ℃.Thus, the buried insulating layer 39 and relax the stress of buried insulating layer 39 of can refluxing can reduce the interface energy level in the border with the 2nd semiconductor layer 34 simultaneously.In addition, buried insulating layer 39 also can form according to the mode that hole portion 38 is all imbedded, and also can form according to the mode of the hole portion 38 of a residual part.
In addition, in the method for Fig. 8, by carrying out the thermal oxidation of semiconductor substrate 31 and the 2nd semiconductor layer 34, the hole portion 38 between semiconductor substrate 31 and the 2nd semiconductor layer 34 that illustrated forms the method for buried insulating layer 39, but also can the hole portion 38 usefulness buried insulating layers 39 between semiconductor substrate 31 and the 2nd semiconductor layer 34 be imbedded by according to CVD method film forming dielectric film in the hole portion 38 between semiconductor substrate 31 and the 2nd semiconductor layer 34.Thus, can prevent that the film of the 2nd semiconductor layer 34 from subtracting, and imbed hole portion 39 between semiconductor substrate 31 and the 2nd semiconductor layer 34 with the material beyond the oxide-film.Therefore, can seek to be configured in the thick filmization of buried insulating layer 39 of the rear side of the 2nd semiconductor layer 34, can reduce permittivity simultaneously and reduce the parasitic capacitance of the rear side of the 2nd semiconductor layer 34.
In addition, as the material of buried insulating layer 39, for example except silicon oxide layer, can also use FSG (fluorosilicate glass) film or silicon nitride film etc.In addition, as buried insulating layer 10, except SOG (Spin On Glass) film, also can use organic lowk film or these perforated membranes of psg film, bpsg film, PAE (polyaryleneether) mesentery, HSQ (hydrogen silsesquioxane) mesentery, MSQ (methylsilesquioxane) mesentery, PCB mesentery, CF mesentery, SiOC mesentery, SiOF mesentery etc.
Then, as shown in Figure 9, form, expose the sidewall of the 2nd semiconductor layer 34 by using photoetching technique and etching technique that the buried insulating layer 39 of the 2nd semiconductor layer 34 and sidewall thereof is carried out pattern.At this, under the situation of the sidewall that exposes the 2nd semiconductor layer 34, also can carry out pattern to semiconductor layer 34 and form, for example also can pattern form the shape of fin shape, pectination, square shape or mesh-shape etc. according to mode with the part that has comprised the 2nd semiconductor layer 34.
Then, as shown in figure 10, by carrying out forming the side of the 2nd semiconductor layer 34 in region R 21 and the one-tenth piece region R 22 and the thermal oxidation on surface at SOI, the side that forms the 2nd semiconductor layer 34 of region R 21 at SOI forms gate insulating film 40a, forms gate insulating film 40b in the side of the 2nd semiconductor layer 34 that becomes piece region R 22 simultaneously.And formed on the 2nd semiconductor layer 34 of gate insulating film 40a, 40b and formed polysilicon layer by methods such as CVD.And, form by using photoetching technique and etching technique that polysilicon layer is carried out pattern, formation is configured in the gate electrode 41a of side that SOI forms the 2nd semiconductor layer 34 of region R 21, forms the gate electrode 41b on the surface of the 2nd semiconductor layer 34 that is configured in into piece region R 2 simultaneously.
And, gate electrode 41a, 41b as mask, are infused in the 2nd semiconductor layer 34 by the foreign ion with As, P, B etc., on the 2nd semiconductor layer 34, form the source/drop ply of the side that is configured in gate electrode 41a, 41b respectively.
Thus, need not to use the SOI substrate and can form soi structure in the zone of the part of semiconductor substrate 31, simultaneously can be at the sidewall configuration channel region of the 2nd semiconductor layer 34.The element that therefore can suppress the increase of chip size and will have various functions of holding good characteristic is formed on the same chip.
In addition, in the above-described embodiment, method by buried insulating layer 39 only stacked one deck the 2nd semiconductor layer 34 on the semiconductor substrate 31 of SOI formation region R 21 has been described, but also can by insulating barrier a plurality of semiconductor layers be layered on the semiconductor substrate 31 of SOI formation region R 21 respectively.
Claims (7)
1, a kind of semiconductor device is characterized in that, possesses:
Semiconductor substrate, it has formed insulating barrier on the zone of a part;
Semiconductor layer, it is configured on the above-mentioned insulating barrier and with epitaxial growth and comes film forming;
The 1st gate electrode, it to be to cross over the mode of the part of above-mentioned semiconductor layer across the 1st gate insulating film ground, extend to the side walls of above-mentioned semiconductor layer and form;
The 1st source/drop ply, it is formed on the above-mentioned semiconductor layer and is configured in the side of above-mentioned the 1st gate electrode respectively;
The 2nd gate electrode, it is formed on the above-mentioned semiconductor substrate across the 2nd gate insulating film; With
The 2nd source/drop ply, it is formed on the semiconductor layer on the above-mentioned semiconductor substrate, and is configured in the side of above-mentioned the 2nd gate electrode respectively;
The side of above-mentioned semiconductor layer of holding above-mentioned the 1st gate electrode is by { 110} face or { the 100} face constitutes, and the surface of above-mentioned semiconductor substrate of holding above-mentioned the 2nd gate electrode is by { the 100} face constitutes.
2, a kind of semiconductor device is characterized in that, possesses:
Semiconductor substrate, it has formed insulating barrier on the zone of a part;
The the 1st and the 2nd semiconductor layer, it is layered on the above-mentioned insulating barrier and with epitaxial growth and comes film forming;
The P-channel field-effect transistor (PEFT) transistor npn npn, it has disposed channel region on the sidewall of above-mentioned the 1st semiconductor layer;
N channel field-effect transistor npn npn, it has disposed channel region on the sidewall of above-mentioned the 2nd semiconductor layer;
P raceway groove or N channel field-effect transistor npn npn, its be formed on the above-mentioned semiconductor substrate and in the surface configuration of above-mentioned semiconductor substrate channel region,
The above-mentioned the 1st and the sidewall of the 2nd semiconductor layer be { 100} face or { 110} face orientation.
3, semiconductor device according to claim 2 is characterized in that, possesses:
Gate electrode, its be configured in the above-mentioned the 1st and the sidewall of the 2nd semiconductor layer on, and jointly be formed on above-mentioned P-channel field-effect transistor (PEFT) transistor npn npn and the above-mentioned N channel field-effect transistor npn npn;
The 1st source/drop ply, its mode with the both sides that are configured in above-mentioned gate electrode is formed on above-mentioned the 1st semiconductor layer;
The 2nd source/drop ply, its mode with the both sides that are configured in above-mentioned gate electrode is formed on above-mentioned the 2nd semiconductor layer.
4, semiconductor device according to claim 2 is characterized in that,
The thickness of above-mentioned the 1st semiconductor layer is to be in 2～3 times the scope of thickness of above-mentioned the 2nd semiconductor layer.
5, according to the semiconductor device described in any of claim 1～4, it is characterized in that,
On above-mentioned semiconductor substrate, form protection diode, bipolar transistor, analog element or high voltage drive FET, on above-mentioned semiconductor layer, form digital element or low voltage drive FET.
6, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On the part on the surface of semiconductor substrate, form the operation of coming the 1st semiconductor layer of film forming with epitaxial growth;
The 2nd semiconductor layer that rate of etch is also littler than above-mentioned the 1st semiconductor layer is carried out to the operation of film with epitaxial growth on above-mentioned the 1st semiconductor layer and semiconductor substrate;
Constitute than the also little material of above-mentioned the 1st semiconductor layer by rate of etch, and be formed on the operation of the supporter of above-mentioned the 2nd semiconductor layer of above-mentioned semiconductor substrate upper support;
The operation of exposed division of the part of above-mentioned the 1st semiconductor layer is exposed in formation;
By the 1st semiconductor layer selectively being carried out etching, between above-mentioned semiconductor substrate and above-mentioned the 2nd semiconductor layer, form the operation of the hole portion of having removed above-mentioned the 1st semiconductor layer by means of above-mentioned exposed division;
Be formed on the operation of having imbedded buried insulating layer in the portion of above-mentioned hole;
The operation of exposing the sidewall of above-mentioned the 2nd semiconductor layer;
Formation comprises the 1st transistorized operation of the 1st gate electrode and the 1st source/drop ply, above-mentioned the 1st gate electrode is to cross over the mode of the part of above-mentioned the 2nd semiconductor layer across the 1st gate insulating film ground, extend to the side walls of above-mentioned the 2nd semiconductor layer and form, above-mentioned the 1st source/drop ply is formed on above-mentioned the 2nd semiconductor layer, and is configured in the side of above-mentioned the 1st gate electrode respectively; With
Formation comprises the 2nd transistorized operation of the 2nd gate electrode and the 2nd source/drop ply, above-mentioned the 2nd gate electrode is formed on the above-mentioned semiconductor substrate across the 2nd gate insulating film, above-mentioned the 2nd source/drop ply is formed on above-mentioned the 1st semiconductor layer, and is configured in the side of above-mentioned the 2nd gate electrode respectively;
And, will hold above-mentioned the 1st gate electrode above-mentioned semiconductor layer the 110} face or the 100} face is as the side of this semiconductor layer, will hold above-mentioned the 2nd gate electrode above-mentioned semiconductor substrate { the 100} face is as the surface of this semiconductor substrate.
7, the manufacture method of semiconductor device according to claim 6 is characterized in that,
Above-mentioned supporter is an element separating insulation film.
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| JP2005063580A JP2006253181A (en) | 2005-03-08 | 2005-03-08 | Semiconductor device and its manufacturing method |
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| US (1) | US7368340B2 (en) |
| JP (1) | JP2006253181A (en) |
| KR (1) | KR100713682B1 (en) |
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| US9153645B2 (en) | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US7777250B2 (en) | 2006-03-24 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| EP2062290B1 (en) | 2006-09-07 | 2019-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US7799592B2 (en) | 2006-09-27 | 2010-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-gate field-effect transistors formed by aspect ratio trapping |
| WO2008039534A2 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures |
| WO2008051503A2 (en) | 2006-10-19 | 2008-05-02 | Amberwave Systems Corporation | Light-emitter-based devices with lattice-mismatched semiconductor structures |
| US8017505B2 (en) * | 2006-11-30 | 2011-09-13 | Seiko Epson Corporation | Method for manufacturing a semiconductor device |
| JP4306724B2 (en) | 2006-12-19 | 2009-08-05 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US8304805B2 (en) | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
| US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
| US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
| KR100869235B1 (en) * | 2007-05-25 | 2008-11-18 | 삼성전자주식회사 | Method of manufacturing semiconductor diode and method of manufacturing pram using the same |
| US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| KR101093588B1 (en) | 2007-09-07 | 2011-12-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Multi-junction solar cells |
| US20090256207A1 (en) * | 2008-04-14 | 2009-10-15 | International Business Machines Corporation | Finfet devices from bulk semiconductor and methods for manufacturing the same |
| US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
| US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
| EP2528087B1 (en) | 2008-09-19 | 2016-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
| US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
| WO2010114956A1 (en) | 2009-04-02 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| KR101872957B1 (en) | 2012-01-02 | 2018-07-02 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| JP6584977B2 (en) * | 2016-02-24 | 2019-10-02 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
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| JPH05206422A (en) * | 1992-01-28 | 1993-08-13 | Canon Inc | Semiconductor device and its manufacture |
| JP3078720B2 (en) * | 1994-11-02 | 2000-08-21 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JPH10261799A (en) | 1997-03-18 | 1998-09-29 | Sony Corp | Manufacture of semiconductor substrate and manufacture of semiconductor device |
| JP2000124092A (en) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby |
| JP2001320052A (en) | 2000-05-02 | 2001-11-16 | Fujitsu Ltd | Semiconductor device and semiconductor integrated circuit |
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| KR100458288B1 (en) * | 2002-01-30 | 2004-11-26 | 한국과학기술원 | Double-Gate FinFET |
| US7180134B2 (en) * | 2004-01-30 | 2007-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and structures for planar and multiple-gate transistors formed on SOI |
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| TW200633125A (en) | 2006-09-16 |
| KR100713682B1 (en) | 2007-05-02 |
| US7368340B2 (en) | 2008-05-06 |
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| JP2006253181A (en) | 2006-09-21 |
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