CN100507586C - Method for evaluating lifespan of integrated circuit chip products - Google Patents
Method for evaluating lifespan of integrated circuit chip products Download PDFInfo
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- CN100507586C CN100507586C CNB2006101132893A CN200610113289A CN100507586C CN 100507586 C CN100507586 C CN 100507586C CN B2006101132893 A CNB2006101132893 A CN B2006101132893A CN 200610113289 A CN200610113289 A CN 200610113289A CN 100507586 C CN100507586 C CN 100507586C
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- 238000000034 method Methods 0.000 title claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 10
- 235000010894 Artemisia argyi Nutrition 0.000 claims description 9
- 244000030166 artemisia Species 0.000 claims description 9
- 230000001133 acceleration Effects 0.000 claims description 7
- 238000005259 measurement Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 3
- 238000011156 evaluation Methods 0.000 abstract 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 235000001892 vitamin D2 Nutrition 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
This invention provides one integration circuit chip product life evaluation method, which comprises the following steps: pre-evaluating positioning chip local area with highest temperature through chip dynamic work mode; processing package removing at the area with highest local temperature; at the package removing area, using infrared remote detecting device to measure bare surface temperature in the constant and high temperature; using the measured chip dynamic work mode bare surface temperature as Abney effect Tuse and Tstress evaluation chip life.
Description
Technical field
The present invention relates to a kind of IC appraisal procedure in (Integrated Circuit, integrated circuit) chip product life-span, particularly a kind of appraisal procedure that adopts the IC chip product life-span of high temperature test.
Background technology
At present at the IC chip field, international employing standard is JEDEC/FSA (JointElectronic Device Engineering Council, Joint Electronic Device Engineering Council/FablessSemiconductor Association, semiconductor association of no factory) the IC HTOL of JP001.01 (HighTemperature Operating Life Test hot operation life-span) test adopts Chinese mugwort grace Nice pattern (Arrhenius mode) as hot speedup factor (AFT, Acceleration factor due toTemperature):
AFT＝exp(EA/k[(1/T
use)-(1/T
stress)])
T wherein
UseAnd T
StressBe junction temperature.
Usually all be as T in actual test process with 125 ℃ of temperature in the baking box
StressAnd it is actual under the accelerated deterioration hot environment, the junction temperature of inside will be higher than the surface temperature of IC encapsulation during the IC dynamic duty, and the surface temperature of IC encapsulation is higher than 125 ℃ of the interior temperature of baking box again, and the concrete temperature difference is relevant with package cooling design (Thermal Design) with the IC design.T
UseBe the average junction temperature in the phase life of product.T
UseTypical value be: 55 ℃ (individual/product for civilian use), 70 ℃ (commercial use product), 85 ℃ (industrial use product).Equally, actual the junction temperature of inside will be higher than IC package surface temperature during the IC dynamic duty under the common temperature limit environment of IC, and IC package surface temperature is higher than the temperature of environment for use again, and the concrete temperature difference is relevant with the package cooling design with the IC design.
T as from the foregoing
StressAdopt 125 ℃ of life-spans that will cause calculating less than normal, if actual T
Stress125 ℃ of temperature that are higher than in the baking box are too much, such as more than 10 ℃, also may cause agine mechaism and acceleration model inconsistent, thereby release the wrong life-span.And T
UseAdopt above representative value, also will cause calculating the life-span out of true very that obtains.
In addition, IC is under dynamic operation mode, and internal temperature branch neither be uniform, and the place that local temperature is high is the easiest aging place.
Summary of the invention
The technical problem to be solved in the present invention is, overcome the deficiency of appraisal procedure in the IC chip product life-span of available technology adopting high temperature test, propose a kind ofly to assess the method for life of product test, to reach the purpose of estimating the IC life-span comparatively accurately by accurate measurement IC nude film duty surface temperature.
In order to address the above problem, the invention provides a kind of appraisal procedure of lifespan of integrated circuit chip products, comprise following steps:
Step 1:, estimate the highest zone of positioning chip local temperature by carrying out the power consumption assessment under the chip dynamic operation mode;
Step 2: go encapsulation process in the highest zone of estimating out of chip local temperature;
Step 3: go to the zone that encapsulates at chip, measure under the normal temperature respectively and the die surfaces temperature under the chip dynamic operation mode under the hot environment with the infrared remote sensing instrument;
Step 4: the die surfaces temperature under the chip dynamic operation mode of usefulness actual measurement is as the T in the pattern of Chinese mugwort grace Nice
UseAnd T
StressThe life-span of estimation chip;
Described normal temperature is the environment for use temperature of described chip.
In addition, in above-mentioned steps 2, chip is removed the diameter of the slightly larger in diameter of encapsulation process in infrared detection head.
At normal temperature described in the above-mentioned steps 3 is 55 ℃ or 70 ℃ or 85 ℃; Described high temperature is 125 ℃.
In addition, when the die surfaces temperature under the chip dynamic operation mode in baking box exceeds Chinese mugwort acceleration model efficient temperature interval, grace Nice (promptly not in 125 ℃～135 ℃ scopes), oven temperature is reduced, make the die surfaces temperature of chip remain on Chinese mugwort acceleration model efficient temperature interval, grace Nice (125 ℃～135 ℃).
The present invention surveys die surfaces temperature under the IC dynamic operation mode by adopting infrared remote sensing technology, and with the die surfaces temperature of actual measurement as the T in grace Nice pattern that ends
UseAnd T
Stress, can estimate life-span of IC comparatively accurately.
Description of drawings
Fig. 1 surveys the synoptic diagram of the die surfaces temperature under the IC dynamic operation mode for the present invention adopts infrared remote sensing technology.
Embodiment
The present invention will be described in detail below in conjunction with drawings and Examples.
Fig. 1 surveys the synoptic diagram of the die surfaces temperature under the IC dynamic operation mode for the present invention adopts infrared remote sensing technology.
As shown in Figure 1, there is the highest high-temperature region of local temperature in the IC chip under dynamic operation mode, handles by go encapsulation (decap) in this high-temperature region, and uses infrared detecting set, can measure the nude film temperature under this high-temperature region dynamic operation mode.
The appraisal procedure of lifespan of integrated circuit chip products of the present invention comprises following steps:
Step 1:, estimate the highest zone of IC local temperature, location by carrying out the power consumption assessment under the IC dynamic operation mode;
Wherein, the power consumption assessment under the IC dynamic operation mode can be realized by IC design software instrument analog simulation;
Step 2: go encapsulation process in the highest zone of estimating out of IC local temperature; Wherein, for the chip of plastic cement encapsulation, can adopt the high concentration red fuming nitric acid (RFNA) of being fuming to go encapsulation process;
Step 3: go to the zone that encapsulates at IC, measure under the normal temperature respectively and the die surfaces temperature under the IC dynamic operation mode under the hot environment with the infrared remote sensing instrument;
When using infrared remote sensing instrument thermometric, temperature-sensing probe is brought into focus, be fixed on and treat directly over the point for measuring temperature; This moment, probe can be measured environment temperature of living in simultaneously, and can carry out temperature compensation by using special software.
Step 4: the die surfaces temperature under the IC dynamic operation mode of usefulness actual measurement is as the T in the pattern of Chinese mugwort grace Nice
UseAnd T
StressThe life-span of estimation IC.
In addition, the power consumption assessment that carries out in the above-mentioned steps 1 under the IC dynamic operation mode can also detect and realizes by the IC nude film after going to encapsulate being carried out the liquid crystal focus.
In above-mentioned steps 2, IC is carried out the diameter of the slightly larger in diameter of Decap in infrared detection head.
In above-mentioned steps 3, described " normal temperature " is indoor temperature, or the normal environment for use temperature of chip product (Temperature at normal use conditions); The normal environment for use temperature of chip product is exactly after this chip is submitted to the user, the environment temperature in normal use; This temperature is pre-determined by the research and development/production mechanism of chip product, and typical value is: 55 ℃ (individual/product for civilian use), 70 ℃ (commercial use product), 85 ℃ (industrial use product).
Described " high temperature " is the accelerated deterioration temperature in the baking box, and this temperature is higher than the normal environment for use temperature of chip product, is generally 125 ℃.
In addition, the die surfaces temperature under IC dynamic operation mode in baking box is too high, when surpassing 135 ℃, oven temperature suitably can be reduced, and the die surfaces temperature of IC is remained between 125 ℃～135 ℃, makes Chinese mugwort grace Nice acceleration model effective.
Claims (4)
1, a kind of appraisal procedure of lifespan of integrated circuit chip products, this method comprises following steps:
Step 1:, estimate the highest zone of positioning chip local temperature by carrying out the power consumption assessment under the chip dynamic operation mode;
Step 2: go encapsulation process in the highest zone of estimating out of chip local temperature;
Step 3: go to the zone that encapsulates at chip, measure under the normal temperature respectively and the die surfaces temperature under the chip dynamic operation mode under the hot environment with the infrared remote sensing instrument;
Step 4: the die surfaces temperature under the chip dynamic operation mode of usefulness actual measurement is as the T in the pattern of Chinese mugwort grace Nice
UseAnd T
StressThe life-span of estimation chip;
Described normal temperature is the environment for use temperature of described chip.
2, the appraisal procedure of lifespan of integrated circuit chip products as claimed in claim 1 is characterized in that, in described step 2, chip is removed the diameter of the slightly larger in diameter of encapsulation process in infrared detection head.
3, the appraisal procedure of lifespan of integrated circuit chip products as claimed in claim 1 is characterized in that, described normal temperature is 55 ℃ or 70 ℃ or 85 ℃; Described high temperature is 125 ℃.
4, the appraisal procedure of lifespan of integrated circuit chip products as claimed in claim 1, it is characterized in that, when the die surfaces temperature under the chip dynamic operation mode in baking box exceeds acceleration model efficient temperature interval, Chinese mugwort grace Nice, oven temperature is reduced, make the die surfaces temperature of chip remain on Chinese mugwort acceleration model efficient temperature interval, grace Nice.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101132893A CN100507586C (en) | 2006-09-21 | 2006-09-21 | Method for evaluating lifespan of integrated circuit chip products |
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|---|---|---|---|
| CNB2006101132893A CN100507586C (en) | 2006-09-21 | 2006-09-21 | Method for evaluating lifespan of integrated circuit chip products |
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| CN100507586C true CN100507586C (en) | 2009-07-01 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100588979C (en) * | 2007-08-24 | 2010-02-10 | 北京中星微电子有限公司 | Testing method for integrated circuit high temperature dynamic aging and testing device thereof |
| CN101915626B (en) * | 2010-07-30 | 2014-10-22 | 上海华虹宏力半导体制造有限公司 | Method for detecting temperature of wafer in real time and method for measuring temperature characteristic of device |
| CN102147822A (en) * | 2010-12-23 | 2011-08-10 | 上海高性能集成电路设计中心 | Large-scale digital integrated circuit power dissipation dynamic assessment device based on power dissipation bank |
| CN103185855B (en) * | 2011-12-27 | 2016-02-10 | 英业达股份有限公司 | Testing equipment |
| WO2023097580A1 (en) * | 2021-12-01 | 2023-06-08 | 中国科学院深圳先进技术研究院 | Method and apparatus for predicting lifetime of integrated circuit, and computer-readable storage medium |
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2006
- 2006-09-21 CN CNB2006101132893A patent/CN100507586C/en not_active Expired - Fee Related
Non-Patent Citations (4)
| Title |
|---|
| Fatigue life prediction of flip-chips in terms of nonlinearbehavior of solder and underfill. Zhengfang，Qian，et，al.1999 Electronic Components and Technology Conference. 1999 |
| Fatigue life prediction of flip-chips in terms of nonlinearbehavior of solder and underfill. Zhengfang，Qian，et，al.1999 Electronic Components and Technology Conference. 1999 * |
| Physical Interpretation of the Tantalum Chip CapacitorLife-Test Results. BUGENE LOH.IEEETRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY,Vol.3 No.4. 1980 |
| Physical Interpretation of the Tantalum Chip CapacitorLife-Test Results. BUGENE LOH.IEEETRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY,Vol.3 No.4. 1980 * |
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