CN100501987C - 芯片向下的球栅阵列封装及其制造方法 - Google Patents

芯片向下的球栅阵列封装及其制造方法 Download PDF

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Publication number
CN100501987C
CN100501987C CNB2005101089244A CN200510108924A CN100501987C CN 100501987 C CN100501987 C CN 100501987C CN B2005101089244 A CNB2005101089244 A CN B2005101089244A CN 200510108924 A CN200510108924 A CN 200510108924A CN 100501987 C CN100501987 C CN 100501987C
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substrate
chip
bonding wire
radiator
hole
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CN1773698A (zh
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雷泽-厄·拉曼·卡恩
萨姆·齐昆·赵
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Avago Technologies International Sales Pte Ltd
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Zyray Wireless Inc
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Abstract

本发明公开了一种空腔或芯片向下的球栅阵列封装，包括一内插式基板连接至所述芯片。所述内插式基板可缩减电路板至半导体或集成电路芯片顶层的电源和接地接点的线路长度。此外，所述内插式基板的采用，还消除了电源和接地接点需设置在IC芯片外围的需求。电源和接地接点可设置在IC芯片顶部金属层的内部区域，在此区域，所述电源和接地接点可通过导电突起或焊线连接至所述内插式基板。

Description

芯片向下的球栅阵列封装及其制造方法
技术领域
本发明涉及集成电路(IC)封装，具体地涉及一种空腔向下阵列集成电路封装。
背景技术
集成电路设备采用封装技术，如芯片向下阵列封装。IC封装为IC提供环境保护，允许IC装配于电路板，允许IC与其他设备进行信号通信，以及其他功能等。
现在急需要的是一种IC封装内高效率的电源输送结构，能缩减IC芯片顶部金属的线路长度，缩减IC芯片上焊线到电源焊点的长度，缩减印刷线路板(PWB)电源/接地层到封装之间的线路长度。
发明内容
本发明的一个实施例提供一个除IC封装内现有第一基板之外的第二基板，用于连接一IC芯片至一印刷电路板(PCB)/印刷线路板(PWB)。所述第二基板通过相应的互连阵列，如锡球、管脚等，与芯片和PCB/PWB连接。
本发明的另一个实施例中提供一种球栅阵列(BGA)封装。所述球栅阵列封装包括一个散热器、第一基板和第二基板以及一个集成电路芯片。所述第一基板包括一个沿所述基板延伸的通孔，所述散热器的一部分可通过所述通孔接触到。所述集成电路芯片附装在所述散热器上，并贯穿所述基板的通孔。所述第二基板具有第一表面，通过互连网络与位于IC芯片中部的结合焊点连接。所述第二基板的第二表面具有一接触焊点阵列，当所述封装安装在电路板上时能够与所述电路板连接。
一个示例中，所述球栅阵列封装还包括一焊线排列，连接IC芯片、第一基板、第二基板和散热器中的至少一部件与IC芯片、第一基板、第二基板和散热器中的至少另一部件。
本发明的另一个实施例提供一种制造球栅阵列封装的方法。一集成电路芯片与第一基板上通孔内的散热器连接，所述基板的通孔沿所述基板延伸贯通，所述散热器的一部分可通过所述通孔接触到。第二基板通过互连网络与位于IC芯片中部的焊点连接。
本发明再一实施例提供一种提供一种内插式基板，实现空腔向下阵列(如BGA、PGA等)封装内电源输送给半导体芯片。
本发明各种实施例中，所述内插式基板可以是平面印刷电路板、载带基板或导电板(如铜板)，与所述半导体芯片电连接。
本发明各种实施例中，所述内插式基板与半导体的具有金属突起或粘合剂的活性表面相贴合。
本发明一实施例中，一成型化合物覆盖所述芯片，并部分覆盖所述内插式基板，以达环境保护的目的。所述内插式基板的底面全部或部分地暴露在外，以与安装封装的PCB/PWB电连接。
本发明各种实施例中，内插式基板下表面上的一个或多个金属接点暴露在外。
本发明各种实施例中，所述内插式基板与PCB/PWB之间的电连接方式可为一个或多个锡球、导电柱、管脚或其他类似物。
本发明一实施例中，所述内插式基板底面露在外面的金属接点或焊点亦可通过锡膏直接焊接至PCB/PWB上相对应的接点位置。
根据本发明的一个方面，提供一种球栅阵列封装，包括：
散热器；
第一基板，具有沿所述第一基板贯通的通孔，所述第一基板连接至所述散热器，所述散热器的一部分可通过所述通孔被接触；
集成电路(IC)芯片，设置在所述第一基板的通孔中并与所述散热器连接；
第二基板，具有第一表面和第二表面，所述第一表面附着在所述IC芯片中部，所述第二表面具有一接触焊点阵列，用于与安装所述球栅阵列封装的电路板连接；
焊线排列，包括连接所述IC芯片至所述散热器的焊线、连接所述IC芯片至所述第一基板的焊线、连接所述IC芯片至所述第二基板的焊线；
封装材料，至少部分覆盖所述散热器、第一基板、第二基板和IC芯片；
其中，所述第二基板具有一中心通孔且沿所述中心通孔内侧形成有第一台阶，所述第二基板沿其外围具有第二台阶，所述连接IC芯片至第二基板的焊线包括连接所述IC芯片中部的接点至所述第二基板的第一台阶的焊线和连接所述IC芯片外缘的接点至所述第二基板的第二台阶的焊线。
优选地，所述散热器包括有一空腔，所述IC芯片附着在其内，所述空腔的开口比所述第一基板的通孔的直径小。
优选地，所述散热器是金属板。
优选地，所述散热器由导电材料制成。
优选地，所述IC芯片通过粘合材料或环氧树脂与所述散热器粘接。
优选地，所述第一基板可为载带基板，有机物基板，陶瓷基板，玻璃基板，聚酰亚胺基板中的任一种。
优选地，所述第一基板为一多层基板。
优选地，所述球栅阵列封装进一步包括一锡球阵列，连接至所述第一基板的一个表面以将所述封装安装在印刷线路板上。
优选地，所述球栅阵列封装进一步包括一与所述接触焊点阵列连接的锡球阵列，以将所述封装与所述线路板连接。
优选地，所述球栅阵列进一步包括有用于粘接所述第二基板与所述印刷线路板的锡膏。
优选地，所述第二基板包括一设置在硬质或弹性绝缘基板上的印刷电路。
优选地，所述绝缘基板可为双马来酰亚胺三嗪(BT)树脂基板、树脂基板、聚酰亚胺载带基板、载带基板、4型阻燃(FR4)层压基板、陶瓷基板或玻璃基板中的任一种。
优选地，所述第二基板为一多层基板。
优选地，所述第二基板的第一表面与所述IC芯片之间设有绝缘材料。
优选地，所述第二基板连接至所述IC芯片的中部，从而电源经由所述第二基板输送给所述IC芯片的中部或从所述IC芯片中部输出。
优选地，所述第二基板连接至所述IC芯片，从而电源经由所述第二基板的交互网络输送给所述IC芯片中部的设备。
优选地，所述球栅阵列封装进一步包括：位于所述IC芯片外围区域的阵列输入/输出(I/O)设备。
优选地，所述焊线排列包括：
一连接所述第二基板至所述散热器的焊线；
至少一连接所述第二基板至所述第一基板的焊线。
优选地，所述第二基板为一金属基板。
优选地，所述金属基板具有一位于中心的通孔。
优选地，所述球栅阵列封装进一步包括：
一锡接点阵列，附着在所述第一基板的一个表面上，用于将所述封装安装在印刷线路板上；
一锡球阵列，连接至所述接触接点阵列，用与连接所述封装与所述印刷线路板。
优选地，所述球栅阵列封装进一步包括：
一锡接点阵列，附着在所述第一基板的一个表面上，用于将所述封装安装在印刷线路板上；
与所述接触接点阵列连接的锡膏，用与连接所述封装与所述印刷线路板。
优选地，所述金属基板包括一铜板。
优选地，所述金属基板的外围部分厚度比中心部分厚度小。
优选地，所述金属基板沿其外围具有一台阶；
所述焊线排列包括：
一连接所述IC芯片至所述第一基板的焊线；
一连接所述IC芯片至所述金属基板台阶的焊线；
一连接所述金属基板台阶至所述散热器的焊线。
优选地，所述金属基板沿其外围具有一台阶；
所述焊线排列包括：
一连接所述IC芯片至所述第一基板的焊线；
一连接所述IC芯片至所述散热器的焊线；
一连接所述IC芯片至所述第二基板的台阶的焊线。
优选地，所述金属基板具有一中心通孔，第一台阶靠近所述中心通孔，第二台阶设置在所述通孔外围；
所述焊线排列包括：
一连接所述IC芯片至所述散热器的焊线；
一连接所述IC芯片至所述第一基板的焊线；
一连接所述IC芯片至所述金属基板第二台阶的焊线；
一连接所述IC芯片至位于所述金属基板中心通孔第一侧的第一台阶的焊线；
一连接所述IC芯片至位于所述金属基板中心通孔上与所述第一侧相对的第二侧的第一台阶的焊线。
根据本发明的一个方面，提供一种球栅阵列封装的制造方法，包括：
a、在第一基板的通孔中，连接一IC芯片至一散热器，所述第一基板的通孔沿所述第一基板延伸贯通，所述散热器的一部分通过所述通孔与所述IC芯片接触；
b、将第二基板附着在所述IC芯片中部；
c、采用焊线排列连接所述IC芯片至所述散热器、连接所述IC芯片至所述第一基板、连接所述IC芯片至所述第二基板；
d、采用封装材料至少部分地覆盖所述散热器、第一基板、第二基板和IC芯片；
其中，所述步骤c进一步包括：
在所述第二基板上形成一中心通孔；
沿所述中心通孔的内侧形成第一台阶；
沿所述第二基板的外围形成第二台阶；
使用焊线连接所述IC芯片中部的接点至所述第二基板的第一台阶；
使用焊线连接所述IC芯片外缘的接点至所述第二基板的第二台阶。
优选地，所述步骤a包括：在所述散热器中形成一空腔以容置所述IC芯片，所述空腔的开口比所述第一基板的通孔的直径小。
优选地，所述步骤a包括：采用金属板或导热材料作为所述散热器。
优选地，所述步骤a包括：通过粘合材料或环氧树脂连接所述IC芯片至所述散热器。
优选地，所述步骤a包括：采用载带基板、有机物基板、陶瓷基板、玻璃基板或聚酰亚胺载带基板中的一种作为第一基板。
优选地，所述步骤a包括：采用一多层基板作为第一基板。
优选地，所述方法进一步包括：
e、将所述第一和第二基板安装在一印刷线路板上。
优选地，所述步骤e包括：通过一锡球阵列安装所述第一和第二基板至所述印刷线路板。
优选地，所述步骤e包括：
采用一锡球阵列安装所述第一基板至所述印刷线路板；
采用锡膏安装所述第二基板至所述印刷线路板。
优选地，所述步骤b包括：在一硬质或弹性绝缘基板上设置印刷电路作为第二基板。
优选地，所述方法进一步包括：采用双马来酰亚胺三嗪(BT)树脂基板、树脂基板、聚酰亚胺载带基板、载带基板、4型阻燃(FR4)层压基板、陶瓷基板或玻璃基板中的任一种作为绝缘基板。
优选地，步骤b包括：采用一多层基板作为第二基板。
优选地，步骤b包括：通过绝缘材料将所述第二基板附着在所述IC芯片中部。
优选地，步骤b中，连接所述第二基板至IC芯片中部，从而允许电源经由所述第二基板输入所述IC芯片中部或从所述IC芯片中部输出。
优选地，步骤b中，连接所述第二基板至所述IC芯片，从而允许电源经由所述第二基板在所述IC芯片中部的设备间传输。
优选地，步骤b中，所述第二基板连接至所述IC芯片，所述IC芯片外围区域仅包括I/O设备。
优选地，所述步骤c进一步包括：
沿所述第二基板的外围形成台阶；
使用焊线连接所述IC芯片至所述第二基板外围的台阶。
优选地，所述方法进一步包括：
使用焊线连接所述第二基板至所述散热器；
使用焊线连接所述第二基板至所述第一基板；
优选地，所述步骤b包括：采用一金属基板作为第二基板。
优选地，所述步骤b包括：在所述金属基板上形成一中心通孔。
优选地，所述步骤b包括：采用一铜板作为所述金属基板。
优选地，所述步骤b包括：将所述金属基板成形为中部的厚度大于外围的厚度。
优选地，所述步骤b包括：
沿所述金属基板外围形成一台阶；
使用一焊线连接所述IC芯片至所述第一基板；
使用一焊线连接所述IC芯片至所述金属基板的台阶；
使用一焊线连接所述金属基板的台阶至所述散热器。
优选地，所述步骤b包括：
沿所述金属基板外围形成一台阶；
使用一焊线连接所述IC芯片至所述散热器；
使用一焊线连接所述IC芯片至所述第一基板；
使用一焊线连接所述IC芯片至所述金属基板的台阶。
优选地，所述步骤b包括：
在所述金属基板上形成一中心通孔；
沿所述金属基板外围形成第一台阶；
沿靠近所述金属基板中心通孔的位置形成第二台阶；
使用一焊线连接所述IC芯片至所述散热器；
使用一焊线连接所述IC芯片至所述第一基板；
使用一焊线连接所述IC芯片至所述金属基板的第二台阶；
使用一焊线连接所述IC芯片至位于所述金属基板中心通孔第一侧的第一台阶；
使用一焊线连接所述IC芯片至位于所述金属基板中心通孔第一侧相对的第二侧的第一台阶。
本发明的实施例提供了一种包括有连接至IC芯片的内插式基板结构的空腔向下或芯片向下球栅阵列封装。该内插式基板可缩减从电路板至IC芯片顶层电源和接地接点的线路长度。内插式基板的采用，还消除了电源和接地接点需设置于IC芯片外围的需求。电源和接地接点可设置在IC芯片顶部金属层的内部区域，在此区域，所述电源和接地接点可通过导电突起(如锡、金等)和/或焊线连接至所述内插式基板。
此种配置方式为IC芯片顶部金属层提供了更大的IO信号路由空间，从而为减小芯片尺寸提供可能。
将电源接点设置在芯片内部区域，可缩减芯片内电源输送线路长度，从而降低芯片内的IR压降。
内插式基板缩短了印刷电路板(PCB)或印刷线路板(PWB)至芯片上接点的电源输送线路长度，为芯片和内插式基板上的电源和地网线路路由提供了灵活性。
在焊线空腔向下区域阵列封装中集成一内插式基板的方法可降低IR压降，可参看如下详述。内插式基板用于分配和输送电源至芯片顶部金属层的电源和接地接点。内插式基板还缩减了芯片、封装与PWB之间的互连线路长度。内插式基板还可用于封装内IO信号互连。
本发明中，互连设备、互联网络、互连阵列、互连元件阵列、锡球阵列等的可交换使用，为封装内各种设备(如电子元器件)间的信号及电源传输提供了接口。
附图说明
下面将结合附图及相应的描述对本发明的目的和特征作进一步说明，附图中：
图1是一种芯片向上球栅阵列封装的示意图；
图2A是一种空腔向下载带球栅阵列(TBGA)封装的示意图；
图2B是一种带有有机或陶瓷基板的空腔向下球栅阵列封装的示意图；
图2C是一种区域卷带自动接合(ATBA)封装的示意图；
图3是一种带有用于TBGA封装内电源/接地层的插入式散热器的TBGA封装的示意图；
图4是一种带有加强了热电性的增强板/内插板的芯片向上TBGA的示意图；
图5是一种带有增强板/转接板和热/电连接器的芯片向上TBGA的示意图；
图6A是根据本发明一个实施例包括有具有连接IC芯片的锡球突起的内插式基板的TBGA实现的示意图；
图6B和图6C分别是图6A中所示的内插式基板的俯视图和仰视图。
图7是图6A中所示TBGA实现的载带基板和内插式基板的支脚高度的示意图；
图8是根据本发明一个实施例的增强型BGA(EBGA)封装的示意图；
图9A和9B分别是根据本发明一个实施例的包括有通过突起和焊线与芯片互连的内插式基板的球栅阵列封装的截面图和仰视图；
图10是根据本发明一个实施例的具有用于内插式基板与封装基板和封装散热器交互连接的焊线的球栅阵列封装的示意图；
图11是根据本发明一个实施例的在内插式基板底面上具有焊线手指的球栅阵列封装的示意图；
图12是根据本发明一个实施例的具有通过接点栅格阵列(LGA)互连并表面贴装至一印刷线路板的内插式基板的球栅阵列封装的示意图；
图13和14是根据本发明一个实施例的包括有一沿其外围具有台阶的金属内插式基板的球栅阵列封装的示意图；
图15是根据本发明一个实施例的带有一金属内插式基板的球栅阵列封装的仰视图；
图16A和16B分别是包括有一通过表面贴装(SMT)接点互连并贴装在印刷线路板上的金属内插式基板的球栅阵列封装的截面图和仰视图；
图17是根据本发明一个实施例的具有一位于绝缘材料上的金属内插式基板的球栅阵列封装的示意图；
图18根据本发明一个实施例的具有一用于焊线互连的中心通孔的导电内插式基板的球栅阵列封装的示意图；
图19A和19B分别是根据本发明一个实施例的中心具有通孔的导电内插式基板结构的横截面图和俯视图；
图20A和20B分别是根据本发明一个实施例的中心具有通孔并具有模型锁定结构的导电内插式基板结构的横截面图和俯视图。
具体实施方式
本发明实施例中所描述的特定的配置及安排，应被理解为所述特定配置及安排仅用于例示说明目的。在没有偏离本发明精神及范围的情况下，相关技术领域的普通技术人员所能认识到的其他配置及安排，也在本发明保护范围之列。此外，本发明还可以应用于相关技术领域普通技术人员所能想到的其他应用领域。
空腔向上球栅阵列封装
图1示出了一种空腔向上球栅阵列封装100。封装100包括芯片102，芯片102通过一种粘合材料(如环氧树脂)粘接在基板104上(例如印刷电路基板)。芯片102上的电路(未示出)通过互连焊线108连接至基板104。封装100可采用成型化合物110进行封装。封装100通过互连设备112连接至PWB(未示出)或类似物，所述互连设备112可为锡球。锡球112-C位于芯片102下的中部位置。
一种空腔向上球栅阵列封装，如封装100，最早由摩托罗拉公司设计采用，被称为过模制衬垫载体(OMPAC)。B.Freyman与R.Pennisi所著的“Overmolded Plastic Pad Array Carders(OMPAC)：A Low Cost，HighInterconnect Density IC Packaging Solution for Consumer and Industrial Electrics”(Electronic Components and Technology Conference，IEEE，pP.176-182，1991)揭露了一种OMPAC，在此将该著作全文作为本发明的参考。塑胶球栅阵列(PBGA)封装，一般称为PBGA封装，以一种塑胶印刷电路板(例如基板)为特征，如基板104，一般采用双马来酰亚胺三嗪(BT)树脂或4型阻燃材料(FR4)制成。
参照图1所示，在空腔向上封装中，一个单一的IC半导体芯片102(或多个IC芯片)可以通过环氧树脂106直接粘合在印刷电路基板104的上表面。焊线108用于电连接IC芯片102的电路至印刷电路基板104。锡球矩阵或阵列112安装在基板104的下表面上。塑胶成型化合物110将IC芯片102和互连焊线108都封装在其内以保护IC芯片102和焊线108不受外围环境的伤害，同时还部分(或全部地)覆盖基板104的上表面。
在某些情况下，BGA封装100表现为较差的热性能。这是因为基板104和塑胶成型化合物110的材料均具有较低的热传导值(例如，BT或FR4型基板的热导系数K＝0.19～0.3W/m℃左右，成型化合物的热导系数K＝0.2～0.9W/m℃左右)。由于芯片102整个被低热导性材料所包围，IC芯片102产生的热都聚集在PBGA封装100内无法散出去。为了释放聚集的热量，IC芯片102必须升温至超过外围环境的温度。
空腔向下球栅阵列封装
图2A示出了一种空腔向下载带球栅阵列(TBGA)封装200。图2B示出了一种带有有机或陶瓷基板的空腔向下BGA封装200′。图2C示出了一种区域卷带自动接合(ATBA)封装200″。上述三种封装之间的主要区别是图2A和图2B中所示的互连焊线208，在图2C中被互连锡球和金突起218所代替。互连装置208和218用于连通各自对应封装中的芯片202与基板204和/或散热器214之间的信号。
为了提高芯片向上分区阵列封装如封装100的热性能，空腔向下BGA封装200、200′与200″，以及空腔向下针栅针列(PGA)封装(未示出)等封装技术发展起来。K.Puttlitz与P.A.Totta所著的“Area Array InterconnectionHandbook”(published by Kluwer Publishing，Boston，2001)第14章中介绍了一种空腔向下的封装，在此将该著作全文作为本发明的参考。在图2A-2C所示的封装200、200′与200″中，芯片202的背面有一热导材料制成的散热器214(如散热片或冷却板)，所述热导材料如铜(热导系数K约为400W/m℃)或陶瓷(热导系数K约为50W/m℃)用于散热及提供低热阻冷却路径。
由于散热器214内的空腔216用于置放封装200、200′、200″中的芯片202，故其不可能放置锡球212或芯片202下的引脚214。由于同样的缘由，为了更高的输入输出(I/O)应用需求而增加封装针脚数量，则通常需要增加封装体积。因此，从封装引脚到芯片上设备(如电子元器件)及I/O的电路长度因为封装基板体积的增加而变长。如果芯片体积较大(例如超过9mm X9mm)，则从芯片202外缘的焊线接点到芯片202的中心区域之间的线路长度会很长。封装基板和芯片上的线路长度增加会导致电路阻抗及电感的增大。根据欧姆定律：I＝V/R，其中，I为电流，V为电压降，R为电阻抗。线路长度的增加导致基板204和芯片202的电阻抗增大，从而导致电压降增加，及基板204和芯片202上的电源输送网路(例如，基板204和芯片202上发送和接收来自供电源的电源的一部分)的载流量降低。
此外，因切换产生的压降杂讯(voltage noise)或切换杂讯(switchingnoise)，与L dI/dt成正比，其中L表示电源输送环路的电感，dI/dt表示电流变化的速率。电感的增加也会导致芯片202内电压下降产生的切换杂讯更高。电流切换频率的增大也将导致高切换杂讯。切换杂讯会导致延迟，从而影响时限，最终导致逻辑错误。
空腔向下阵列封装200、200′与200″的芯片大小一般约为9mm X 9mm或更大，且封装体积较大(例如，约27mm X 27mm至45mm X 45mm)。半导体芯片202上，从封装引脚至芯片202到核心电源以及I/O缓存器的I/O电源网络与该核心之间具有相对较高的电感。由于这些封装中电源输送网络的电感特性及芯片上高频电源输送能力的缺乏，这些封装应用于高速数字系统时受到限制。
带有插入式散热器的空腔向下焊线阵列封装
图3示出了一种TBGA封装300，其带有一插入式散热器320，该插入式散热器320可用作TBGA封装300的电源或接地层。为了提高封装热性能，插入式散热器320位于封装300的芯片封装模型310中。申请号为09/783,034的美国专利申请(申请日为2001年2月15日，申请人为R.Khan和S.Zhao，发明名称为“Enhanced Die-Down Ba1l Grid Array Packages and Method forMaking the Same”)介绍了此种配置结构，在此将该专利申请全文作为本申请的参考。插入式散热器320促进覆盖芯片容置空腔316的塑胶成型化合物310内的热量散发。此外，插入式散热器320既可用作封装300的电源层，亦可用作封装300的接地层。例如，封装芯片302的电源或接地接点可通过焊线308连接至插入式散热器320的外缘。当插入式散热器320的下表面322外露时，其下表面322在表面贴装过程中或表面贴装后焊接至一PCB(未示出)，以连接该PCB电源层或接地层至封装300。一个示例中，软带基板304上的电源或接地层线路和锡球可通过使用散热器320而删去，从而缩短电流线路长度，并降低封装的电感和阻抗。
然而，芯片302与散热起320之间的直接接触可能会损害和缩减芯片302的活性表面及连接芯片302与基板304的焊线308。在此，将1999年10月2日公告的美国专利5,977,626全文作为本实施例描述的参考。
为了改善制造方法，已发展出插入式散热器封装设计的各种变形，用于芯片向上BGA封装。例如，可参看2003年4月22日公告的专利号为6,552,428的美国专利，发明名称为“Semiconductor Package Having An Exposed HeatSpreader”，在此将该专利全文作为参考。
在上述实施例中，插入式散热器和半导体芯片的电源/接地层之间的直接电连接不可能实现。而且，IC芯片被塑胶成型化合物和有机基板所隔离。因此，从芯片散发的热量必须透过塑胶成型化合物到达散热器。一般塑胶成型化合物的热导系数值为0.5～0.9W/m℃，电路化有机基板的热导系数为0.2～2W/m℃。这些热导系数值显著低于铜(热导系数K约为400W/m℃)和铝(热导系数K约为180W/m℃)的热导系数值。因此，热量仍然积聚在IC芯片封装内塑胶成型化合物和有机基板的周围。
带有增强铜板和热/电连接器的球栅阵列封装
图4示出了一种带有一增强板/内插板424的芯片向上的TBGA封装400。增强铜板/内插板424用于增加芯片402和封装400其他部分的热传递区域。2001年10月29日申请的申请号为09/984,259的美国专利申请介绍了此种技术，在此将该专利申请全文作为参考。
如图4所示，芯片402具有两相对的第一表面426和第二428。封装400中，芯片402的第一表面426与增强铜板424贴合。增强铜板424的第二表面430连接至有机基板404，该有机基板可为聚酰亚胺载带或环氧树脂(如双马来酰亚胺三嗪)基板。增强铜板424的表面区域比芯片402的表面区域大，以利于促进热量散发至周围的材料中。芯片402下方的接地/散热球412通过基板404中的接地/散热通孔432连接至铜增强板424。连接IC芯片402的接地/电源接点至金属增强板424进一步降低了因接地电流回流及电源输送产生的封装电感。
带有增强铜板/内插板及热/电连接器的球栅阵列封装
图5示出了一种带有增强板/内插板524和热/电连接器534的芯片向上TBGA封装500。通过在基板504中心区域设置一通孔538，芯片502和PCB(未示出)之间的热电连接可使用热/电连接器534来实现。IC芯片502的第一表面直接连接至增强板524的第一表面。增强铜板524的第二表面与热/电连接器534相连。热/电连接器534将热量和电流从增强铜板524传递给安装封装500的PCB。
与芯片502相接的增强板524(如图5所示)，可通过焊线508连接至芯片502的接地接点。
通过使用热/电连接器534，可降低封装500与PCB或PWB之间因电源输送和电流回流所产生的环路电感。
集成电路内的带电操作
集成电路(IC)上的操作通过电源驱动。操作的速率取决于IC上晶体管与其他元器件的数量及电源输送至上述元器件的输送数度。用于高速宽带通信系统的特定用途集成电路(ASIC)设备的操作频率的提升要求芯片上的电源以较高的电流密度输送并在较短的时间内转换电流。这一点可参看K.T.Tang和E.G.Friedan所著的“Simultaneous Switching Noise in On-Chip CMOS PowerDistribution Networks”(IEEE Transactions on Very Large Scale Integration(VLSI)Systems，Vol.10，No.4，pp.487-493，August 2002)，在此将该文全文作为参考。
IC和超大规模集成电路(VLSI)芯片上采用金属线来输送电源。这些金属线常常因电迁移现象和过量的线阻抗而受干扰。电迁移是因导电电子与离散金属原子之间的动量交换而产生的大规模迁移，其对IC上的金属导体造成累进破坏。关于这一点，可参看W.S.Song和L.A.Glasser所著的“PowerDistribution Techniques for VLSI Circuits”(IEEE Journal of Solid-State Circuit，v.21，pp.150156，Feb.1986)，在此将该文全文作为参考。电迁移在IC金属线内产生断路和短路，这一点可参看Jim Lloyd和David Overhauser所著的“Electromigration wreaks havoc on IC design”(Electroninc Design News，march26，1998，p.145-148)，在此将该文全文作为参考。电力输送的高电流，过量的电源输送线阻抗，结合电源输送的高电流，沿电源输送线路产生电压降。
因电流和阻抗产生的芯片上电源-接地网络的电压降被称为“IR压降”(其中I表示电流，R表示电阻)。关于这一点，可参看S.Lin和N.Chang所著的“Challenges in Power-Ground Integrity”(Proceedings of the 2001 IEEE/ACMInternational Conference on Computer-aided design，pp.651-654，November 4-8，2001)，在此将该文全文作为参考。IR压降沿互连/金属线产生，通过低速转换速度致使性能下降。这一点一般可通过安装足够数量的电源分支和连接以限制电压的下降来避免。
为了缓解因带电阻金属线的高电流产生的问题，一种采用统一置放网状交织的电源和接地金属线/分支而形成的多层电源输送网络被用于芯片上的电源输送。一般采用两层或多层金属来建立电源-接地网络。一较厚的顶层金属用于输送电源至芯片上较大的部分，该层下面较小的金属线用于输送电源至芯片上较小的部分。大部分的示例中，大多数电压降和最大电流密度都集中在顶层。因此，采用特定的制造技术，电压降的功率限制和IR压降的电流密度通过顶层金属厚度的上限而得到控制。
实际上，电源和其他信号都需要通过金属线传输。越厚和越多电源分支意味着留给芯片上信号传输的空间越少，从而可能要求增加芯片大小。由于IC芯片通过焊线互连，电源和I/O接点一般位于芯片外缘。电源接点的统一布置使得较多的I/O信号线接点被推放至芯片的角落处。当I/O信号线接点被推放至芯片角落时，会产生焊线长度和封装线路长度之间的不匹配，从而导致宽I/O焊线的歪斜。关于这一点，可参看2003年12月2日公告的专利号为6,657,870B1的美国专利，专利名称为“Die Power Distribution System”，在此将该文全文作为参考。
具有更有效带电操作的空腔向下球栅阵列封装
如上所述，需要的是提供一种IC封装内的高效电源输送结构，缩短芯片顶部金属层的线路长度，缩小连接芯片电源/接地接点的焊线长度，缩减PCB/PWB电源/接地层至封装的线路长度。因此如上所述，本发明的实施例提供了一种用于IC封装的内插式基板结构。该内插式基板可减小芯片顶层金属的电源和接地接点之间的互连线路长度，还可以去掉电源和接地接点必须位于芯片外缘的要求。电源和接地接点可位于顶层金属的内部区域，在该内部区域，电源和接地接点可以通过导电突起(例如锡球、金等)或焊线连接至内插式基板。
球栅阵列封装实施例
图6A示出了一种TBGA封装600，使用具有连接芯片602的锡球突起652的第二基板650。图6B和6C分别示出了图6A中内插式基板650的俯视图和仰视图。半导体芯片602附着在散热器614的空腔616内。互连焊线608(即一个或多个焊线)用于电连接芯片602外缘656上的焊线接点654至基板604(例如载带基板)和散热器614。第二基板650的内插式基板材料可为有机物(例如BT、FR4等)、陶瓷、玻璃、载带(例如聚酰亚胺载带)或其他绝缘材料。底部填充剂658用于固定芯片602中心区域660的焊线接点(未示出)与内插式基板650之间的互连突起652。底部填充剂658的填充工艺与现有的倒装晶片技术中所采用的方法相同。
具体实施例中，内插式基板650可包括一个、两个或多个(例如1、2、3、4、5...等等)电布线层662。电布线层662可采用迭片结构、堆积或其他相关技术领域普通技术人员所熟知的工艺方法。
图6A所示，内插式基板650内有第一和第二电布线层662，用于芯片602上表面和下表面的电路由。电镀通孔(PTH)664连接基板650的上表面665上的金属线路(未示出)至下表面667上的金属线路或锡球接点(未示出)。
不同示例中，内插式基板650和芯片602的中心区域660之间的互连突起652的材料可为焊锡、金、导电聚合物、环氧/粘胶柱体或其他金属材料。互连突起652的数量不限，可为一互连突起阵列。
一个示例中，互连突起652(例如锡球)可直接固定在芯片602的焊线接点上。接着将内插式基板650放置在芯片602上，同时保证互连突起652与内插式基板650上相应的焊线接点相接触。在不同示例中，可通过锡球型突起的回流或环氧树脂型突起的凝固来实现基板650与芯片602的互连。
另一个示例中，芯片602也可在锡球型突起回流或环氧树脂型突起凝固之前置放于基板650上。
一个示例中，互连锡球652还可以用多种不同的材料固定至内插式基板650上(如图6C所示)。例如，互连突起652的基础材料为铜，该互连突起652可成柱状或截球状放置在内插式基板650上。接着将铜突起652用焊锡、金或其他电导体材料覆盖，此种方式亦可强化与芯片602上的焊线接点654之间的连接。
一个实施例中，一个或多个锡球666用于连接第二基板650至PCB/PWB。如图6B所示，锡球阵列666(例如中心锡球)连接至基板650的下表面667上的锡球接点，用于电连接表面贴装封装600的PCB/PWB(未示出)。需要注意的是，锡球666和突起652作为一完全填充的阵列可成环形(如图6B和6C所示)，或为内插式基板650上任何其他形式的布置。
一个示例中，由于电源输送及接地电流回流，内插式基板650的下表面667上的锡球666与上表面665上的锡球突起652可用来传送与接收I/O信号。
封装材料610用于填充空腔616，覆盖互连焊线608和芯片602。在该实例中，内插式基板650的下表面667未被封装材料610覆盖。一个示例中，封装方法与TBGA封装所使用的方法相同(例如，围堰填充(dam-and-fi1l)或固顶密封(Glob top))。
另一个实施例中，BGA封装600具有一金属内插式基板650。本实施例的各种示例设计中，内插式基板650可由金属或其他电导体材料制成。例如，内插式基板650可为铜或铝板。上表面665上的镀银或镀锡接点654用于连接锡球突起652，下表面667上的镀银或镀锡接点654用于连接锡球666，从而实现互连。由于内插式基板650在所有的方向都导电，锡球666和突起652仅用于电源输送或接地电流回流(例如，正电源Vdd或负电源Vss)。底部填充剂658用于固定芯片中心区域的焊线接点(未示出)与内插式基板650上表面665上的接点之间的突起652。底部填充剂的填充方法与现有的倒装晶片技术中所采用的方法相同。
图7示出了根据本发明一实施例的载带基板604的支脚高度h1和内插式基板650的支脚高度h2。一个示例中，如果h2小于h1，内插式基板650底部的锡球666的直径d2比载带基板604底部的锡球612的直径d1小，反之亦然。因而：
若h2<h1，d2<d1；
若h2>h1，d2>d1。
通过控制空腔616的深度、芯片602的厚度、内插式基板650的厚度、突起652的直径以及芯片到散热器连接装置的厚度，内插式基板650的支脚高度h2可大于、等于或小于载带基板604的支脚高度h1(即h2<h1、h2＝h1、h2>h1都有可能)。
内插式基板650上的锡球666之间的中心间距(如球距)可与载带基板604上锡球612之间中心间距相同或不同。可将完整的锡球矩阵阵列(M x N)贴装在内插式基板650下表面667上，亦可减少阵列中心或矩阵中间行的锡球666。
图8至图12示出了与图6A中封装600相类似的其他实施例，以下将进行进一步的描述。需要注意的是，这些实施例可以以任何形式组合。
增强型球栅阵列封装
图8示出了一种增强型的BGA(EBGA)封装。图8所示是一种空腔向下的塑胶球栅阵列封装800，具有第二基板850(如印刷电路基板)，通过锡球突起852连接至芯片802的中心区域。该封装800采用一平面散热器814，该平面散热器814可以是一块金属板，一般由铜板制成。带有中心通孔868的有机基板804(如BT或FR4)连接至散热器814。一个示例中，基板804可具有四层或更多金属布线层。需要注意的是，不带内插式基板850的封装800有时候也被称为增强型球栅阵列封装或EBGA。该设计的其他特征一般与上述EBGA的实施例相同。
在内插式基板与芯片之间采用锡球突起和焊线互连的球栅阵列封装
图9A和9B分别示出了BGA封装900的截面图和仰视图，该BGA封装900具有第二基板950(例如内插式基板)，通过突起952和焊线908连接至芯片902。半导体芯片902与内插式基板950之间的电连接通过连接至芯片中心区域的凸起952(如焊锡、金或其他导电材料)和连接至芯片外缘的焊线908来实现。一个示例中，内插式基板950可以包括多层布线层970。例如，内插式基板950可具有四个布线层970。焊线908亦可用作内插式基板950的支架或台阶972和基板904之间的电连接，连接至第二基板950的任一布线层。
一个示例中，如果内插式基板950采用一多层基板，则基板的一个或多个布线层970可暴露在外部用于焊线连接。
图10所示是封装1000，包括有连接内插式基板1050与基板1004和散热器1014的焊线1008。一个示例中，焊线1008用来连接内插式基板1050和散热器1014。
图11所示是封装1100，该封装1100包括有位于内插式基板1150下表面1174上的焊线手指1176。
参照图10和图11，内插式基板1050/1150上的焊线手指1076/1176设置在内插式基板1050/1150的下表面1074/1174上。焊线焊接后，封装基板1004/1104与内插式基板1050/1150上的焊线手指1076/1176均被封装材料1010/1110(如顶部密封材料)覆盖。这些示例中，覆盖在内插式基板1050/1150下表面1074/1174上的顶部密封材料环绕在内插式基板1050/1150外围边缘，而中心区域暴露在外(即未被封包材料1010/1110所覆盖)。覆盖在封装基板1004/1104下表面上的封装材料靠近芯片1002/102的内部区域，而外围区域(靠近基板1004/1104的外边缘区域)没有被覆盖。封装材料1010/1110的厚度必须被控制，以使封装材料的支脚高度h2足够大，以使封装基板1004/1104的锡球1012/1112和内插式基板1050/1150的锡球1066/1166在表面贴装至PCB/PWB时塌陷(collapse)。
带有通过接点栅格阵列互连并贴装在PWB上的内插式基板的封装
图12示出了封装1200，包括内插式基板1250，通过接点栅格阵列(LGA)1280互连并表面贴装至PWB 1282上。与图6～11所示的球栅阵列互连方式不同的是，第二基板1250下表面1274上的无掩蔽导电接点阵列1284可用来与表面贴装封装1200的PWB 1282电连接，而无需附加锡球。这一示例中，内插式基板1250的支脚高度h3足够小，以保证当封装1200安装在PWB 1282上时，内插式基板1250下表面1274上的无掩蔽导电接点阵列1284可与PWB1282上相应位置的锡膏阵列1280(如预先印刷好的锡膏柱)相接触。经过回流工艺后，锡膏柱1280与外围锡球1212一起塌陷并凝固，连接内插式基板1250与PWB 1282。
一个示例中，无掩蔽导电接点阵列1284可采用铜接点。该无掩蔽接点阵列互连也称为接点栅格阵列(LGA)。无掩蔽导电接点阵列1284表面可以有涂层，例如，在表面镀锡、银或其他导电材料，以帮助锡在表面贴装过程中被润湿。
一个示例中，内插式基板1250亦可设有一引脚阵列(未示出)用于与PWB1282的互连。
带有金属内插式基板的球栅阵列封装
图13示出了球栅阵列封装1300，包括一金属内插式基板1350，该内插式基板1350沿其外围设有一台阶1364。为提高内插式基板1350的模型闭合性能，金属内插式基板1350外围的一个或多个突架或台阶1364可通过蚀刻、冲压或其他金属成型方法加工出来。封装材料1310覆盖台阶1364，以紧固闭合内插式基板1350。台阶1364的侧壁1366可被封装材料完全覆盖或者部分覆盖。
图14示出了球栅阵列封装1400，包括一金属内插式基板1450，该内插式基板1450沿其外围设有一台阶1464。如图所示，沿半导体芯片1402外缘的电源或接地接点1468可通过一条或多条焊线1408与内插式基板1450连接。
一个示例中，为了便于焊线连接的实现，金属内插式基板1450的台阶1464上的焊线表层1470可选择地通过电镀或其他表面涂覆方法涂覆一层银、金或其他导电材料。例如，电镀材料1452可涂覆在焊线表层1470上。
一个示例中，散热器1414可通过一条或多条焊线与内插式基板1450连接。
图15是根据本发明一个实施例的带有内插式基板1550的球栅阵列封装1500的仰视图。如图15所示，为避免短路，内插式基板1550与散热器1514之间的焊线连接1508设置在角落处。该示例中，为了显示出封装材料1510下的封装结构，封装材料1510显示为透明。从内插式基板1550到芯片1502和散热器1514的焊线连接1508均在图中示出。
当散热器1514和金属内插式基板1550之间互连后，散热器1514和金属内插式基板1550处于相同的电位。散热器1514内的空腔(未示出)成为法拉第静电屏蔽室(Faraday cage)容置半导体芯片1502。由此可见，这种封装结构可以提供极佳的电磁干扰(EMI)屏蔽，不论是从封装1500内的芯片1502辐射出的电磁干扰还是从封装1500外辐射至芯片1502的电磁干扰都能屏蔽。带有通过表面贴装接点互连并贴装至PWB上的金属内插式基板的球栅阵列封装
图16A和16B分别是球栅阵列封装1600的截面图和仰视图，该球栅阵列封装1600包括一金属内插式基板1650，具有用于互连并表面贴装(surfacemount)至PWB 1674的SMT接点1672(参看图16B)。SMT接点矩阵1672可设置在金属内插式基板1650下表面1658上，用以连接PWB 1674。这种方式与前面所述的采用LGA连接内插式基板与PWB的方式相同。下表面1658可选择地采用各种金属如锡、银、金或其他金属进行沉积处理，以利于在表面贴装过程中能更好地与PWB 1674上相对应的接点1676(如印刷锡膏)焊接。上述所提到的各种参数，如支脚高度h3，用于确定如何配置该内插式基板以应用于某一特定用途。
位于绝缘材料上的金属内插式基板
图17所示为球栅阵列封装1700，包括一位于绝缘材料1778上的金属内插式基板1750。本实施例中，不需要采用锡球或其他导电突起来作为内插式基板1750与集成电路芯片1702之间的电连接。焊线1708用于连接内插式基板1750与芯片1702外缘上的电源或接地接点1768。类似的结构可参看申请号为09/783,034，申请日为2001年2月15日，发明名称为“Enhanced Die-DownBall GridArray Packages and Method for Making the Same”的美国专利申请的图3，将该美国专利申请全文在此作为本实施例的参考。但是，图17中所示的绝缘材料1778位于金属内插式基板1750与芯片1702的上表面1780之间。一个示例中，绝缘材料1778可防止导电内插式基板1750与芯片1702上表面1780上的电路(图中未示出)直接接触，而从防止出现短路。绝缘材料1778可为载带、BT、FR4、陶瓷、热介面材料(TMI)、粘附性材料或本领域普通技术人员所熟知的其他类似材料。
导电内插式基板具有中心通孔用于焊线互连的球栅阵列封装
图18所示为球栅阵列封装1800，包括一具有中心通孔1882用于焊线连接的导电内插式基板1850。此种配置结构可使用一条或多条焊线将金属内插式基板1850与芯片1802中心区域的电源或接地接点(图中未示出)连接起来。如图18所示，基板1850还绕通孔1882周围设有一突架或台阶1883，以利于焊线连接，焊线可沿通孔1882延伸。台阶1883可部分或全部环绕于通孔1882。
图19A和19B分别示出了具有中心通孔1982的导电内插式基板1950结构的横截面图和俯视图。中心通孔1982用于焊线互连。一个示例中，如图19A所示，内插式基板1950侧壁1986上的浇口(mold gate opening)1984用于封装工艺中的模内流动成型。
带有通孔1984的内插式基板1950可用来取代图18所示的空腔向下封装1800中的内插式基板1850。一示例中，封装1800采用围堰填充(例如固顶密封)工艺封装芯片，则芯片1802附着在散热器1814上后，内插式基板1950附着在芯片1802的中心区域上。焊线焊接完成后，基板1804上围绕接点手指(如焊线位置处)的外围设置有塑胶屏障(dam)(图18中未标示)。随后，在该屏障和金属内插式基板1905的上基架之间填充成型化合物。成型化合物经浇口1984流至金属内插式基板1950的下部，并覆盖芯片1802，以达到环境保护之目的。
图20A和20B分别示出了导电内插式基板2050结构的横截面图和俯视图，该基板包括一中心通孔2082和一个或多个锁模机构2088。为固定内插式基板2050，可在金属内插式基板2050上设置锁模突起或凹口2088。锁模突起或凹口2088的形状可设置为但不限于梯形或三角形。
各个示例中，中心通孔1802、1902与2002的形状可为圆形(如图19B所示)、方形(如图20B所示)或其他规则或不规则的形状。
其他特征及实施例
本发明其他的特征及优点描述如下：
内插式基板(如图6A-6C和图7中的基板650，图8中的基板850，图9中的基板950，图10中的基板1050，图11中的基板1150，图12中的基板1250，图13中的基板1350，图14中的基板1450，图15中的基板1550，图16A-16B中的基板1650，图17中的基板1750，及图18中的基板1850)与半导体芯片的中心区域连接，实现与半导体芯片在其中心区域的互连，而不增加互连阻抗和电感。
该内插式基板可用于电源分配和电源输送，还可用于信号路由。
导电突起和焊线均可用于内插式基板和芯片之间的互连。
内插式基板可通过多种类型的互连方式(如锡球、焊线)连接同一芯片上的不同焊接接点。内插式基板可通过球栅阵列封装、针栅阵列、单一的焊接接点或导电接点阵列与PCB或PWB电连接。从封装芯片上的焊接接点到PCB/PWB的线路长度也因路由距离的缩减而缩短。
内插式基板上的锡球中心到中心的距离(又称为球间间距)可与封装基板上的外部球栅阵列的球间间距相同，也可以不同。
完整的锡球矩阵阵列(M x N)可附着在内插式基板的下表面上。根据需求，中心部分的锡球或位于中间行的锡球数量亦可适当减少(例如被移除)。
内插式基板的中心通孔可实现与封装芯片中心区域的焊接接点的焊线互连。
在内插式基板上设计一锁定机构，可增强带有内插式基板的空腔向下封装的结构的整体性。
该内插式基板可从各种类型的基板中选择，如有机物基板、载带基板或陶瓷基板、高密度基板、内建式基板或特氟纶(Teflon)基板等等。该内插式基板可使用单布线层基板或多层基板。该内插式基板可采用铜、铝等导体材料。
本发明可采用固顶密封、注塑成型或其他芯片封装工艺。
用于空腔向下封装的散热器，可连接至采用电导体材料制成的内插式基板的相同电势处，或连接至单层或多层内插式基板的电源/接地层以形成一电磁干扰(EMI)屏蔽室，如用于容置半导体芯片的法拉第屏蔽室。
金属内插式基板可采用各种金属表面成型工艺、材料或方法，应用于该内插式基板的各点各面。
该内插式基板可通过一个或多个焊线连接至封装基板以及封装散热器。
该内插式基板可使用各种不同结构(如台阶、通孔等)或形状(如方形、矩形、圆形、辐射状、切口、凹口和一边或多边上形成的台阶等)来缩短焊线长度，降低封装装配工艺中短路的风险，并增强封装机械性能、散热性能、电学性能与稳定性能。
现有的空腔向下阵列封装中，封装的底部中央是芯片封装材料，未与安装该封装的PWB有电接触(如图2所示的实施例中)。封装下表面与PWB(未示出)之间的间隙因空气的低热导性能(空气热导系数k＝0.026W/m℃，封装模型的热导系数k＝0.7W/m℃左右)而阻碍了从芯片到PWB的热量传导。
但是，使用本发明所述的内插式基板，为IC芯片和应用电路板(如PCB或PWB)之间的热流提供了热传导路径。封装的散热性能亦因此而提高，尤其当内插式基板采用金属材质(如铜)时，热导性能因板结合处的热阻抗降低而提高。
将空腔向下封装中的内插式基板的金属层和散热器接地，即可很容易构建一电磁干扰屏蔽室(如法拉第屏蔽室)来容置该半导体芯片。
IC芯片装配在散热器和内插式基板接地层内，散热器和内插式基板接地层形成一电势面，如接地电压，以充分地封装该IC芯片。
此种结构可防止封装内电磁干扰辐射泄漏到封装外，亦可阻止外部的电磁干扰辐射进入空腔内部。
为满足电源分配、输送与信号路由的各种不同应用需求，内插式基板可相应采用各种不同的材料。
为满足各种不同应用需求及提供各种不同形状及外观的封装，可相应采用各种不同的芯片封装工艺，包括固顶密封、注塑成型或其他类似工艺等。
上述对本发明各种不同实施例的描述，应被理解为仅用于示例说明之目的，本发明不仅限于上述实施例。对于相关技术领域普通技术人员可理解的是，在本发明的精神和范围内作一定的修改、变化或等效替换都是显而易见的。本发明的范围，不仅限于上述实施例，应参考本申请的权利要求而确定。

Claims (10)

1、一种球栅阵列封装，其特征在于，包括：
散热器；
第一基板，具有沿所述第一基板贯通的通孔，所述第一基板连接至所述散热器，所述散热器的一部分可通过所述通孔被接触；
IC芯片，设置在所述第一基板的通孔中并与所述散热器连接；
第二基板，具有第一表面和第二表面，所述第一表面附着在所述IC芯片中部，所述第二表面具有一接触焊点阵列，用于与安装所述球栅阵列封装的电路板连接；
焊线排列，包括连接所述IC芯片至所述散热器的焊线、连接所述IC芯片至所述第一基板的焊线、连接所述IC芯片至所述第二基板的焊线；
封装材料，至少部分覆盖所述散热器、第一基板、第二基板和IC芯片；
其中，所述第二基板具有一中心通孔且沿所述中心通孔内侧形成有第一台阶，所述第二基板沿其外围具有第二台阶，所述连接IC芯片至第二基板的焊线包括连接所述IC芯片中部的接点至所述第二基板的第一台阶的焊线和连接所述IC芯片外缘的接点至所述第二基板的第二台阶的焊线。
2、根据权利要求1所述的球栅阵列封装，其特征在于，所述散热器包括有一空腔，所述IC芯片附着在其内，所述空腔的开口比所述第一基板的通孔的直径小。
3、根据权利要求1所述的球栅阵列封装，其特征在于，所述第二基板的第一表面与所述IC芯片之间设有绝缘材料。
4、根据权利要求1所述的球栅阵列封装，其特征在于，所述焊线排列进一步包括：
连接所述第二基板至所述散热器的焊线；
连接所述第二基板至所述第一基板的焊线。
5、根据权利要求4所述的球栅阵列封装，其特征在于，所述连接第二基板至散热器的焊线包括连接所述第二基板外围的第二台阶至所述散热器的焊线。
6、一种球栅阵列封装的制造方法，其特征在于，包括：
a.在第一基板的通孔中，连接一IC芯片至一散热器，所述第一基板的通孔沿所述第一基板延伸贯通，所述散热器的一部分通过所述通孔与所述IC芯片接触；
b、将第二基板附着在所述IC芯片中部；
c、采用焊线排列连接所述IC芯片至所述散热器、连接所述IC芯片至所述第一基板、连接所述IC芯片至所述第二基板；
d、采用封装材料至少部分地覆盖所述散热器、第一基板、第二基板和IC芯片；
其中，所述步骤c进一步包括：
在所述第二基板上形成一中心通孔；
沿所述中心通孔的内侧形成第一台阶；
沿所述第二基板的外围形成第二台阶；
使用焊线连接所述IC芯片中部的接点至所述第二基板的第一台阶；
使用焊线连接所述IC芯片外缘的接点至所述第二基板的第二台阶。
7、根据权利要求6所述的球栅阵列封装的制造方法，其特征在于，所述步骤a包括：在所述散热器中形成一空腔以容置所述IC芯片，所述空腔的开口比所述第一基板的通孔的直径小。
8、根据权利要求6所述的球栅阵列封装的制造方法，其特征在于，所述步骤b包括：通过绝缘材料将所述第二基板附着在所述IC芯片中部。
9、根据权利要求6所述的球栅阵列封装的制造方法，其特征在于，所述方法进一步包括：采用焊线排列连接所述第二基板至所述散热器、连接所述第二基板至所述第一基板。
10、根据权利要求9所述的球栅阵列封装的制造方法，其特征在于，所述方法进一步包括：采用焊线排列连接所述第二基板外围的第二台阶至所述散热器。
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US8021927B2 (en) 2011-09-20
US20100285637A1 (en) 2010-11-11
TWI319223B (en) 2010-01-01
CN1773698A (zh) 2006-05-17
US7786591B2 (en) 2010-08-31
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US20060065972A1 (en) 2006-03-30
EP1643551A2 (en) 2006-04-05

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