CN100498914C

CN100498914C - Power circuit of grid drive circuit of thin film transistor liquid crystal display panel

Info

Publication number: CN100498914C
Application number: CNB2006100012381A
Authority: CN
Inventors: 左仲先; 王德峻; 张芳龙
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2006-01-10
Filing date: 2006-01-10
Publication date: 2009-06-10
Anticipated expiration: 2026-01-10
Also published as: CN101000748A

Abstract

A power supply circuit of grid driving circuit on liquid crystal display face plate of film transistor type is featured as making output signal of said power supply circuit be decreased from high-level to low-level slowly for solving problem of image residue by using two power supply signals to make control circuit in power supply circuit to act correctly when normal work and switching-off is done by said power supply circuit.

Description

The power circuit of LCD panel of thin-film transistor gate driver circuit

Technical field

The present invention relates to a kind of LCD panel of thin-film transistor, particularly about a kind of power circuit of LCD panel of thin-film transistor gate driver circuit.

Background technology

In thin film transistor (TFT) (TFT) LCD (LCD) panel system, in order to make picture when starting shooting, present best picture quality, and design control circuit control boot program, after being postponed through one, power supply signal exports to gate driving IC, to obtain best picture quality.Fig. 1 is the synoptic diagram of the power circuit 100 of known TFT LCD panel gate driver circuit, one low voltage logic circuit 160 connects a power supply signal VIN, produce a control signal CRL to the output of control circuit 150 according to a clock signal VFLK who produces by clock pulse control IC with control power circuit 100, input to power circuit 100 after the one power supply signal VGH by the VIN generation connects an electric capacity 108, behind control circuit 150, produce the gate driver circuit 124 that an output signal VGHM gives TFT LCD.Low voltage logic circuit 160 comprises that a delay circuit 110 is connected with VIN to produce an inhibit signal, the input of this inhibit signal and VIN conduct or door 112, this inhibit signal and VFLK be as the input of Sheffer stroke gate 114, or the output of door 112 and Sheffer stroke gate 114 as with the input of door 116 to produce CRL.Control circuit 150 comprises switch 118 and 120 and one resistance 122 that is connected with switch 120, the unlatching by CRL gauge tap 118 and 120 or close, and then the output of control power circuit 100.Fig. 2 is sequential Figure 200 of Fig. 1, simultaneously with reference to figure 1 and Fig. 2, when electric power starting VIN rises to high level by low level, VGH begins to rise to high level by low level, unlatching by CRL gauge tap 118 and 120 or close, make VGH behind control circuit 150, produce the gate driving IC 124 that a VGHM who differs a time delay 210 with VIN gives TFT LCD, so that picture promptly presents best picture quality in a start, time delay 210 is different with the difference of panel vendor, approximately between between the 20ms to 100ms, this moment is if VFLK is a high level, then be output as low level with door 116, switch 118 and 120 is respectively opening and closed condition, VGHM equals VGH, when if VFLK is low level, then be output as high level with door 116, switch 118 and 120 is respectively closed condition and opening, VGHM is via resistance 122 discharge generation top rake 240 over the ground, promote the picture quality of TFT LCD panel to improve the situation that TFT LCD panel picture flashes (flicker) fall time of putting in order top rake 240 via the adjustable size that changes resistance 122.But when power-off, VGHM just drops to low level by high level in a short period of time, shown in zone 220, make TFT when carrying out shutdown, still have the residual image residue that wherein causes of electric charge on panel, to produce ghost phenomena, this ghost phenomena can be via making VGHM drop to low level by high level lentamente when carrying out shutdown, shown in zone 230, so that the electric charge among the TFT discharges fully and solves.

In the prior art, making VGHM be dropped to low level method lentamente by high level when carrying out shutdown has to go up at printed circuit board (PCB) (PCB) and increases required assembly or two kinds of increase by one big electric capacity between VGHM and gate driving IC.The benefit that increases assembly on printed circuit board (PCB) is to improve by the top rake of adjusting VGHM the quality of picture, and its shortcoming is that the assembly that increases causes the increase of manufacturing cost.The benefit that increases by a big electric capacity between VGHM and gate driving IC is can not increase manufacturing cost, and its shortcoming is to improve by the top rake of adjusting VGHM the quality of picture.

Therefore, designing a kind of power circuit that can not increase manufacturing cost and can adjust top rake and the TFT LCD panel gate driver circuit of eliminating ghost, is the problem that industry needs to be resolved hurrily.

Summary of the invention

Purpose of the present invention is to provide a kind of power circuit of adjusting top rake and can eliminating the TFT LCD panel gate driver circuit of ghost phenomena.

According to the present invention, a kind of power circuit of gate driver circuit of TFT LCD panel comprises: a low voltage logic circuit, connect one first power supply signal, and produce a control signal according to a voltage signal, described first power supply signal comprises master battery signal, and described voltage signal is a clock signal by clock pulse control IC output; One shutdown circuit connects first power supply signal and a second source signal, produces an off signal with the state of judging described power circuit, and described second source signal is a power supply signal by described first power supply signal generation; An and control circuit, control the output of described power circuit according to control signal and off signal, described control circuit comprises: a level displacement circuit has second control signal and the 3rd control signal of varying level according to control signal and off signal generation; One driver element is controlled the unlatching of one first switch and a second switch or is closed according to second and third control signal, and then controls the output of described power circuit; And a resistance, be connected between second switch and the earth terminal; One first switch is used for opening or cutting out according to the control of described second control signal; One second switch is used for opening or closing according to the control of described the 3rd control signal.

The present invention utilizes power circuit that two power supply signals make TFT LCD panel gate driver circuit all to have signal to make the correct start of control circuit in this power circuit in operate as normal and when carrying out shutdown, make that the output signal of this power circuit slowly drops to low level by high level when carrying out shutdown, the single power supply signal can't make the correct start of control circuit in the solution prior art when carrying out shutdown, causes the output signal of power circuit to be dropped rapidly to the ghost phenomena that low level produces by high level.

Description of drawings

Fig. 1 is the synoptic diagram of the power circuit of known TFT LCD panel gate driver circuit.

Fig. 2 is the sequential chart of Fig. 1.

Fig. 3 is the synoptic diagram of the power circuit of TFT LCD panel gate driver circuit of the present invention.

Fig. 4 is the synoptic diagram of shutdown control circuit among Fig. 3.

Fig. 5 is the synoptic diagram of one embodiment of the present of invention.

Fig. 6 is the sequential chart of Fig. 5.

Fig. 7 is the circuit diagram of level shift and driver element among Fig. 5.

100 power circuits, 108 electric capacity

110 delay circuits 112 or door

114 Sheffer stroke gates 116 and door

118 switches, 120 switches

122 resistance, 124 gate driver circuits

150 control circuits, 200 sequential charts

210 time delays 220 zone

230 regional 240 top rakes

300 power circuits, 310 low voltage logic circuit

320 shutdown circuits, 322 detecting units

324 detecting units, 326 state judging units

328 shutdown logics, 330 control circuits

340 level displacement circuits, 350 driver elements

360 switches, 370 switches

510 level shifts of 380 resistance and driver element

520 electric capacity, 540 delayers

550 Sheffer stroke gates 560 or door

570 gate driver circuits, 600 sequential charts

610 carry out off-mode 620 normal operating conditionss

630 carry out off-mode 640 off-mode

650 time delays 660 top rake

710 level displacement circuits, 712 displacement units

714 buffer cells, 716 displacement units

718 buffer cells, 720 not gates

722 not gates, 750 driver elements

752 not gates, 754 not gates

762 resistance, 764 switches

Embodiment

Fig. 3 is the synoptic diagram of the power circuit 300 of TFT LCD panel gate driver circuit of the present invention, power circuit 300 comprises that a low voltage logic circuit 310 connects master battery signal VIN1, produce a control signal CRL1 according to a voltage signal VFLK (a for example clock signal by clock pulse control IC product), one shutdown circuit 320 connects a VIN1 and a power supply signal VIN2 by the VIN1 generation, and judge that according to VIN1 and VIN2 the state of power circuit 300 produces an off signal Pwr0ff, one control circuit 330 makes an input signal VGH (for example by VIN1 generation power supply signal) produce the gate driver circuit that output signal VGHM gives TFT LCD behind control circuit 330 according to the output of CRL1 and Pwr0ff control power circuit 300.Control circuit 330 comprises that a level displacement circuit 340 produces control signal CRL2 and CRL3 according to CRL1 and Pwr0ff, one driver element 350 is according to the unlatching of CRL2 and

CRL3 gauge tap

360 and 370 or close to produce VGHM, when switch 360 is opened, VGHM charges to VGH, when switch 370 was opened, VGHM discharged over the ground via a resistance 380.

Fig. 4 is the synoptic diagram of shutdown control circuit 320 among Fig. 3, with reference to Fig. 3 and Fig. 4, level generation signal PG1 and PG2 that detecting unit 322 and 324 detects VIN1 and VIN2 respectively give state judging unit 326, PG1 is a logical one when VIN1 is high level, otherwise then be logical zero, similarly, PG2 is a logical one when VIN2 is high level, otherwise then be that " 0 '; state judging unit 326 is judged the state of power circuit 300 according to PG1 and PG2; when PG1 is that logical one and PG2 are when being logical zero; power circuit 300 is for carrying out open state, when PG1 and PG2 were logical one, power circuit 300 be a normal operating conditions to logic; when PG1 is that logical zero and PG2 are when being logical one; power circuit 300 is the execution off-mode, and when PG1 and PG2 were logical zero, power circuit 300 was off-mode, when shutdown logic 328 is judged power circuit 300 for the execution off-mode at state judging unit 326, produce off signal Pwr0ff.

Fig. 5 is an embodiment of the power circuit 300 of TFT LCD panel gate driver circuit of the present invention, one low voltage logic circuit 310 comprises a delayer 540, one or the door 560 and one Sheffer stroke gate 550, delayer 540 connects VIN1 to produce an inhibit signal, the input of this inhibit signal and VIN1 conduct or door 560, this inhibit signal and VFLK are as the input of Sheffer stroke gate 550, one shutdown circuit 320 connects VIN1 and VIN2, level according to VIN1 and VIN2 produces Pwr0ff, one control circuit 330 comprises level shift and driver element 510,

switch

360 and 370 and be connected resistance 380 between switch 370 and the earth terminal, or door 560 and the output of Sheffer stroke gate 550 and Pwr0ff are as the input of level shift and driver element 510, with the unlatching that produces control

signal gauge tap

360 and 370 or close, VGH connects an electric capacity 520 and produces VGHM to gate driver circuit 570 through control circuit 330 after.In this embodiment,

switch

360 and 370 is respectively PMOS transistor and the nmos pass transistor that grid connects level shift and driver element 510 output terminals.

Fig. 6 is the sequential chart 600 of Fig. 5, with reference to Fig. 5 and Fig. 6, when electric power starting, VIN1 rises to high level by low level and produces a starting-up signal PG, power circuit 300 enters carries out open state 610, VIN2 and VGH rise to high level in response to PG gradually by low level subsequently, power circuit 300 enters normal operating conditions 620, delayed device 540 outputs one of PG and PG differ the inhibit signal PGD of a time delay 650, VGHM is just produced after power supply is stable, so that picture promptly has best picture quality in start at the beginning, time delay 650 is approximately between between the 20ms to 100ms, this moment control circuit 330 according to or the

output control switch

360 and 370 of door 560 and Sheffer stroke gate 550, when VFLK is high level, level shift and driver element 510 are output as low level,

switch

360 and 370 is respectively opening and closed condition, VGHM equals VGH, when VFLK is low level, level shift and driver element 510 are output as high level,

switch

360 and 370 is respectively closed condition and opening, VGHM is via resistance 380 discharge generation top rake 660 over the ground, promote the picture quality of TFT LCD panel to improve the situation that TFT LCD panel picture flashes (flicker) fall time of putting in order top rake 660 via the adjustable size that changes resistance 380.When power-off, VIN1 drops to low level by high level and finishes PG, power circuit 300 enters carries out off-mode 630, VIN2 and VGH drop to low level in response to the end of PG gradually by high level, low voltage logic circuit 310 is closed at this moment, shutdown circuit 320 produces Pwr0ff, control circuit 330 makes

switch

360 and 370 maintain opening and closed condition respectively according to Pwr0ff, make VGHM identical with the level of VGH, drop to low level by high level gradually, eliminate ghost phenomena with the electric charge that release remains among the TFT, when VIN1 and VIN2 were low level, power circuit 300 was off-mode 640.

Fig. 7 is the circuit diagram of level shift and driver element 510 among Fig. 5, level shift and driver element 510 comprise level displacement circuit 710 and driver element 750, level displacement circuit 710 comprises

buffer cell

714 and 718 and

displacement unit

712 and 716, driver element 750 comprise level at not gate between VGH and the VIN2 752 and level the not gate 754 between VIN2 and earth terminal, displacement unit 712 is connected between buffer cell 714 Sheffer stroke gates 752, displacement unit 716 is connected between buffer cell 718 Sheffer stroke gates 754, buffer cell 714 is made of the not gate 720 of several level between VIN1 and earth terminal, buffer cell 718 is made of the not gate 722 of several level between VIN1 and earth terminal, and

displacement unit

712 and 716 is made of several PMOS and nmos pass transistor.The output CRL1 of low voltage logic circuit enters

displacement unit

712 and 716 respectively behind

buffer cell

714 and 718, shutdown logic 328 comprises that a resistance 762 is connected between VIN2 and the switch 764, shutdown logic 328 produces Pwr0ff according to the output of state judging unit 326, and Pwr0ff directly imports displacement unit 712 and 716.In the present embodiment, switch 764 is the nmos pass transistor of a grid connection status judging unit 326 output terminals.When normal operating conditions, VIN1 and VIN2 are high level, displacement unit 712 according to CRL1 produce the control signal CRL2 of level between VGH and VIN2 give not gate 752 with gauge tap 360 unlatching or close, displacement unit 716 according to CRL1 produce the control signal CRL3 of level between VIN2 and earth terminal give not gate 754 with gauge tap 370 unlatching or close.When carrying out off-mode, VIN1 is a low level and VIN2 is a high level, the Pwr0ff that shutdown logic 328 produces is a high level, displacement unit 712 produces CRL2 according to Pwr0ff and opens for not gate 752 force switch 360, displacement unit 716 produces CRL3 according to Pwr0ff and closes for not gate 754 force switch 370, makes VGHM and VGH have identical level.

The foregoing description is only in order to explanation the present invention, and non-limiting the present invention.

Claims

1. the power circuit of a LCD panel of thin-film transistor gate driver circuit is characterized in that, comprising:

One low voltage logic circuit connects one first power supply signal, and produces a control signal according to a voltage signal, and described first power supply signal comprises master battery signal, and described voltage signal is a clock signal by clock pulse control IC output;

One shutdown circuit connects first power supply signal and a second source signal, produces an off signal with the state of judging described power circuit, and described second source signal is a power supply signal by described first power supply signal generation; And

One control circuit is controlled the output of described power circuit according to control signal and off signal, and described control circuit comprises:

One level displacement circuit has second control signal and the 3rd control signal of varying level according to control signal and off signal generation;

One driver element is controlled the unlatching of one first switch and a second switch or is closed according to second and third control signal, and then controls the output of described power circuit; And

One resistance is connected between second switch and the earth terminal;

One first switch is used for opening or cutting out according to the control of described second control signal;

One second switch is used for opening or closing according to the control of described the 3rd control signal.

2. power circuit as claimed in claim 1 is characterized in that, described low voltage logic circuit comprises:

One delayer connects first power supply signal to produce an inhibit signal;

One or door, produce one first according to first power supply signal and inhibit signal and export;

One Sheffer stroke gate produces one second output according to voltage signal and inhibit signal; And

One with door, produce control signal according to first and second output.

3. power circuit as claimed in claim 1 is characterized in that, described shutdown circuit comprises:

One first detecting unit detects the level of first power supply signal;

One second detecting unit, the level of detection second source signal;

One state judging unit is according to the state of the electrical level judging power circuit of first and second power supply signal; And

One shutdown logic is when state judgment unit judges power circuit is when carrying out off-mode, to produce off signal.

4. power circuit as claimed in claim 3 is characterized in that, described shutdown logic comprises:

One switch opens or cuts out according to the output of state judging unit; And

One resistance is connected between second source signal and the switch.

5. power circuit as claimed in claim 4 is characterized in that described switch comprises a nmos pass transistor, the output of its grid connection status judging unit.

6. power circuit as claimed in claim 3 is characterized in that, described state judging unit is a low level at the level of first power supply signal, and the level of second source signal judges that described power circuit is for carrying out off-mode when being high level.

7. power circuit as claimed in claim 1 is characterized in that, described level displacement circuit comprises:

One first displacement unit is given described driver element in order to produce second control signal;

One first buffer cell, the connection control signal and first displacement unit;

One second displacement unit is given described driver element in order to produce the 3rd control signal; And

One second buffer cell, connection control signal and second displacement unit.

8. power circuit as claimed in claim 7 is characterized in that, described first and second buffer cell is made of a plurality of not gate.

9. power circuit as claimed in claim 7 is characterized in that, described first and second displacement unit is made of a plurality of PMOS and nmos pass transistor.

10. power circuit as claimed in claim 1 is characterized in that, described driver element comprises two not gates that level is different.

11. power circuit as claimed in claim 1 is characterized in that, described first switch comprises a PMOS transistor, and its grid connects second control signal.

12. power circuit as claimed in claim 1 is characterized in that, described second switch comprises a nmos pass transistor, and its grid connects the 3rd control signal.