CN100492624C - External pin structure, active part array base plate, photoelectric device and making method - Google Patents
External pin structure, active part array base plate, photoelectric device and making method Download PDFInfo
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- CN100492624C CN100492624C CN 200710170332 CN200710170332A CN100492624C CN 100492624 C CN100492624 C CN 100492624C CN 200710170332 CN200710170332 CN 200710170332 CN 200710170332 A CN200710170332 A CN 200710170332A CN 100492624 C CN100492624 C CN 100492624C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
This invention relates to an outer pin structure set on a base board, an active element array base board, a photoelectric device and its manufacturing method, in which, the outer pin structure includes multiple first outer pins, multiple second outer pins and a patternized dielectric layer, in which, the first one is matched on the base board including multiple actually parallel first leads and multiple first connection points at the ends of the first leads, the second outer pins are set on the base board including multiple second leads and multiple second connecting points at the ends of the second leads, and each of the second connection point is overlapped with part of a first lead, the patternized dielectric layer is set between the first and second outer pins to expose the first connection points.
Description
Technical field
The present invention relates to a kind of external pin structure, have active component array base board and the electrooptical device and the manufacture method thereof of aforementioned external pin structure, and relate in particular to a kind of the have external pin structure of three-dimensional arrangement design, active component array base board and electrooptical device and manufacture method thereof with aforementioned external pin structure.
Background technology
At present, LCD is widely used in the electronic products such as mobile phone, TV, mobile computer, and for adapting to the demand in market, except the continuous increase of the size of liquid crystal display equipment screen picture, the resolution of screen also constantly upwards promotes, so the output signal of LCD inside chip or the usage quantity of chip also must increase thereupon.
Technical in the chip join of LCD, chip can be connected in by several configuration mode in the LCD, such as be with chip adhesive on glass substrate (Chip On Glass, COG), or with chip adhesive on soft board (Chip On Film, COF).
At present, with regard to the configuration mode of chip adhesive on glass substrate, dispose a plurality of outer pin between the viewing area that is connected in chip and LCD on the glass substrate.In order to adapt to the increase of chip signal output, the number density of outer pin also with raising.But for the further configuration density that improves contact, so prior art is the size that the contact of outer pin is dwindled or dwindled to the spacing (pitch) of the outer pin on the glass substrate.
Yet, when the spacing between the outer pin on the glass substrate is little to a certain degree the time, will influence the aligning accuracy of board, and then reduce the yield of technology because of the capacity limit that exceeds board.In addition, the size of lug on the chip must be dwindled for the design that cooperates the small size contact.When the size of the projection on the chip is little to a certain degree the time, the intensity of shear of projection can reduce, so projection comes off easily and make reliability on the low side, and then increases cost of manufacture.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of external pin structure and manufacture method thereof, can increase the outer pin density on the substrate and not need the spacing between the contact on the substrate is dwindled or dwindled the size of contact.
Another purpose of the present invention is to provide a kind of active component array base board and manufacture method thereof, can increase the output signal that is disposed at the chip on the active component array base board.
Still a further object of the present invention is to provide a kind of electrooptical device and manufacture method thereof, can improve the screen resolution of display floater in the electrooptical device.
For achieving the above object, the invention provides a kind of external pin structure, and external pin structure is to be configured on the substrate.External pin structure comprises a plurality of first outer pin, a plurality of second outer pin and a pattern dielectric layer.The first outer pin is to be configured on the substrate, and the first outer pin comprises many first parallel in fact leads and a plurality of first contacts that are positioned at first wire end.The second outer pin is to be configured on the substrate, and the second outer pin a plurality of second contacts of comprising many second leads and being positioned at second wire end, and each second contact partly overlaps with one first lead wherein.Pattern dielectric layer is outside first outside the pin and second between the pin, and pattern dielectric layer exposes first contact.
And, for achieving the above object, the invention provides a kind of electrooptical device, and electrooptical device comprises at least one above-mentioned external pin structure.
And for achieving the above object, the present invention proposes a kind of active component array base board, and active component array base board comprises a substrate, a plurality of pixel cell, a plurality of first outer pin, a plurality of second outer pin and a pattern dielectric layer.Wherein, substrate has a viewing area and a perimeter circuit district that is positioned at outside the viewing area, and pixel cell then is disposed in the viewing area.The first outer pin configuration is electrical connected in the perimeter circuit district and with pixel cell, and the first outer pin a plurality of first contacts of comprising many first leads and being positioned at first wire end.The second outer pin configuration is electrical connected in the perimeter circuit district and with pixel cell, and the second outer pin a plurality of second contacts of comprising many second leads and being positioned at second wire end, and each second contact partly overlaps with one first lead wherein.Pattern dielectric layer is disposed between the first outer pin and the second outer pin, and pattern dielectric layer exposes first contact.
In one embodiment of this invention, first contact is arranged along a first direction, and second contact is arranged along a second direction, and first direction is parallel in fact with second direction.
In one embodiment of this invention, second lead and first lead partly overlap.
In one embodiment of this invention, each second lead comprises one first section, one second section and one the 3rd section, first section overlaps with first lead and is connected first contact, and second section is connected between first section and the 3rd section, the 3rd section and first lead is parallel to each other is staggered.
In one embodiment of this invention, the 3rd section is to be made by identical rete with the first outer pin.
In one embodiment of this invention, wherein at least one is staggered arrangement in fact between each first contact and between each second contact.
And the present invention also proposes a kind of manufacture method of external pin structure, comprising: form pin outside a plurality of first on a substrate, and the first outer pin comprises many first parallel in fact leads and a plurality of first contacts that are positioned at first wire end.On substrate, form a pattern dielectric layer, and pattern dielectric layer covers part first lead and exposes first contact.On pattern dielectric layer, form pin outside a plurality of second, and a plurality of second contacts that the second outer pin comprises many second leads and is positioned at second wire end, and second contact and first lead overlap partly.
And the present invention proposes a kind of manufacture method of active component array base board, and the manufacture method of active component array base board comprises the manufacture method of above-mentioned external pin structure.
And the present invention proposes a kind of manufacture method of electrooptical device, and the manufacture method of electrooptical device comprises the manufacture method of above-mentioned external pin structure.
External pin structure of the present invention can make the first outer pin and the second outer pin present three-dimensional arrangement design and only arrange outer pin on two dimensional surface and the contact distribution density of pin can't promote outside feasible problem to improve in the prior art.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is that a kind of external pin structure of one embodiment of the invention is disposed at the schematic diagram on the substrate;
Fig. 2 A is along the profile of I-I ' line segment among Fig. 1;
Fig. 2 B is along the profile of II-II ' line segment among Fig. 1;
Fig. 3 is that the another kind of external pin structure of one embodiment of the invention is disposed at the schematic diagram on the substrate;
Fig. 4 is that another external pin structure of one embodiment of the invention is disposed at the schematic diagram on the substrate;
Fig. 5 is that another external pin structure of one embodiment of the invention is disposed at the schematic diagram on the substrate;
Fig. 6 is that the another kind of external pin structure of one embodiment of the invention is disposed at the schematic diagram on the substrate;
Fig. 7 is the schematic diagram of a kind of active component array base board of one embodiment of the invention;
Fig. 8 is the schematic diagram of a kind of electrooptical device of one embodiment of the invention;
Wherein, Reference numeral:
100,300,400: external pin structure 110,310: the first outer pins
112,312: the first leads 114,314,412,612: the first contacts
120,320: the second outer pins 122,322: the second leads
122a: first section 122b: second section
122c: the 3rd section 124,324,422,512: the second contacts
130: pattern dielectric layer 132: opening
134: contact hole 200,710: substrate
700: active component array base board 712: viewing area
714: perimeter circuit district 720: pixel cell
800: electrooptical device 810: display floater
820: electronic component A: first direction
B: second direction
Embodiment
Fig. 1 is the schematic diagram of a kind of external pin structure of one embodiment of the invention, and Fig. 2 A be among Fig. 1 along the profile of I-I ' line segment, Fig. 2 B is along the profile of II-II ' line segment among Fig. 1.Please be simultaneously with reference to Fig. 1, Fig. 2 A and Fig. 2 B, external pin structure 100 of the present invention is configured on the substrate 200.Substrate 200 can be transparency carrier (as: glass substrate, quartz base plate, or other substrate), flexible base plate (as: plastic base, the thinning glass substrate, the polyesters substrate, polyketone class substrate, the polyethers substrate, the polyester substrate, the polyalkenes substrate, carbene class substrate, poly-epoxy alkene class substrate, poly-cyclenes class substrate, poly-naphthenic substrate, polyamides class substrate, poly-phenols substrate, polyacetals class substrate, or other polymer class substrate, or above-mentioned combination), opaque substrate (as: silicon chip, pottery, or other substrate), printed circuit board (PCB), bendable printed circuit board (PCB), have printing brush plate and bendable printed circuit board (PCB) simultaneously, or other circuit board or substrate that is fit to.External pin structure 100 comprises a plurality of first outer pin 110, a plurality of second outer pin 120 and a pattern dielectric layer 130.The first outer pin 110 is configured on the substrate 200, and the first outer pin 110 comprises many first parallel in fact leads 112 and a plurality of first contacts 114 that are positioned at these first lead, 112 ends, and wherein first lead 112 is connected with first contact 114.
The second outer pin 120 also is to be configured on the substrate 200.Second contact 124 that the second outer pin 120 comprises second lead 122 and is positioned at second lead, 122 ends, wherein second lead 122 is connected with second contact 124, and each second contact 124 all overlaps with one first lead 112 part wherein.In addition, in present embodiment, second lead 122 and first lead 112 can partly overlap.Wherein at least one is single layer structure or sandwich construction for the first outer pin 110 and the second outer pin 120, and its material comprises transparent materials (as: gold, silver, copper, iron, tin, plumbous, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminium, metals such as zinc, above-mentioned alloy, above-mentioned metal oxide, above-mentioned metal nitride, or above-mentioned combination), transparent material (as: indium tin oxide, indium-zinc oxide, the aluminium zinc oxide, the aluminium zinc oxide, the cadmium tin-oxide, the cadmium zinc oxide, indium tin zinc oxide, hafnium oxide, zinc oxide, or other material, or above-mentioned combination), or above-mentioned combination.
In addition, outside the pin 110 and second between the pin 120, just the first outer pin 110 and the second outer pin 120 are electrically insulated in fact pattern dielectric layer 130 outside first.Wherein, pattern dielectric layer 130 is single layer structure or sandwich construction, and its material comprises inorganic (as: silica, silicon nitride, silicon oxynitride, hafnium oxide, hafnium nitride, zinc oxide, zinc nitride, carborundum, or other material, or above-mentioned combination), organic material (as: the silicide of carbon containing hydrogen-oxygen, polyalcohols, the polyamides class, poly-inferior acyl class, benzocyclobutene, polyesters, the polyketone class, polyethers, polyalkenes, photoresistance, poly-cyclenes class, the polyalkylene oxide class, poly-naphthenic, poly-phenolic, poly-phenols, the polyacetals class, or other base polymer, or above-mentioned combination), or above-mentioned combination.Pattern dielectric layer 130 has a plurality of openings 132 to expose first contact 114.Certainly, pattern dielectric layer 130 also can be only to cover first lead 112 of a part and expose first contact 114 and another first lead 112 partly, and another first lead 112 partly that exposes can't produce with follow-up conductive coating structure and electrically connects, and the second outer pin 120 that also promptly comprises the first outer pin 110 of first lead 112 and comprise second lead 122 still is electrically insulated in fact and can allows institute's transmission signals be transmitted on the original outer pin.
Yet, external pin structure 100 of the present invention is not limited to this, just external pin structure 100 can be two-layer above conductor structure, for example: external pin structure 100 also have the 3rd outer pin (not illustrating), all round pin (not illustrating) and by second pattern dielectric layer (not illustrating), the 3rd pattern dielectric layer (not illustrating) is with separation and insulate.
From the above, external pin structure 100 of the present invention has the first outer pin 110 and the second outer pin 120, and, the first outer pin 110 and the second outer pin 120 are electrically insulated in fact by the pattern dielectric layer 130 separation first outer pin 110 and the second outer pins 120.Therefore, the present invention can make outer pin 110,120 carry out the three-dimensional arrangement design problem that the density of pin 110,120 can't promote outside feasible to improve prior art only to arrange outer pin 110,120 on two dimensional surface.Also therefore, the present invention can effectively increase the quantity of the outer pin 110,120 on the substrate 200 under the spacing or the situation of the size of contact 114,124 of not dwindling between the contact 114,124.
In other words because the present invention can effectively promote the density of outer pin 110,120, therefore on the equal area of substrate 200 the present invention can than prior art arrangement more outside pin 110,120.And the total amount of pin 110,120 transmission signals outside the more outer pin 110,120 of configuration can help to increase on substrate 200.Therefore, when external pin structure 100 is applied in display unit, will help to promote the resolution of screen.Certainly, the present invention also can be that outer pin 110,120 numbers of configuration on substrate 200 are identical with the outer number of pins of prior art, and still the area of outer pin 110, the 120 of the present invention substrate 200 shared than the outer pin of prior art is little.Therefore, under the situation of identical transmission signals total amount, outer pin 110,120 of the present invention helps to dwindle the area of substrate 200.Or outer pin 110,120 of the present invention can increase the degree of freedom of other element (not illustrating) configuration on the substrate 200.
Then, please continue with reference to Fig. 1, Fig. 2 A and Fig. 2 B, the manufacture method of the external pin structure 100 of present embodiment is as described below.On substrate 200, form pin 110 outside a plurality of first, and the first outer pin 110 comprises one first parallel in fact lead 112 and one first contact 114 that is positioned at first lead, 112 ends.Then, on substrate 200, form a pattern dielectric layer 130, and pattern dielectric layer 130 covers first leads 112 and expose first contact 114 and be example, but be not limited thereto.Afterwards, on pattern dielectric layer 130, form one second contact 124 that pin 120, the second outer pins 120 comprise one second lead 122 and are positioned at second lead, 122 ends outside a plurality of second, and second contact 124 and the first partly overlapping of lead 112.
The manufacture method of the external pin structure 100 of present embodiment can be applied in the manufacture method of active component array base board, or is applied in the manufacture method of electrooptical device.When the manufacture method of the external pin structure 100 of present embodiment is applied in the manufacture method of active component array base board; the first outer pin 110 and the second outer pin 120 can form simultaneously with the conductor line in the active component array base board, and pattern dielectric layer 130 then can form simultaneously with dielectric layer in the active component array base board (as: insulating film layer, inner layer dielectric layer, protective layer, and flatness layer, dye coating or other rete or above-mentioned combination).In other words, the manufacture method of the external pin structure 100 of present embodiment can be compatible with in the middle of the active cell array technology.In addition, the manufacture method of the external pin structure 100 of present embodiment, come as example with deposition, exposure and etching mode, but be not limited thereto, also can ink-jetting style, screen painting mode, deposition and laser divests (laserablation) mode or alternate manner or above-mentioned combination.
In present embodiment, second lead 122 comprises one first section 122a, one second section 122b and one the 3rd section 122c.Wherein, first section 122a overlaps with part first lead 112 and also directly is connected second contact 124.Second section 122b is connected between first section 122a and the 3rd section 122c.The 3rd section 122c and first lead 112 are arranged in parallel with each other, and the 3rd section 122c and second section 122b partly overlap and electrically connect by contact hole 134.The 3rd section 122c can be to be made by identical rete with the first outer pin 110.In other embodiment, the 3rd section 122c also can be to be made by different retes with the first outer pin 110.In other words, external pin structure has by the first outer pin of different rete mades and the second outer pin, but not as limit, also can be made by identical rete.
In present embodiment, first contact 114 can be arranged along a direction A, and second contact 124 can be arranged along a second direction B, and first direction A is parallel in fact with second direction B.That is to say that the arrangement mode of first contact 114 and second contact 124 is to change synchronously.Below will in Fig. 3～Fig. 6, introduce other multiple arrangement mode of first contact 114 and second contact 124.Certainly, below explanation only is the enforcement example, and the present invention is not as limit.
In addition, please refer to Fig. 3, each 314 of first contact of external pin structure 300 of the present invention and each 324 of second contact in fact all are height and are staggered.In addition, the arrangement mode of first contact 314 and second contact 324 is to change synchronously.By prior art as can be known, the staggered joint configuration mode of height helps to improve the distribution density of contact, and the present invention is height is staggered except being positioned at first contact 314 with one deck, and second contact 324 that also has another layer conductor layer to be formed also can be height and be staggered.Therefore, external pin structure 300 of the present invention can have higher outer pin 310,320 distribution densities.
In addition, as shown in Figure 4, external pin structure 400 of the present invention can be that 412 of at least two first contacts and at least two second 422 of contacts in fact all are height and are staggered.In present embodiment, be in fact all to be height with 412 of per three first contacts and 422 of per three second contacts to be staggered be example, but be not limited thereto, also can four, five, six, more than seven or the like, and the number of first contact of each group, optionally be same as or be different from the number of second contact of another group.In other words, several can be arranged in the present embodiment with the first online always contact 412 and be considered as one group, just be staggered mutually and respectively organize first contact 412.In like manner, also several can be arranged in the present embodiment with the second online always contact 422 and be considered as one group, just be staggered mutually and respectively organize second contact 422.The height that presents that in addition, in groups these first contact 412 and second contact 422 can be synchronous or nonsynchronous is staggered.
Moreover as shown in Figure 5, the direction that first contact 114 is arranged also can be not parallel with the direction that second contact 124 is arranged, and the step ground that just differs from one another changes.First contact 114 can be to arrange along first direction A, 512 of second contacts then are to be height in fact to be staggered, and the number of second contact 512 of this kind arrangement mode, can be one, two, three, four, five, more than six or the like, or as shown in Figure 6,124 of second contacts can be to arrange along second direction B, first contact 612 then is to be height in fact to be staggered, and the number of first contact 612 of this kind arrangement mode, can be one, two, three, four, five, more than six or the like.
Below will further specify the embodiment that external pin structure 300 of the present invention is applied to active component array base board.Certainly, below explanation only is the enforcement example, and the present invention is not as limit.
Fig. 7 is the schematic diagram of a kind of active component array base board of one embodiment of the invention.Please refer to Fig. 7, active component array base board 700 of the present invention comprises a substrate 710, a plurality of pixel cell 720, a plurality of first outer pin 310, a plurality of second outer pin 320 and the pattern dielectric layer 130.Substrate 710 has a viewing area 712 and a perimeter circuit district 714 that is positioned at outside this viewing area 712, and pixel cell 720 is positioned at viewing area 712.The first outer pin 310 is disposed in the perimeter circuit district 714, and the first outer pin 310 is electrical connected with pixel cell 720.The second outer pin 320 is disposed in the perimeter circuit district 714, and the second outer pin 320 is electrical connected with pixel cell 720.In addition, pattern dielectric layer 130 is disposed between the first outer pin 310 and the second outer pin 320, and pattern dielectric layer 130 exposes first contact 314.The mode that pattern dielectric layer 130 exposes first contact 314 can be that pattern dielectric layer 130 has the position and exposes first contact 314 and another first lead 312 partly corresponding to a plurality of openings 132 of first contact 314 or first lead 312 of pattern dielectric layer 130 cover parts.Yet embodiments of the invention, to have being staggered of the first outer pin 310 and the second outer pin 320 in one of them perimeter circuit district 714 is example, but be not limited thereto, the arrangement mode of the first outer pin 310 and the second outer pin 320 also can be selected the wherein at least a arrangement mode from the foregoing description.And the first outer pin 310 and the second outer pin 320 are arranged in several perimeter circuits district 714, and visual its design is gone up the number (as: 1,2,3, more than 4 or the like) in demand and perimeter circuit district 714 and decided.Moreover the present invention is arranged on the active component array base board 700 external pin structure 300 with as example, but is not limited thereto.For instance, the present invention also can select with described wherein at least one arrangement mode of the external pin structure of the foregoing description be arranged on drive circuit (as: IC, chip) and the zone that outer member is connected, on flexible printed circuit and the zone that outer member is connected, on printed circuit board (PCB) and the zone that outer member is connected or other with zone that outer member is connected on or the combination in any of above-mentioned zone.Wherein, outer member can be lead, contact mat, have circuit or other element or an above-mentioned combination in any of transmitting semiotic function.
Fig. 8 is the schematic diagram of a kind of electrooptical device of one embodiment of the invention.Please refer to Fig. 8, in present embodiment, external pin structure of the present invention can be applied in the electrooptical device 800, and electrooptical device 800 comprises a display floater 810, at least one electronic component 820.Display floater 810 and electronic component 820 dispose the external pin structure that is used to transmit signal in one of them at least, and wherein external pin structure can be the described any or multiple external pin structure of the foregoing description.When display floater 810 is display panels, display floater 810 can be the penetrating type display floater, the semi penetration type display floater, reflective display panel, colored filter display floater of (color filter on array) on active layers, active layers display floater of (array on color filter) on colored filter, vertical orientation type (VA) display floater, horizontal switch type (IPS) display floater, multi-domain perpendicular alignment-type (MVA) display floater, twisted nematic (TN) display floater, super-twist nematic (STN) display floater, pattern vertical orientation type (PVA) display floater, super pattern vertical orientation type (S-PVA) display floater, the advanced person is type (ASV) display floater with great visual angle, fringe field switch type (FFS) display floater, continuous fireworks shape arrange type (CPA) display floater, axial symmetry is arranged micella type (ASM) display floater, optical compensation curved arrange type (OCB) display floater, super horizontal switch type (S-IPS) display floater, advanced super horizontal switch type (AS-IPS) display floater, extreme edge electric field switch type (UFFS) display floater, stabilizing polymer alignment-type display floater, double vision angle type (dual-view) display floater, three visual angle type (triple-view) display floaters, 3 d display (three-dimensional) or other profile plate, or above-mentioned combination.In addition, display floater also can be organic electric-excitation luminescent displaying panel (as: fluorescence organic electric-excitation luminescent displaying panel, phosphorescence organic electric-excitation luminescent displaying panel or above-mentioned combination), and the molecule of phosphorescence and fluorescence can be micromolecule, big molecule or above-mentioned combination.Moreover, display floater also can be the inorganic electroluminescence display floater, perhaps display floater also can be hybrid display floater (hybrid display panel), and for example: display panels has liquid crystal composition and electroluminescence composition or electric exciting light emitting display panel simultaneously and has organic electric-excitation luminescent composition and inorganic electroluminescence composition simultaneously.
In addition, electronic component 820 can be control element, executive component, treatment element, input element, memory element, driving element, light-emitting component, protection component, sensing element, detecting element or other function element or aforesaid combination.The type of electrooptical device 800 comprises the panel in portable product (as mobile phone, video camera, camera, mobile computer, game machine, wrist-watch, music player, electronic mail transceiver, map navigator, digital photo or similar products like), video and audio product (as audio-visual projector or similar products like), screen, TV, indoor/outdoor billboard or the projector.
In sum, external pin structure of the present invention has the first outer pin and the second outer pin, and separates the first outer pin and the second outer pin by pattern dielectric layer, and the first outer pin and the second outer pin are electrically insulated in fact.Therefore, the present invention externally pin carry out three-dimensional arrangement design and existing only on two dimensional surface, arrange outer pin and the density of pin can't promote outside feasible problem to improve.Also therefore, the present invention can effectively increase the density of outer pin on the substrate under the spacing between the contact that does not dwindle on the substrate or the size of contact.When external pin structure is applied in display unit, can promote the resolution of screen.Therefore in addition, in the technology of active component array base board, also can make external pin structure of the present invention in the lump, make that external pin structure of the present invention can not increase manufacturing cost and method is simple and easy, but be not limited thereto.For instance, the present invention can be not make with the technology of active component array base board yet.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (16)
1. an external pin structure is disposed on the substrate, it is characterized in that, this external pin structure comprises:
The a plurality of first outer pin is disposed on this substrate, and those first outer pins comprise many first parallel leads and a plurality of first contacts that are positioned at those first wire ends;
The a plurality of second outer pin, be disposed on this substrate, a plurality of second contacts that those second outer pins comprise many second leads and are positioned at those second wire ends, and respectively this second contact partly overlaps with this first lead respectively, and respectively this first lead is electrically insulated with this second contact respectively; And
One pattern dielectric layer is formed on those first outer pins, and exposes those first contacts, and those second outer pins are formed on the pattern dielectric layer.
2. external pin structure according to claim 1 is characterized in that, those first contacts are arranged along a first direction, and those second contacts are arranged along a second direction, and this first direction is parallel with this second direction.
3. external pin structure according to claim 1 is characterized in that, those second leads and those first leads partly overlap.
4. external pin structure according to claim 1, it is characterized in that, respectively this second lead comprises one first section, one second section and one the 3rd section, those first section overlaps with those first leads and is connected those second contacts, those second section is connected between those first section and those the 3rd section, those the 3rd section with those first lead is parallel to each other is staggered.
5. external pin structure according to claim 4 is characterized in that, those the 3rd section is to be made by identical rete with those first outer pins.
6. external pin structure according to claim 1 is characterized in that, wherein at least one is staggered arrangement between each those first contact and between each those second contact.
7. an active component array base board is characterized in that, comprising:
One substrate has a viewing area and a perimeter circuit district that is positioned at outside this viewing area;
A plurality of pixel cells are disposed in this viewing area;
The a plurality of first outer pin is disposed in this perimeter circuit district, and is electrical connected with those pixel cells, a plurality of first contacts that those first outer pins comprise many first leads and are positioned at those first wire ends;
The a plurality of second outer pin, be disposed in this perimeter circuit district, and be electrical connected with those pixel cells, a plurality of second contacts that those second outer pins comprise many second leads and are positioned at those second wire ends, and respectively this second contact partly overlaps with this first lead respectively, and respectively this first lead is electrically insulated with this second contact respectively; And
One pattern dielectric layer is formed on those first outer pins, and exposes those first contacts, and those second outer pins are formed on the pattern dielectric layer.
8. active component array base board according to claim 7 is characterized in that, those first contacts are arranged along a first direction, and those second contacts are arranged along a second direction, and this first direction and this second direction are parallel to each other.
9. active component array base board according to claim 7 is characterized in that, those second leads and those first leads partly overlap.
10. active component array base board according to claim 7, it is characterized in that, respectively this second lead comprises one first section, one second section and one the 3rd section, those first section overlaps with those first leads and is connected those second contacts, those second section is connected between those first section and those the 3rd section, those the 3rd section with those first lead is parallel to each other is staggered.
11. active component array base board according to claim 10 is characterized in that, those the 3rd section is to be made by identical rete with those first outer pins.
12. active component array base board according to claim 7 is characterized in that, it is characterized in that between each those first contact and between each those second contact, at least one is staggered and arranges.
13. the manufacture method of an external pin structure is characterized in that, comprising:
Form pin outside a plurality of first on a substrate, those first outer pins comprise many first parallel leads and a plurality of first contacts that are positioned at those first wire ends;
On this substrate, form a pattern dielectric layer, cover those first leads of part and expose those first contacts; And
On this pattern dielectric layer, form pin outside a plurality of second, a plurality of second contacts that those second outer pins comprise many second leads and are positioned at those second wire ends, and those second contacts and those first leads partly overlap, and those first leads are electrically insulated with this second contact respectively.
14. the manufacture method of an active component array base board is characterized in that, comprises the manufacture method of the described external pin structure of claim 13.
15. an electrooptical device is characterized in that, comprises the described external pin structure of at least one claim 1.
16. the manufacture method of an electrooptical device is characterized in that, comprises the manufacture method of the described external pin structure of claim 13.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710170332 CN100492624C (en) | 2007-11-12 | 2007-11-12 | External pin structure, active part array base plate, photoelectric device and making method |
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| CN 200710170332 CN100492624C (en) | 2007-11-12 | 2007-11-12 | External pin structure, active part array base plate, photoelectric device and making method |
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| CN101150104A CN101150104A (en) | 2008-03-26 |
| CN100492624C true CN100492624C (en) | 2009-05-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103076937B (en) * | 2013-01-30 | 2016-04-27 | 福建科创光电有限公司 | The electrode pin of capacitive touch screen |
| CN105093728A (en) * | 2015-07-10 | 2015-11-25 | 武汉华星光电技术有限公司 | Drive circuit and liquid-crystal display panel |
| CN106292111B (en) * | 2016-10-20 | 2019-08-20 | 深圳市华星光电技术有限公司 | A kind of array substrate and liquid crystal display panel |
| CN110061037A (en) * | 2019-04-25 | 2019-07-26 | 京东方科技集团股份有限公司 | Flexible base board and display device |
| WO2020232690A1 (en) * | 2019-05-23 | 2020-11-26 | 深圳市柔宇科技有限公司 | Pin structure and flexible panel |
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