CN100490140C - 双规引线框 - Google Patents

双规引线框 Download PDF

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Publication number
CN100490140C
CN100490140C CNB031460666A CN03146066A CN100490140C CN 100490140 C CN100490140 C CN 100490140C CN B031460666 A CNB031460666 A CN B031460666A CN 03146066 A CN03146066 A CN 03146066A CN 100490140 C CN100490140 C CN 100490140C
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CN
China
Prior art keywords
lead frame
chip
lead
frame part
pedal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031460666A
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English (en)
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CN1571151A (zh
Inventor
周伟煌
白志刚
C·H·布朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to CNB031460666A priority Critical patent/CN100490140C/zh
Priority to US10/644,160 priority patent/US6917097B2/en
Priority to US11/043,224 priority patent/US7033866B2/en
Publication of CN1571151A publication Critical patent/CN1571151A/zh
Application granted granted Critical
Publication of CN100490140C publication Critical patent/CN100490140C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

一种用于半导体器件的引线框(20)包括第一引线框部分(12)，它具有限定一空腔(16)的周长，自周长向内延伸的多个引线(14)及第一厚度。第二引线框部分(18)固定到第一引线框部分(16)。第二引线框部分(18)具有接收在第一引线框部分(12)的空腔(16)内的芯片踏板(20)。第二引线框部分(18)的第二厚度大于第一引线框部分(12)的厚度。该双规引线框特别适用于高功率器件，其中芯片踏板充当散热器。

Description

双规引线框
技术领域
本发明涉及集成电路及封装的集成电路，且特别涉及一种用于封装的集成电路的引线框。
背景技术
集成电路(IC)芯片是一个在半导体晶片(如硅晶片)上形成的小器件。引线框是一个金属框架，其通常包括一支持已经从晶片中切除的IC芯片的踏板。引线框具有提供外部电连接的引线接头。即，将芯片固定到芯片踏板上，然后通过引线接合将芯片的焊盘与引线接头固定以此提供外部电连接。用保护材料将芯片与引线接合封装以此形成一封装.视封装类型而定可按现状(例如在薄型小尺寸封装(TSOP)中)使用外部电连接，或通过固定用于球栅阵列(BGA)的球状焊球以进一步处理外部电连接。这些端点允许芯片与例如在印刷电路板上的其他电路电连接。
引线框通常由铜或镍合金形成。一种方法是通过焊接将芯片固定到芯片踏板上。高功率器件需要极其高温的焊接固定(大约300℃)及回流焊(device reflow)(大约260℃)。但是，在高温下引线框电镀易退化，这会影响引线焊接过程。特别是，由于电镀表面之冶金变化及助焊剂污染影响了金线的结合能力。此外，最好使用一厚的芯片踏板用于高功率器件以促进散热。但是，分离(切割或冲)一由极厚的金属形成的引线框非常困难且不可靠。
理想的是提供一具有良好散热且不难分离的引线框.此外，理想的是能够通过不导致缺陷的高温方法将芯片固定到芯片踏板上。
发明内容
本发明是用于半导体器件的引线框.该引线框包括一第一引线框部分及一第二引线框部分。第一引线框部分具有一限定一空腔的周长及多个自周长向内延伸的引线。第二引线框部分固定到第一引线框部分且具有一芯片踏板，其尺寸被设计成可被接收于第一引线框部分的空腔内.第二引线框部分的厚度约是第一引线框部分的厚度的两倍.该第一及第二引线框部分最好是由铜形成的且彼此电绝缘。通过为芯片踏板及引线接头提供分离的引线框部分，可在将该第一及第二引线框部分放在一起之前进行芯片固定，由此芯片固定及回流焊(软熔)过程的高温不会影响引线接头。此外，提供与引线接头分开的芯片踏板允许这两部分具有不同厚度.因此，芯片踏板可以是厚的，以允许良好散热，而引线接头较细以便容易进行分离。
本发明还提供一种半导体器件，具有第一及第二金属引线框部分，一集成电路芯片，金属丝及一密封物.第一引线框部分具有围绕一空腔的多个引线。第二引线框部分固定到第一引线框部分且彼此电绝缘。第二引线框部分具有一被接收于第一引线框部分的空腔内的芯片踏板.第二引线框部分的厚度大于第一引线框部分的厚度.集成电路芯片被固定到位于空腔内的芯片踏板上且被上述多个引线围绕.芯片包括通过金属丝电连接到相应引线的多个芯片焊盘.密封物覆盖该集成电路芯片的顶面，上述金属丝，及上述引线的顶面，并且暴露至少上述引线的一个底面及该第二引线框的一个底面。相对较厚且具有一暴露的表面的芯片踏板可用作芯片的散热器。相对薄的引线接头易于分离。
本发明还包括一种封装多个半导体器件的方法，其同时包括以下步骤：
提供第一引线框面板，该第一引线框面板具有多个第一引线框部分，每个第一引线框部分具有一限定一空腔的周长及自周长向内延伸的多个引线，其中该第一引线框面板具有第一及第二面及一第一厚度；
沿着第一引线框面板的外周长形成第一配合结构；
将黏合剂施用在该第一引线框面板的第一面上；
提供一第二引线框面板，该第二引线框面板包括多个第二引线框部分，每个第二引线框部分包括具有第一及第二表面及一第二厚度的芯片踏板；
沿着第二引线框面板的外周长形成第二配合结构；
将多个半导体芯片固定到上述芯片踏板的相应第二表面，其中每个半导体芯片在其表面上具有多个焊盘；
将第二引线框面板堆栈在第一引线框面板上以使上述芯片踏板的第一表面可被接收于相应的空腔内且接触黏合剂，且第一及第二配合结构彼此配合；
利用多个金属丝将上述多个芯片焊盘与上述各个第二引线框部分的上述多个引线中的相应引线电连接；
在第二引线框面板的第二表面，芯片及电连接上方形成一模塑料；及
进行将多个第一及第二引线框部分自该引线框面板中分开的分离操作，从而形成单个封装的器件.
附图说明
结合附图将更好地了解下述详细说明的本发明的较佳实施例.为了说明本发明，附图展示了一目前较佳的实施例.但是应了解，本发明不限于图中所展示的精确布置及手段。在附图中：
图1是根据本发明一实施例的封装的半导体器件的放大剖面图；
图2是根据本发明一实施例的第一引线框面板的俯视平面图；
图3是根据本发明一实施例的第二引线框面板的俯视平面图；
图4A-4G是根据本发明一实施例的形成双规(dual gauge)引线框半导体器件的方法的侧面剖面图；及
图5是根据本发明一实施例的一封装的半导体器件的放大立体图.
具体实施方式
下文的详细说明连同附图仅仅是说明本发明的该目前较佳实施例，其并不代表本发明可以实施的唯一形式.应了解，包含在本发明的精神及范围内的不同实施例可以实现相同或等同功能.本领域的技术人员应了解，本发明可以应用在各种封装及封装类型中.
附图中的某些特征已被放大以方便说明，且附图及组件不必按照固有的比例。此外，本发明所展示的内容体现在四面扁平无引线(QFN)类型封装中。但是，本领域的技术人员不难理解本发明之详细内容，且本发明适用于其他封装类型。在附图中，使用相同数字代表相同部件。
现在参见图1，图中示出了根据本发明的半导体器件10的一实施例的放大的剖面图。半导体器件10包括第一引线框部分12，其具有围绕空腔16的多个引线14。该第一引线框部分12最好由金属或金属合金形成且具有一第一预定厚度。第二引线框部分18被固定到第一引线框部分12。第二引线框部分18包括一被接收于第一引线框部分的空腔16内的芯片踏板20。空腔16的尺寸及形状是根据封装的IC芯片尺寸及形状形成。因此，尽管空腔16通常是矩形或正方形，但是其可具有其他形状，视集成电路芯片的形状而定。第二引线框部分18最好具有不同于第一厚度的第二厚度。例如，对于生成许多热量的电源电路而言，第二引线框部分18可用作一散热器。在这种情况下，第二厚度最好大于第一厚度。在一更优选的实施例中，第一厚度约为或小于第二厚度的一半。在一个实例中，制造一引线框，其中第一部分具有约为8密尔的第一厚度且第二厚度约为20密尔。这些尺寸允许第一引线框部分容易地分离，且同时第二引线框部分提供良好的散热。
该第一及第二引线框部分12及18最好由金属或金属合金形成，例如铜并且可以电镀。在一个实施例中，第二引线框部分18包括一0.5mm厚的铜块。如本领域的技术人员所知的那样，上述引线框部分12及18可以通过压制、冲压或蚀刻形成。通过例如胶带的黏合剂将第二引线框部分18固定到第一引线框部分12，下文将予以更详细说明，尽管彼此连接，但是最好使它们彼此电绝缘。这种电绝缘是本发明的一个重要特征，尤其对于多芯片装配而言。
集成电路芯片22被固定到芯片踏板20上，由于芯片踏板位于空腔内，芯片22被多个引线14围绕。集成电路芯片22可以是一种本领域的技术人员熟悉的类型，例如在硅晶片上形成的并自该硅晶片切下形成的电路。如前所述，空腔16的尺寸和形状被设计成可以接收芯片22。典型的芯片尺寸可从4毫米 x 4毫米到12毫米 x 12毫米。上述芯片22可具有一从约0.15mm到约0.525mm范围的厚度。以已知方式将芯片22固定到芯片踏板20，例如通过焊接固定方法，此方法允许热量通过焊料24从芯片22消散到芯片踏板20。在其他实施例中，可通过一黏合剂材料层或一胶带将芯片22固定到芯片踏板20。
芯片22包括多个芯片焊盘26。最好使用一引线焊接方法，通过金属丝28将芯片焊盘26与相应引线14电连接。上述金属丝及引线焊接方法为本领域的技术人员所熟知。在一个实施例中，使用一种0.05mm的金丝且在另一实施例中使用0.25mm的铝丝。但是，可使用不同材料及直径的各种已知金属丝，包括涂层(绝缘的)及非涂层的金属丝。
半导体器件10还包括密封物30，覆盖集成电路芯片22的顶面、金属丝28及引线14的顶面，剩下至少上述引线14的一底面及第二引线框部分18的一底面暴露在外。上述引线14的暴露部分用以将器件10连接到其他器件，例如通过一PCB，芯片踏板20的暴露底面允许从中散热。密封物30可包括一通常用于封装的电子器件的塑料，且该塑料通过压模法形成在引线框部分12及18，芯片22及金属丝28的上方。器件10的一示范实施例的总厚度约为2毫米。
参见图2，图中示出了根据本发明的第一引线框面板32的俯视平面图。第一引线框面板32包括一第一引线框部分34的阵列。在该实例中，引线框面板32是3x3阵列。但是实际上，上述阵列通常更大。而且，阵列中的行数不必与列数相等。每个第一引线框部分34包括一周长，该周长定义空腔36，且具有向内延伸的多个引线38。如下所述，空腔36的尺寸和形状被设计成接收一芯片踏板。在所示实施例中，通过拉杆40限定引线框部分34的周长，引线38自拉杆40延伸。尽管所示的引线38长度相等，但是引线38的长度及宽度可改变。例如，用于电源及接地的引线较信号引线更宽且更短。第一引线框面板32具有一预定的第一厚度，例如0.2mm，该厚度对半导体引线框来说是一常规尺寸。
第一引线框面板32也包括沿着第一引线框面板32的外周长形成的第一配合结构42。在目前的较佳实施例中，第一配合结构42包括已经在引线框面板32上蚀刻或切割的一系列槽。下文将更详细说明第一配合结构42的用途。第一引线框面板32也可包括用以帮助将第一引线框面板32与第二引线框面板(图3)对齐的多个标记或孔44。可在面板32中蚀刻，冲孔或切割上述标记或孔44。
参见图3，图中示出了根据本发明的第二引线框面板46的俯视平面图。第二引线框面板46包括一第二引线框部分48的阵列。与图2所示的第一引线框面板相同，第二引线框面板46是3 x 3阵列，但通常其尺寸和形状被设计成与第一引线框面板32匹配。第二引线框部分48包括一芯片踏板50。第二引线框面板46的尺寸和形状被设计成与第一引线框面板32匹配，以便在空腔36内接收芯片踏板50且将芯片踏板50与引线38间隔开。但是，如参考图1所讨论的那样，芯片踏板50的尺寸和形状被设计成接收一特定的半导体芯片，例如芯片22。
第一及第二引线框面板32及46最好由一块导电金属，金属合金或具有良好导热性的电镀金属形成，例如铜或电镀铜。尽管第一及第二引线框面板32及46最好由同一种材料形成，但这并不是必须的。可通过冲压法形成引线框面板32及46，但是，对于更为复杂及较高密度的引线框来说，最好用化学蚀刻方法。正如本领域的技术人员所了解的那样，蚀刻方法使用一布线图掩膜限定引线框的详细图案，然后蚀去该金属的未遮蔽部分。如果存在非电镀区域，使用一电镀掩膜以遮蔽非电镀区域，然后通过一电镀方法给未遮蔽部分镀上金属层。在方法之间进行冲洗及清洗步骤。这种掩膜、蚀刻、电镀、冲洗及清洗方法为本领域的技术人员所了解。
第二引线框面板46也具有一预定的第二厚度。在下述实施例中，芯片踏板50不仅用以支持芯片，而且充当一散热器。因此，对于这些实施例，较佳的是形成相对较厚的第二引线框面板。例如，第二预定厚度应该较第一预定厚度厚，且最好是第一引线框面板32厚度的两倍或更多。在一个实施例中，第二引线框面板具有一约为0.5mm的厚度。芯片踏板50可与拉杆52相互连接。自面板46的外周长延伸的外部拉杆54可具有一在自较宽部分的锥形之后的狭窄部分，但这不是必须的。
第二引线框面板46最好也包括沿其外直径形成的第二配合结构56，与第一引线框面板32的第一配合结构42配合。在目前的较佳实施例中，第二配合结构56包括通过化学蚀刻在面板46中形成的一系列的脊或埂。第二引线框面板46也包括可与第一引线框面板32中上述孔44对齐的多个标记或孔58。这些标记或孔58可在面板46中通过蚀刻，冲孔或切割形成。
当第一及第二引线框面板32及46叠在一起时，即当将第一引线框面板32叠到第二引线框面板46上时，埂56插入槽42中，且上述芯片踏板50被相应的空腔36接收。第一及第二配合结构42及56的用途是在压模或封装过程中防止树脂或模塑料渗出，这将在下文中予以详细说明。
参考图4A-4F，图中示出了形成导体器件的各个阶段的剖面图，以说明一种形成根据本发明的一实施例的双规引线框半导体器件的方法。图4示出了具有多个第一引线框部分62的第一引线框面板60(在该实例中，示出了两个)。每个第一引线框部分62具有限定一空腔64的周长及自周长向内延伸的多个引线66。第一引线框面板60具有第一及第二面68及70以及一预定的第一厚度。如前所述，第一引线框面板70最好具有一约0.2mm的厚度。第一引线框面板60还包括沿着其外周长的第一配合结构。在目前的较佳实施例中，第一配合结构是一在第一引线框面板60的周长的周围形成的槽72。可通过切割，冲压或蚀刻形成槽72。图中展示的槽72具有锥形。但是，上述面可以是垂直的。
图4B示出了用于第一引线框面板60的第一面68的黏合剂74。黏合剂74最好包括一胶带，例如掩膜胶带。黏合剂74用于将第二引线框面板固定到第一引线框面板60。同时，当粘附剂74包括掩膜胶带时，该掩膜胶带帮助控制树脂渗出。
图4C示出了第二引线框面板76。该第二引线框面板76包括多个第二引线框部分78(在此例中为两个，与第一引线框面板60情况相同)。每个第二引线框部分78包括具有第一及第二表面82及84的芯片踏板80及第二预定的厚度。第二厚度较佳的大于第一厚度，且在一实施例中，该第二预定的厚度约为0.5mm。沿着第二引线框面板76的外周长形成第二配合结构。第二配合结构被设计成与第一配合结构(槽72)配合。在目前的较佳实施例中，第二配合结构是一埂86。埂86的尺寸和形状适合于装配在槽72(见图4F)内。可以通过切割或化学蚀刻形成埂86。例如，如果第二引线框面板76是由具有约0.5mm厚度的金属形成，则可切割或蚀刻该边缘以形成埂82。
参见图4D，将多个半导体芯片88固定到芯片踏板80的相应第二表面。图4D展示了一个固定的芯片88.下一步是将另一芯片固定到另一芯片踏板。通过如环氧树脂的黏合剂可将芯片88固定到芯片踏板80上，但最好是通过例如焊锡膏的导热黏合剂将其固定.本领域的技术人员应了解，芯片88在其暴露的表面上包括多个焊盘.
在将芯片88固定到芯片踏板80后，将第一及第二引线框面板60及76叠在一起.即，如图4E所示，将第二引线框面板76叠放到第一引线框面板60上，以使上述芯片踏板80的第一表面被接收于相应空腔64内且接触粘附剂74，且第一及第二配合结构彼此配合.因此，埂86被接收在槽72内且接触粘附剂74。在目前的较佳实施例中，将第一及第二引线框面板60及76彼此电绝缘，且由此使第一及第二引线框部分62及78彼此电绝缘.
在固定引线框面板60及76后，利用多个金属丝90将88的芯片焊盘与相应的第一引线框部分62的多个引线66的各个引线电连接.如图4F所示，通过引线焊接方法可将金属丝90连接到上述引线66及芯片焊盘.如图4G所示，在引线焊接后，在第二引线框面板76的第二表面、芯片88及金属丝90上方形成一模塑料或密封物92。第一及第二配合结构的槽72及埂86防止在压模过程中树脂渗出。
然后，通过进行将多个第一及第二引线框部分62及78从引线框面板60及76中分开的分离操作形成各个封装的器件.例如，可沿着虚线A-A、B-B及C-C切割面板60及76以此形成单个器件.可在分离之前或之后将黏合剂或掩膜胶带74从第一引线框面板60的第一面68及第二引线框面板76的第一表面82移去以此暴露上述引线66及第二引线框部分78的第一表面82。
现在参见图5，图中示出了根据本发明的一实施例的具有两个芯片102及104的双规引线框封装的器件100。将两芯片102及104固定到第一引线框部分108的相对厚的芯片踏板106，而器件100的引线110较该第一引线框部分的芯片踏板106薄。厚芯片踏板106可以作为散热器，消散芯片102及104生成的热量。最好使芯片踏板106与引线110隔离.可以看出，引线110可为各种期望的长度(及宽度).利用金属丝114将引线110连接到芯片102及104上的盘112。通过传统的引线焊接方法可将金属丝114固定到垫112及引线114上。在芯片102及104、第一引线框108的顶面、金属丝114及引线110上方形成密封物116.暴露引线110的底面(未图示)以此允许器件100与其他器件或一PCR连接.又在底面上暴露上述芯片踏板(散热器)106以此允许良好的热消散.双规引线框，多芯片封装器件允许较高I/O密度，仍提供良好的电性能.
本发明的双规引线框设计提供一较厚踏板及较薄的I/O接线端.提供较薄的接线端允许更精确的节距及更好的尺寸控制.对于切割型的QFN封装，铜或金属引线框材料的量及厚度影响切割分离方法的质量.仅在功能上必须的地方使用厚的铜或金属材料，而较薄的金属用于非关键区域，例如引线框接头，如此大大减小金属切削的量。此外，在芯片焊接固定方法中，在引线焊接之前具有分离的踏板及引线接头允许引线接头保持清洁且免除焊接过程的污染，带来更可靠的引线结合.
本发明较佳实施例的描述仅是为了展示和说明，但并非意在限制本发明的形式。本领域的技术人员应了解，在不脱离本发明的精神和范围的前提下，可对上述实施例作出修改.例如，可以形成具有两个以上部分的引线框，譬如具有由两个或更多构件形成的芯片踏板.因此，应当理解，本发明并不限于揭示的特定实施例，而是包括由所附权利要求书所限定的本发明的精神和范围内的修改.

Claims (20)

1.一种用于半导体器件的引线框，该引线框包括：
第一引线框部分，其具有一限定一空腔的周长及自周长向内延伸的多个引线，其中所述第一引线框部分具有0.2mm的第一厚度；及
固定到所述第一引线框部分的第二引线框部分，该第二引线框部分具有一接收于所述第一引线框部分的空腔内的芯片踏板，其中所述第二引线框部分具有0.5mm的第二厚度。
2.根据权利要求1的引线框，其中所述第一及第二引线框部分由金属或金属合金形成。
3.根据权利要求2的引线框，其中所述第一及第二引线框部分由铜形成。
4.根据权利要求1的引线框，其中所述第一及第二引线框部分彼此电绝缘。
5.一种用于半导体器件的引线框，该引线框包括：
第一引线框部分，其具有一限定一空腔的周长及自周长向内延伸的多个引线，其中所述第一引线框部分具有0.2mm的第一厚度；
固定到所述第一引线框部分的第二引线框部分，该第二引线框部分具有一接收于所述第一引线框部分的空腔内的芯片踏板，其中所述第二引线框部分具有0.5mm的第二厚度；及
其中所述第一及第二引线框部分由铜形成且彼此电绝缘。
6.一种半导体器件，其包括：
第一引线框部分，具有围绕一空腔的多个引线，其中所述第一引线框部分具有0.2mm的第一厚度；
固定到所述第一引线框部分的第二引线框部分，该第二引线框部分具有接收于所述第一引线框部分的空腔内的芯片踏板，其中所述第二引线框部分具有0.5mm的第二厚度；
利用高温芯片固定方法固定到所述芯片踏板上的集成电路芯片，其位于所述空腔内且被多个引线围绕，所述芯片包括多个芯片焊盘；及
将各个芯片焊盘与相应的引线电连接的多个金属丝。
7.根据权利要求6的半导体器件，还包括一覆盖所述集成电路芯片的顶面、上述金属丝、及上述引线的顶面的密封物，其中至少上述引线的一个底面及该第二引线框部分的一个底面暴露在外。
8.根据权利要求7的半导体器件，其中所述第一及第二引线框部分由铜形成。
9.根据权利要求6的半导体器件，其中所述第一及第二引线框部分彼此电绝缘。
10.一种半导体器件，包括：
第一金属引线框部分，具有围绕一空腔的多个引线，其中所述第一引线框部分具有0.2mm的第一厚度；
第二金属引线框部分，固定到所述第一引线框部分并与其彼此电绝缘，所述第二引线框部分具有一接收于所述空腔内的芯片踏板，其中所述第二引线框部分具有0.5mm的第二厚度；
利用高温芯片固定方法固定到所述芯片踏板的集成电路芯片，其位于所述空腔内且被多个引线围绕，该芯片包括多个芯片焊盘；
将各个芯片焊盘与相应的引线电连接的多个金属丝；及
一覆盖该集成电路芯片的顶面、上述金属丝、及上述引线的顶面的密封物，其中至少上述引线的一个底面及该第二引线框的一个底面暴露在外。
11.根据权利要求10的半导体器件，其中所述第一及第二引线框部分由铜形成。
12.一种封装半导体器件的方法，包括以下步骤：
提供第一引线框部分，该部分具有一限定一空腔的周长及自周长向内延伸的多个引线，其中所述第一引线框部分具有第一及第二面及0.2mm的第一厚度；
将黏合剂施于所述第一引线框部分的第一面；
提供第二引线框部分，它包括具有第一及第二表面及0.5mm的第二厚度的芯片踏板；
利用高温芯片固定方法将半导体芯片固定到所述芯片踏板的第二表面，其中所述半导体芯片在其表面上具有多个焊盘；
将所述第二引线框部分叠层在所述第一引线框部分上以使所述芯片踏板的第一表面被接收在所述空腔内且接触粘附剂；
利用多个金属丝将上述多个芯片焊盘与上述多个引线的相应引线电连接；
在所述第二引线框部分的第二面、所述半导体芯片、及上述电连接的上方形成模塑料；及
从所述第一引线框部分的第一面及所述第二引线框部分的第一表面中除去黏合剂，以使第二引线框部分的第一表面及引线暴露在外。
13.根据权利要求12的封装半导体器件的方法，其中所述黏合剂的施加步骤包括将胶带施加于所述第一引线框部分的第一面。
14.根据权利要求12的封装半导体器件的方法，其中所述芯片固定步骤包括利用焊锡膏将芯片固定到芯片踏板。
15.根据权利要求12的封装半导体器件的方法，其中所述芯片固定步骤包括利用环氧树脂将芯片固定到芯片踏板。
16.一种封装多个半导体器件的方法，包括以下步骤：
提供第一引线框面板，所述第一引线框面板具有多个第一引线框部分，每个第一引线框面部分具有一限定一空腔的周长及自周长向内延伸的多个引线，其中所述第一引线框部分具有第一及第二面及0.2mm的第一厚度；
沿着所述第一引线框面板的一外周长形成第一配合结构；
将黏合剂施加于所述第一引线框面板的第一面；
提供包括多个第二引线框部分的第二引线框面板，每个第二引线框部分包括一具有第一及第二表面及0.5mm的第二厚度的芯片踏板；
沿着所述第二引线框面板的一外周长形成第二配合结构；
利用高温芯片固定方法将多个半导体芯片固定到所述芯片踏板的上述各个第二表面，其中每个半导体芯片在其表面上具有多个焊盘；
将所述第二引线框面板叠层在所述第一引线框面板上，以使所述芯片踏板的第一表面被接收于相应的空腔内且接触粘附剂，且所述第一及第二配合结构彼此配合；
利用多个金属丝将所述芯片的多个芯片焊盘与上述各个第一引线框部分的多个引线的相应引线电连接；
在所述第二引线框面板的第二表面、所述芯片及上述电连接的上方形成模塑料；及
进行将上述多个第一及第二引线框部分从引线框面板中分开的分离操作，从而形成单个的封装器件。
17.根据权利要求16的封装多个半导体器件的方法，还包括从所述第一引线框面板的第一面及从所述第二引线框部分的第一表面中除去黏合剂，以使所述第二引线框部分的第一表面及引线暴露在外。
18.根据权利要求16的封装多个半导体器件的方法，其中所述第一配合结构包括一系列槽且所述第二配合结构包括一系列埂，其中当叠层第一及第二引线框面板时，将上述系列埂装配在上述系列槽的相应槽内。
19.根据权利要求18的封装多个半导体器件的方法，其中在模塑料形成步骤中，上述的槽及埂结构防止模塑料渗出。
20.一种半导体器件，包括：
第一金属引线框部分，具有围绕一空腔的多个引线，其中所述第一引线框部分具有0.2mm的第一厚度；
固定到所述第一引线框部分且与其彼此电绝缘的第二金属引线框部分，所述第二引线框部分具有一对接收于所述空腔内的相邻芯片踏板，其中所述第二引线框部分具有0.5mm的第二厚度；
利用高温芯片固定方法固定到各个芯片踏板的第一及第二集成电路芯片，所述芯片位于所述空腔内且被多个引线围绕，每个第一及第二芯片包括多个芯片焊盘；
将所述第一及第二芯片的各个芯片焊盘与相应的引线电连接的多个金属丝；及
一覆盖该第一及第二集成电路芯片的顶面、金属丝及引线的顶面的密封物，其中引线的至少底面及第二引线框暴露在外。
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US11/043,224 US7033866B2 (en) 2003-07-15 2005-01-26 Method for making dual gauge leadframe

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US6917097B2 (en) 2005-07-12

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