CN100490094C - Ion implantation in use for reducing I/O NMOS inverse short-channel effect - Google Patents
Ion implantation in use for reducing I/O NMOS inverse short-channel effect Download PDFInfo
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- CN100490094C CN100490094C CNB2003101092271A CN200310109227A CN100490094C CN 100490094 C CN100490094 C CN 100490094C CN B2003101092271 A CNB2003101092271 A CN B2003101092271A CN 200310109227 A CN200310109227 A CN 200310109227A CN 100490094 C CN100490094 C CN 100490094C
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- polysilicon
- nmos
- ion
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- silica
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Abstract
The technical procedure includes following steps: (1) after ion implantation for P channel and APT, depositing 2000 Angstrom polysilicon; (2) polysilicon at tube grid area is removed by using I/O NMOS LDD photo etching plate; (3) depositing 700 Angstrom silicon oxide; (4) corroding silicon oxide 800 Angstrom so as to form two pieces of inside wall in width 700 Angstrom, and ion implantation is carried out under threshold voltage is adjusted; (5) removing polysilicon and oxide, normal technical flow is continued, depositing grid oxidizing layer. Advantages are: comparing with traditional channel full implantation, the disclosed procedure provides even distribution of boron and eliminates peak shaped distribution at two ends of channel through selective boron implantation.
Description
Technical field
The utility model relates to a kind of ion injection that is used to reduce the anti-short-channel effect of I/O NMOS, is meant a kind of selectivity channel ion injection that is used to reduce the anti-short-channel effect of I/O NMOS especially.
Background technology
Anti-short-channel effect (RSCE) becomes more and more important in the sub-micron nmos device.Because low doping source/leakage (LDD) and source/leakage (SD) ion inject formed damage, in heat treatment process, form the transient enhanced diffusion (TED) of boron, cause the peak shape of raceway groove both sides boron to distribute, thereby make the threshold voltage of device with long the reducing and increase of grid.The threshold voltage that RSCE causes is easy to form the drift of device property because technology rises and falls with the long inhomogeneities that distributes of grid, can cause the acute variation of short channel device threshold voltage such as the error of grid etching.In order to improve the fault-tolerance of technology, need in I/O NMOS, reduce RSCE, make threshold voltage distribution more smooth.
Summary of the invention
The object of the present invention is to provide a kind of selective local channel ion to I/O NMOS to inject, it can reduce anti-short-channel effect, and forming uniformly, boron distributes.
The present invention also aims to provide a kind of transistor component that can adopt the selectivity channel ion to inject.
Adopt the selectivity ion to inject to the nmos device raceway groove, form raceway groove boron distribution more uniformly, thereby the distribution that reduces threshold voltage effectively rises and falls.
The step that the local channel ion of I/O NMOS selectivity ion is injected of the present invention is as follows:
The first step, after P raceway groove and the injection of APT ion, the deposit polysilicon;
Second step, adopt I/O NMOS LDD photoetching carving to remove the polysilicon in nmos pass transistor grid region, form groove;
The 3rd step, silicon oxide deposition;
The 4th step, adopt the wet etching silica, form two inside wall of certain width, the ion of adjusting threshold voltage subsequently injects, wherein remove in the wet etching and be positioned on the polysilicon surface and the silica of channel bottom, and keep the silica that is positioned at trenched side-wall;
The 5th step, remove polysilicon and silica, continue normal technological process, carry out the gate oxide deposit.
Two the transistor device of corresponding the object of the invention, it comprises P type substrate, the polysilicon layer and the raceway groove window thereof of covering it on, the inboard of polysilicon has the inside wall that is formed by silicon oxide deposition and etching.
By above-mentioned setting, compared with prior art, the invention has the beneficial effects as follows: inject by the selectivity ion, reduce the RSCE in the NMOS manufacturing process, make threshold voltage distribution more even, adopt the present invention not need to increase new reticle, and hot carrier's effect improves, source-and-drain junction electric capacity almost remains unchanged.Improved the operational characteristic of NMOS pipe.
Description of drawings
Fig. 1 is the processing step that selectivity channel ion of the present invention injects.
Fig. 2 is a cross direction profiles of injecting boron in the raceway groove of back with the I/O NMOS selectivity channel ion of TCAD simulation.
Fig. 3 is that threshold voltage is with the long variation contrast of grid in new technology and the common process after injecting with the I/O NMOS selectivity channel ion that TCAD simulates.
Fig. 4 is the device that selectivity channel ion of the present invention injects I/O NMOS.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
Technology performing step of the present invention is as follows:
See also shown in Figure 1, selectivity channel ion injection technology at first after P raceway groove and APT ion inject, deposit
Polysilicon forms a polysilicon layer above monocrystalline substrate;
Second step, adopt I/O NMOS LDD photoetching carving to remove the polysilicon in nmos pass transistor grid region, form groove;
The 3rd step, silicon oxide deposition
, in the polysilicon layer zone and the surface in the zone gone of photoetching carving form a silicon oxide layer;
The 4th step, adopt the wet etching silica, remove and be positioned on the polysilicon surface and the silica of channel bottom, and keep the silica that is positioned at trenched side-wall, thereby form width in the zone that the photoetching carving is gone be
Two inside wall, the ion of adjusting threshold voltage subsequently as required injects;
At last, remove polysilicon and silica, continue normal technological process, carry out the gate oxide deposit.
Adopt the cross direction profiles of boron ion in the raceway groove in the I/O nmos pass transistor after the above step to inject evenly, the more important thing is that the peak shape of having eliminated the raceway groove two ends distributes than conventional raceway groove is complete.The contrast of consulting boron distribution curve in the raceway groove of new technology shown in Figure 2 and common process distributes at distance raceway groove center line 0.125 to 0.175 unit distance place two peaks shape originally and is effectively eliminated as can be seen.Like this, threshold voltage distribution is more even, has improved the electric property of NMOS pipe.See also new technology shown in Figure 3 and common process I/O NMOS threshold voltage as can be seen, after adopting new technology, can reduce the fluctuating of threshold voltage with channel length with the long change curve comparison diagram of grid.And do not change because anti-break-through ion injects, short-channel effect does not degenerate in new technology.
The selectivity channel ion that employing of the present invention reduces the anti-short-channel effect of I/O NMOS injects transistor device, it comprises P type substrate, and the polysilicon layer and the raceway groove window thereof that cover on it: the inboard of polysilicon has the inside wall that is formed by silicon oxide deposition and etching.
In sum, the present invention can finish goal of the invention, make the I/O nmos pass transistor that adopts selective local channel ion method for implanting of the present invention to make to form and more evenly be the boron distribution, thereby threshold voltage distribution is more even.Not needing among the present invention increases new reticle, and hot carrier's effect improves, and source/drain junction electric capacity is almost constant.
Claims (4)
1, the method injected of a kind of local channel ion of selectivity ion that is used to reduce the anti-short-channel effect of I/O NMOS, its operating procedure is:
The first step, after P raceway groove and the anti-break-through ion injection of APT, the deposit polysilicon;
Second step, adopt I/O NMOS LDD photoetching carving to remove the polysilicon in nmos pass transistor grid region, form groove;
The 3rd step, silicon oxide deposition;
The 4th step, adopt the wet etching silica, form two inside wall of certain width, the ion of adjusting threshold voltage subsequently injects, wherein remove in the wet etching and be positioned on the polysilicon surface and the silica of channel bottom, and keep the silica that is positioned at trenched side-wall;
The 5th step, remove polysilicon and silica, continue normal technological process, carry out the gate oxide deposit.
2, the method for claim 1 is characterized in that: the deposit polysilicon is in the first step
3, method as claimed in claim 2 is characterized in that: silicon oxide deposition in the 3rd step
4, the method for claim 1 is characterized in that: the inside wall width that forms in described the 4th step is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101092271A CN100490094C (en) | 2003-12-10 | 2003-12-10 | Ion implantation in use for reducing I/O NMOS inverse short-channel effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101092271A CN100490094C (en) | 2003-12-10 | 2003-12-10 | Ion implantation in use for reducing I/O NMOS inverse short-channel effect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1627488A CN1627488A (en) | 2005-06-15 |
| CN100490094C true CN100490094C (en) | 2009-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101092271A Expired - Fee Related CN100490094C (en) | 2003-12-10 | 2003-12-10 | Ion implantation in use for reducing I/O NMOS inverse short-channel effect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100442463C (en) * | 2005-09-07 | 2008-12-10 | 上海华虹Nec电子有限公司 | Method for improving voltage distribution of component threshold value |
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| TR01 | Transfer of patent right |
Effective date of registration: 20171213 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090520 Termination date: 20181210 |