CN100489772C - Stream data-oriented resequencing access storage buffering method and device - Google Patents
Stream data-oriented resequencing access storage buffering method and device Download PDFInfo
- Publication number
- CN100489772C CN100489772C CNB2007100345774A CN200710034577A CN100489772C CN 100489772 C CN100489772 C CN 100489772C CN B2007100345774 A CNB2007100345774 A CN B2007100345774A CN 200710034577 A CN200710034577 A CN 200710034577A CN 100489772 C CN100489772 C CN 100489772C
- Authority
- CN
- China
- Prior art keywords
- address
- buffer cell
- data
- reorder
- half buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a resequencing visit deposit buffer method and device facing to cluster data, which is to set address resequencing buffer module between address generator and bottom memorizer, and data returning buffer module between address generator and upper stream buffer module, the address resequencing buffer unit and data returning buffer module connect with control logic module. Address resequencing buffer module is used to regroup visit address from address generator, making the address recorded its internal elements continuous relatively. The data returning buffer module preserves data transmitted from the bottom memorizer in Burst Mode, the control logic module controls when to send the visit deposit request according to the features of visit and chooses some or all the elements of a certain unexpected transmission to return them into upper stream buffer module.
Description
Technical field
The present invention is mainly concerned with the microprocessor Design field, refers in particular to a kind of reorder memory access way to play for time and device towards flow data.
Background technology
The stream handle structure is a class is used the SIMD type that can efficiently handle at stream a processor structure.Stream is used bandwidth is had high requirements, and its data amount of having is big, continue to flow into and less characteristics such as reuse.The stream handle key process unit is the calculating group of a series of concurrent workings.It is handled unit and is stream (stream), stream has order isomorphic record (record) to form by some, what form record then is a series of relevant data elements (element), and one of them data element is a word, and the inner data element of record is deposited in storer continuously.The address production part is responsible for the stream with the unit of being recorded as in the superstructure is resolved into single data element sequence according to adapting to the parallel efficient algorithm of handling of calculating group, the memory scheduling buffer memory is responsible for converting thereof into the address sequence that is fit to visit DDR or DDR2 storer, for convenience of explanation, being referred to as DDR or DDR2 storer hereinafter is the DDR storer.
Current the most frequently used chip external memory is DDR DRAM, the important characteristic of DDR is exactly burst type (burst) transmission, it is by the fast access of a column access realization to a plurality of continuous data elements of current activation row, its burst-length is generally 2,4 and 8, that is to say that a memory access can be from storer by several data, this access mode provides very high handling capacity for continuous memory access.Therefore, if memory access stream address sequence is continuous block address sequence, the DDR storer can reach very high memory access efficient so.
Summary of the invention
The technical problem to be solved in the present invention just is: at the technical matters of prior art existence, but the invention provides a kind of by adopting a kind of reorder buffer method that the memory access sequence is resequenced according to memory access stream record length dynamic-configuration, make discrete memory access sequence serialization, optimize memory access, can improve reorder the memory access way to play for time and the device towards flow data of memory access efficient, expansion effective bandwidth simultaneously.
For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of memory access way to play for time that reorders towards flow data is characterized in that:
(1) between address generator and bottom storer, is provided with reorder buffer unit, address, between address generator and upper stream buffer cell, be provided with data and return buffer cell, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, it all is double buffering that reorder buffer unit, address and data are returned buffer cell, and described data are returned the data that buffer cell comprises two same structures and returned half buffer cell;
(2) record length, memory access pattern information are sent to the steering logic unit that links to each other with reorder buffer unit, address the work of stream controller enabling address generator the time, the rule of fill address reorder buffer unit is determined in the steering logic unit according to stream length, record length, memory access pattern information;
(3) according to above-mentioned rule half buffer cell that reorders of an address in the reorder buffer unit, address is filled in, when filling in when finishing, stop this address half buffer cell that reorders to receive and to fill in operation and to send the memory access address that chooses, another address request that half buffer cell can the receiver address generator produces of reordering this moment to lower floor;
(4) for read operation load, after the memory access address sends, the data return signal of steering logic unit device to be stored is effective, in case burst is effective for the transmission of bottom memory burst, just data are sent to corresponding data and return the M[i of half buffer cell] [0] number position, it is capable the 0th column position of i that data are returned half buffer memory, 0≤i≤burst length-1 wherein, burst length is the length of primary memory burst type transmission, next time then with deposit data at M[i] [1] number position, it is capable the 1st column position of i that data are returned half buffer memory, 0≤i≤burstlength-1 wherein, burst length are the length of primary memory burst type transmission, by that analogy, finish up to n burst transmission data are all filled in, wherein n is corresponding with CLUSTER number and OFFSET register number; After above process is finished, these data are returned half buffer cell and have been filled in and finish, can send the buffering readable signal this moment to the upper stream buffer cell, the steering logic unit is sent to the upper strata buffer cell according to the address corresponding data that address selection in half buffer cell returns in half buffer cell in data that reorders, when data return data in half buffer cell all read finish after, discharge reorder half buffer cell and data of this address and return half buffer cell;
(5) for write operation Store, after certain memory access address sends, being reordered in the address, the corresponding data of these row send to the bottom storer successively in the matrix of half buffer cell, that is to say the several number certificate of an address to being listed as, by that analogy, all data all send and finish in half buffer cell is reordered in this address, discharge this address half buffer cell that reorders.
Reorder buffer unit, described address comprises the address of two same structures half buffer cell that reorders, each address half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each address half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically; The described buffering of writing is by the row major principle, promptly with M[0 in proper order] [0], M[0] [1], M[0] [n-1], M[1] [0] ... M[1] [n-1],, M[7] and [0], M[7] order of [n-1], filling in the record length that whether finishes on current memory access stream each time and decide, is not that half buffer cell that at every turn all will be reordered in the address fills up just to lower floor's transmission memory access request:
(1), when stream length 〉=8, the memory burst transmission burst length request of bottom is made as 8, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 8 in the address, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being filled in last reclen%8 element of current each record if reclen%8 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%8 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%8 represents that record length presses 8 deliverys;
(2), when 4≤during stream length＜8, the request of bottom memory burst transmission burst length is made as 4, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 4 in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤3,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%4 element of current each record if reclen%4 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%4 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%4 represents that record length presses 4 deliverys;
(3), when 2≤during stream length＜4, the request of bottom memory burst transmission burst length is made as 2, reorder and send the memory access request to bottom after half buffer cell column direction fills up two in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤1,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%2 element of current each record if reclen%2 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%2 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%2 represents that record length presses 2 deliverys;
(4), when stream length=1, under the pattern of striding, want special consideration, steplength is that the request of 1 o'clock bottom memory burst transmission burst length is made as 4, half buffer cell M[0 reorders in the address] [j] number position fill in and finish after just to lower floor transmission memory access request, 0≤j≤n-1 wherein is in this case as long as send M[0] address of [0] number position is just passable; When steplength was other situations, it was the same as lower floor's transmission memory access request to take to catch up with the method for stating step (3) description.
A kind of access buffering mechanism that reorders towards flow data, it is characterized in that: it comprises that reorder buffer unit, address, data return buffer cell and steering logic unit, be arranged at reorder buffer unit, address between address generator and the bottom storer and be used for the memory access address sequence that address generator produces is reconfigured, make write down inner element separately the address relatively continuously; Being arranged at data between address generator and the upper stream buffer cell returns buffer cell and is used for preserving the data that bottom memory burst formula is transmitted out, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, and the steering logic unit is according to when outwards sending the memory access request when time characteristics control of visit, returning the some or all of element of selecting certain burst type transmission the buffer cell from data and send back in the upper stream buffer cell and work.
Reorder buffer unit, described address comprises the address of two same structures half buffer cell that reorders, each address half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically.
The described buffering of writing is by the row major principle, promptly with M[0 in proper order] [0], M[0] [1], M[0] [n-1], M[1] [0] ... M[1] [n-1],, M[7] and [0], M[7] order of [n-1], fill in the record length that whether finishes on current memory access stream each time and decide, be not all half buffer cell that reorders will be filled up just to send the memory access request to lower floor at every turn:
(1), when stream length 〉=8, the memory burst transmission burst length request of bottom is made as 8, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 8 in the address, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being filled in last reclen%8 element of current each record if reclen%8 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%8 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%8 represents that record length presses 8 deliverys;
(2), when 4≤during stream length＜8, the request of bottom memory burst transmission burst length is made as 4, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 4 in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤3,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%4 element of current each record if reclen%4 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%4 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%4 represents that record length presses 4 deliverys;
(3), when 2≤during stream length＜4, the request of bottom memory burst transmission burst length is made as 2, reorder and send the memory access request to bottom after half buffer cell column direction fills up two in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤1,0≤j≤n-1, the request address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%2 element of current each record if reclen%2 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%2 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%2 represents that record length presses 2 deliverys;
(4), when stream length=1, under the pattern of striding, want special consideration, steplength is that the request of 1 o'clock bottom memory burst transmission burst length is made as 4, half buffer cell M[0 reorders in the address] [j] number position fill in and finish after just to lower floor transmission memory access request, 0≤j≤n-1 wherein is in this case as long as send M[0] address of [0] number position is just passable; When steplength was other situations, it was the same as lower floor's transmission memory access request to take to catch up with the method for stating step (3) description.
Described data are returned the data that buffer cell comprises two same structures and are returned half buffer cell, and each data is returned half buffer cell and had 8 * n data word cell.
Compared with prior art, advantage of the present invention just is:
1, the hardware implementation complexity is low.Most important parts are two groups of corresponding buffer structures among the present invention; Steering logic then mainly is the pairing of control to address date between the read-write of each buffering and the buffering, does not relate to very complicated logic.
2, increase substantially the memory access efficient of stream handle, increased effective bandwidth.Adopt memory access sequence rearrangement technology of the present invention, can effectively utilize the record organization characteristic of stream and the memory access characteristic of current main flow storer, improve the memory access data user rate, increase effective bandwidth.Can solve the address sequence that the address production part generates in the stream handle and directly send into the low problem of throughput that the bottom memory controller brings,
Description of drawings
Fig. 1 is the logical framework synoptic diagram that reorders of the present invention;
Fig. 2 is that half buffering and the data of reordering of the present invention are returned the logical organization synoptic diagram of buffering;
Fig. 3 is a workflow synoptic diagram of the present invention.
Embodiment
Below with reference to the drawings and specific embodiments the present invention is described in further details.
Referring to shown in Figure 3, a kind of memory access way to play for time that reorders towards flow data of the present invention the steps include:
(1) between address generator and bottom storer, is provided with reorder buffer unit, address, between address generator and upper stream buffer cell, be provided with data and return buffer cell, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, and it all is double buffering that reorder buffer unit, address and data are returned buffer cell;
(2) information such as record length, memory access pattern are sent to the steering logic unit that links to each other with reorder buffer unit, address the work of stream controller enabling address generator the time, the rule of reorder buffer is determined to fill in the steering logic unit according to these information;
(3) according to above-mentioned rule half buffer cell that reorders of an address in the reorder buffer unit, address is filled in, when filling in when finishing, stop this address half buffer cell that reorders to receive and to fill in operation and to send the memory access address that chooses, another address request that half buffer cell can the receiver address generator produces of reordering this moment to lower floor;
(4) concerning with read operation load operation, after the memory access address sends, the steering logic unit waits for that the data return signal of storer is effective, in case bottom burst transmission effectively, just data are sent to corresponding data and return the M[i of half buffer cell] [0] (0≤i≤burst length-1, burst length is the length of primary memory burst type transmission) number position, next time then with deposit data at M[i] [1] (0≤i≤burst length-1, burst length is the length of primary memory burst type transmission) number position, by that analogy, finish up to n burst transmission data are all filled in, wherein n is corresponding with CLUSTER number and OFFSET register number; After above process is finished, these data are returned half buffer cell and have been filled in and finish, can send the buffering readable signal this moment to the upper stream buffer cell, the corresponding data that the steering logic unit returns in half buffer cell in data according to the address selection in half buffer cell that reorders is sent to the upper strata buffer cell, when data return data in half buffer cell all read finish after, discharge these reorder half buffer cell and data and return half buffer cell;
(5) operate for write operation Store, after certain memory access address sends, the data that these row are corresponding in the matrix of half buffer cell that reorders to be sent to the bottom storer successively, that is to say the several number certificate of an address to being listed as, by that analogy, all data all send and finish in this reorders half buffer cell, discharge this half buffer cell that reorders.
Wherein, reorder buffer unit, address comprises the address of two same structures half buffer cell that reorders, each address half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each address half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically; The described buffering of writing is by the row major principle, promptly with M[0 in proper order] [0], M[0] [1], M[0] [n-1], M[1] [0] ... M[1] [n-1],, M[7] and [0], M[7] order of [n-1], filling in the record length that whether finishes on current memory access stream each time and decide, is not that half buffer cell that at every turn all will be reordered in the address fills up just to lower floor's transmission memory access request:
(1), when stream length 〉=8, the memory burst transmission burst length request of bottom is made as 8, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 8 in the address, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being filled in last reclen%8 element of current each record if reclen%8 is not equal to zero and reorder in the address, half buffer cell column direction just should send the memory access request to lower floor after filling in reclen%8 element as long as reorder in the address, and wherein reclen%8 represents that record length presses 8 deliverys;
(2), when 4≤during stream length＜8, the request of bottom memory burst transmission burst length is made as 4, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 4 in the address, promptly buffering has only been filled in M[i] [j] (unit of position of 0≤i≤3,0≤j≤n-1).Request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%4 element of current each record if reclen%4 is not equal to zero and reorder in the address, half buffer cell column direction just should send the memory access request to lower floor after filling in reclen%4 element as long as reorder in the address, and wherein reclen%4 represents that record length presses 4 deliverys;
(3), when 2≤during stream length＜4, the request of bottom memory burst transmission burst length is made as 2, reorder and send the memory access request to bottom after half buffer cell column direction fills up two in the address, promptly buffering has only been filled in M[i] [j] (0≤i≤1, the unit of position of 0≤j≤n-1), request address are the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%2 element of current each record if reclen%2 is not equal to zero and reorder in the address, half buffer cell column direction just should send the memory access request to lower floor after filling in reclen%2 element as long as reorder in the address, and wherein reclen%2 represents that record length presses 2 deliverys;
(4), when stream length=1, under the pattern of striding, want special consideration, steplength is that the request of 1 o'clock bottom memory burst transmission burst length is made as 4, half buffer cell M[0 reorders in the address] and [j] (as long as 0≤j≤n-1) just can send the memory access request to lower floor after filling in number position and finishing, in this case transmission M[0] address of [0] number position is just passable; When steplength is other situations, can take to send the memory access request to lower floor with previously described method is the same.
As depicted in figs. 1 and 2, a kind of access buffering mechanism that reorders of the present invention towards flow data, it comprises that reorder buffer unit, address, data return buffer cell and steering logic unit, be arranged at reorder buffer unit, address between address generator and the bottom storer and be used for the memory access address sequence that address generator produces is reconfigured, make write down inner element separately the address relatively continuously; The data that are arranged between address generator and the upper stream buffer cell are returned the data that buffer cell preservation bottom memory burst formula is transmitted out, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, and the steering logic unit is according to when outwards sending the memory access request when time characteristics control of visit, returning the some or all of element of selecting certain burst type transmission the buffering from data and send back in the upper stream buffer cell and work.The reorder buffer unit comprises half buffer cell that reorders of two same structures, each half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically.Data are returned buffering and reorder buffer is corresponding, also are made up of half buffering of two 8 * n, receive the data of being come out by the DDR burst transfer when its role is to the load operation, and it is not selected these data, directly deposits corresponding position.Control assembly is determined filling in rule, determine sending the opportunity of memory access address and the data in the load operation data returned in the buffering are selected of reorder buffer according to control information.Referring to shown in Figure 1, the module logic diagram that reorders in the embodiment of the invention.The module that reorders comprises following little module altogether: two half bufferings that reorder, two data are returned half buffering and are controlled the effectively steering logic of running of these bufferings.It all is the matrix structure of 8 * n in logic that half buffering and the data of reordering are returned half buffering, and steering logic can be filled in their mode according to the dynamic decision of the size of record length, and determines the opportunity and the mode of memory access according to the mode of filling in.The record storage inside continuity of upsetting by address generator is reconfigured to adapt to the accessing operation of bottom memory controller in the parts that reorder.Fig. 2 is that half buffering and the data of reordering of the present invention are returned the building-block of logic of buffering.Among Fig. 1 four and half buffering all is organized into the structure of matrix form in logic, actually can realize this logical organization by the saltus step of read-write pointer.The value of n depends on the number that calculates the group among the figure.That each accessing operation sends all is M[0] [j] (address of position of 0≤j≤n-1), in the pattern of striding record length be in 1 the special circumstances half buffering fill in have only M[0 after finishing] address of [0] position sends, this moment M[0] [j] (0≤j≤n-1) address of position is continuous in storage space.
Claims (6)
1, a kind of memory access way to play for time that reorders towards flow data is characterized in that:
(1) between address generator and bottom storer, is provided with reorder buffer unit, address, between address generator and upper stream buffer cell, be provided with data and return buffer cell, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, it all is double buffering that reorder buffer unit, address and data are returned buffer cell, and described data are returned the data that buffer cell comprises two same structures and returned half buffer cell;
(2) record length, memory access pattern information are sent to the steering logic unit that links to each other with reorder buffer unit, address the work of stream controller enabling address generator the time, the rule of fill address reorder buffer unit is determined in the steering logic unit according to stream length, record length, memory access pattern information;
(3) according to above-mentioned rule half buffer cell that reorders of an address in the reorder buffer unit, address is filled in, when filling in when finishing, stop this address half buffer cell that reorders to receive and to fill in operation and to send the memory access address that chooses, another address request that half buffer cell can the receiver address generator produces of reordering this moment to lower floor;
(4) for read operation load, after the memory access address sends, the data return signal of steering logic unit device to be stored is effective, in case burst is effective for the transmission of bottom memory burst, just data are sent to corresponding data and return the M[i of half buffer cell] [0] number position, it is capable the 0th column position of i that data are returned half buffer memory, 0≤i≤burst length-1 wherein, burst length is the length of primary memory burst type transmission, next time then with deposit data at M[i] [1] number position, it is capable the 1st column position of i that data are returned half buffer memory, 0≤i≤burstlength-1 wherein, burst length are the length of primary memory burst type transmission, by that analogy, finish up to n burst transmission data are all filled in, wherein n is corresponding with CLUSTER number and OFFSET register number; After above process is finished, these data are returned half buffer cell and have been filled in and finish, can send the buffering readable signal this moment to the upper stream buffer cell, the steering logic unit is sent to the upper strata buffer cell according to the address corresponding data that address selection in half buffer cell returns in half buffer cell in data that reorders, when data return data in half buffer cell all read finish after, discharge reorder half buffer cell and data of this address and return half buffer cell;
(5) for write operation Store, after certain memory access address sends, being reordered in the address, the corresponding data of these row send to the bottom storer successively in the matrix of half buffer cell, that is to say the several number certificate of an address to being listed as, by that analogy, all data all send and finish in half buffer cell is reordered in this address, discharge this address half buffer cell that reorders.
2, the memory access way to play for time that reorders towards flow data according to claim 1, it is characterized in that: reorder buffer unit, described address comprises the address of two same structures half buffer cell that reorders, each address half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each address half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically; What half buffer cell was reordered in described address writes buffering in proper order for by the row major principle, promptly with M[0] [0], M[0] [1], M[0] [n-1], M[1] [0] ... M[1] [n-1],, M[7] and [0], M[7] order of [n-1], filling in the record length that whether finishes on current memory access stream each time and decide, is not that half buffer cell that at every turn all will be reordered in the address fills up just to lower floor's transmission memory access request:
(1), when stream length 〉=8, the memory burst transmission burst length request of bottom is made as 8, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 8 in the address, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being filled in last reclen%8 element of current each record if reclen%8 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%8 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%8 represents that record length presses 8 deliverys;
(2), when 4≤during stream length＜8, the request of bottom memory burst transmission burst length is made as 4, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 4 in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤3,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%4 element of current each record if reclen%4 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%4 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%4 represents that record length presses 4 deliverys;
(3), when 2≤during stream length＜4, the request of bottom memory burst transmission burst length is made as 2, reorder and send the memory access request to bottom after half buffer cell column direction fills up two in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤1,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%2 element of current each record if reclen%2 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%2 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%2 represents that record length presses 2 deliverys;
(4), when stream length=1, under the pattern of striding, want special consideration, steplength is that the request of 1 o'clock bottom memory burst transmission burst length is made as 4, half buffer cell M[0 reorders in the address] [j] number position fill in and finish after just to lower floor transmission memory access request, 0≤j≤n-1 wherein is in this case as long as send M[0] address of [0] number position is just passable; When steplength is other situations, take with the method for step (3) description the same to lower floor's transmission memory access request.
3, a kind of access buffering mechanism that reorders towards flow data, it is characterized in that: it comprises that reorder buffer unit, address, data return buffer cell and steering logic unit, be arranged at reorder buffer unit, address between address generator and the bottom storer and be used for the memory access address sequence that address generator produces is reconfigured, make write down inner element separately the address relatively continuously; Being arranged at data between address generator and the upper stream buffer cell returns buffer cell and is used for preserving the data that bottom memory burst formula is transmitted out, reorder buffer unit, address returns buffer cell with data and links to each other with the steering logic unit, and the steering logic unit is according to when outwards sending the memory access request when time characteristics control of visit, returning the some or all of element of selecting certain burst type transmission the buffer cell from data and send back in the upper stream buffer cell and work.
4, the access buffering mechanism that reorders towards flow data according to claim 3, it is characterized in that: reorder buffer unit, described address comprises the address of two same structures half buffer cell that reorders, each address half buffer cell that reorders has 8 * n data word cell, wherein n is corresponding with the number of the number that calculates the group, OFFSET register, and each address half buffer cell that reorders is the matrix M [7] [n-1] of a 8 * n logically.
5, the access buffering mechanism that reorders towards flow data according to claim 4, what it is characterized in that described address reorders half buffer cell writes buffering in proper order for by the row major principle, promptly with M[0] [0], M[0] [1], M[0] [n-1], M[1] [0],, M[1] and [n-1] ... M[7] [0], M[7] order of [n-1], fill in the record length that whether finishes on current memory access stream each time and decide, be not that half buffer cell that at every turn all will be reordered in the address fills up just to lower floor's transmission memory access request:
(1), when stream length 〉=8, the memory burst transmission burst length request of bottom is made as 8, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 8 in the address, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1],, M[0] and storage addresses in [n-1] number position; When half buffer cell is being filled in last reclen%8 element of current each record if reclen%8 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%8 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%8 represents that record length presses 8 deliverys;
(2), when 4≤during stream length＜8, the request of bottom memory burst transmission burst length is made as 4, reorder and send the memory access request to lower floor after half buffer cell column direction fills up 4 in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤3,0≤j≤n-1, request address is the address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%4 element of current each record if reclen%4 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%4 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%4 represents that record length presses 4 deliverys;
(3), when 2≤during stream length＜4, the request of bottom memory burst transmission burst length is made as 2, reorder and send the memory access request to bottom after half buffer cell column direction fills up two in the address, be that address half buffer cell that reorders has only been filled in M[i] unit of [j] position, wherein 0≤i≤1,0≤j≤n-1, the request address M[0 in half buffer cell that reorders] [0], M[0] [1] ..., M[0] and storage addresses in [n-1] number position; When half buffer cell is being handled last reclen%2 element of current each record if reclen%2 is not equal to zero and reorder in the address, half buffer cell column direction is filled in behind reclen%2 the element and is just sent the memory access request to lower floor as long as reorder in the address, and wherein reclen%2 represents that record length presses 2 deliverys;
(4), when stream length=1, under the pattern of striding, want special consideration, steplength is that the request of 1 o'clock bottom memory burst transmission burst length is made as 4, half buffer cell M[0 reorders in the address] [j] number position fill in and finish after just to lower floor transmission memory access request, 0≤j≤n-1 wherein is in this case as long as send M[0] address of [0] number position is just passable; When steplength is other situations, take with the method for step (3) description the same to lower floor's transmission memory access request.
6, according to claim 3 or the 4 or 5 described access buffering mechanisms that reorder towards flow data, it is characterized in that: described data are returned the data that buffer cell comprises two same structures and are returned half buffer cell, and each data is returned half buffer cell and had 8 * n data word cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100345774A CN100489772C (en) | 2007-03-19 | 2007-03-19 | Stream data-oriented resequencing access storage buffering method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100345774A CN100489772C (en) | 2007-03-19 | 2007-03-19 | Stream data-oriented resequencing access storage buffering method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101021783A CN101021783A (en) | 2007-08-22 |
| CN100489772C true CN100489772C (en) | 2009-05-20 |
Family
ID=38709558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100345774A Expired - Fee Related CN100489772C (en) | 2007-03-19 | 2007-03-19 | Stream data-oriented resequencing access storage buffering method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100489772C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442387B (en) * | 2008-12-22 | 2011-04-20 | 成都市华为赛门铁克科技有限公司 | Method and apparatus for processing back-pressure data |
| JP5419761B2 (en) * | 2010-03-12 | 2014-02-19 | アズビル株式会社 | Device control apparatus and CPU |
| CN102567241A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Memory controller and memory access control method |
| CN102541506B (en) * | 2010-12-29 | 2014-02-26 | 深圳市恒扬科技有限公司 | First-in-first-out (FIFO) data register, chip and equipment |
| CN113742260A (en) * | 2021-11-05 | 2021-12-03 | 南京宏泰半导体科技有限公司 | Address scrambler generating device and method for memory test |
-
2007
- 2007-03-19 CN CNB2007100345774A patent/CN100489772C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101021783A (en) | 2007-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10811077B2 (en) | Refresh control circuit, memory device including the same and method of operating the same for hammer refresh operation | |
| EP3091439B1 (en) | Multi-bank memory with multiple read ports and multiple write ports per cycle | |
| CN101308697B (en) | FIFO burst buffer with large capacity based on SDRAM and data storage method | |
| CN1825479B (en) | Memory device and method for exchanging data with memory device | |
| US20160378379A1 (en) | Multi-layer memory system having multiple partitions in a layer | |
| CN100489772C (en) | Stream data-oriented resequencing access storage buffering method and device | |
| US20140185376A1 (en) | Method and system for asynchronous die operations in a non-volatile memory | |
| CN101702326B (en) | Memory controller | |
| JP5430484B2 (en) | Semiconductor memory device and control method thereof | |
| CN103246625B (en) | A kind of method of data and address sharing pin self-adaptative adjustment memory access granularity | |
| US8127087B2 (en) | Memory controller for improved read port selection in a memory mirrored system | |
| CN106095328A (en) | Each cycle has a read port and the multi-bank memory of one or more write port | |
| CN102541678A (en) | Multichannel NAND flash parallel memory controller | |
| CN103092785B (en) | Ddr2 sdram controller | |
| CN105518784A (en) | Data processor with memory controller for high reliability operation and method | |
| WO2016176807A1 (en) | Dram refreshing method, apparatus and system | |
| CN102681946A (en) | Memory access method and device | |
| JPH07507410A (en) | Improved solid state memory elements | |
| CN105279108A (en) | Method for writing data of solid-state drive | |
| CN100550189C (en) | The device of data storing method, mapping affairs and the method for write data line | |
| CN108417235A (en) | A kind of DRAM memory and access method based on 3D encapsulation | |
| US10372337B2 (en) | Write request processing method and memory controller | |
| CN102541769A (en) | Memory interface access control method and device | |
| CN100536021C (en) | High-capacity cache memory | |
| CN104575589B (en) | A kind of radiation-resistant SRAM self-refresh circuits of availability high and its self-refresh method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090520 Termination date: 20110319 |