CN100485894C - Flip chip packaging method and packaging structure thereof - Google Patents
Flip chip packaging method and packaging structure thereof Download PDFInfo
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- CN100485894C CN100485894C CNB2005101097791A CN200510109779A CN100485894C CN 100485894 C CN100485894 C CN 100485894C CN B2005101097791 A CNB2005101097791 A CN B2005101097791A CN 200510109779 A CN200510109779 A CN 200510109779A CN 100485894 C CN100485894 C CN 100485894C
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The method for packaging flip chip includes steps: supplying substrate, and the substrate possesses multiple IC substrate units; at least one metal inner connection layer is setup in each IC substrate unit; multiple connection pads are set up on surface of IC substrate unit; next, forming patternized procured adhesion layer to cover the substrate and the connection pads; forming openings to expose partial up surface of each connection pad, and filling conducting material into each opening; then, providing multiple chips, and multiple conductive salient points setup on bottom surface of chip; installing chip on surface of IC substrate unit; finally, dividing up the substrate into multiple structures of packaging flip chip. At least one chip is setup on surface of structure of packaging flip chip.
Description
Technical field
The invention provides a kind of flip-chip package method and flip-chip encapsulating structure, refer to that especially a kind of chip is installed on the method for packing and the flip-chip encapsulating structure of flip-chip substrate.
Background technology
In recent years, miniaturization and multifunction along with portable machines such as mobile computer, personal digital assistant (PDA) and mobile phones, and the function of CPU (CPU) and memory modules (memorymodule) etc. is complicated, make semiconductor technology not only need to develop to high integration, also must be to high density (high density) encapsulation development, so various light, thin, short, little packaging body just constantly is developed.And flip-chip (flip chip, FC) encapsulating structure is compared with traditional encapsulating structure, have rapid heat dissipation, low inductance, multiterminal and the less advantage of chip size, thus range of application also because these advantages constantly are expanded, and the use amount in several years of future will become the several times growth.
Please refer to Fig. 1, Fig. 1 is the generalized section of prior art flip-chip package (flip chip package, FC package) structure 30.As shown in Figure 1, prior art flip-chip encapsulating structure 30 includes a tube core (die) 32, and tube core 32 has active surface (active surface) 34 and a plurality of binder course (not shown) is arranged on active surperficial 34.Flip-chip encapsulating structure 30 includes substrate (substrate) 36 in addition, and this substrate has insulating protective layer 38,45 respectively in upper and lower surface, and substrate 36 is a multi-layer sheet, and insulating protective layer 38 has the salient point weld pad (bump pad) of a plurality of perforates to appear substrate.
Active surperficial 34 of tube core 32 insulating protective layers 38 during encapsulation towards substrate 36, and the position of each binder course (not shown) is corresponding with the position of each salient point weld pad (not shown).A plurality of solder bumps (solderbump) 42 are arranged at respectively between each binder course (not shown) and each the salient point weld pad (not shown), so that the physical connection of each binder course (not shown) to each salient point weld pad (not shown) to be provided.And between each binder course (not shown) and each solder bump 42, comprise (the under bump metallurgylayer of metallurgy layer under the salient point usually in addition, do not show), look the needs of technology and component design, can be used as binder course, barrier layer, wettable layer or conductive layer.Simultaneously, include at least one very lagre scale integrated circuit (VLSIC) (verylarge scale integration in the tube core 32, VLSI) or at least one utmost point very lagre scale integrated circuit (VLSIC) (ultra large scaleintegration, ULSI) the above integrated circuit of grade also is to be electrically connected to substrate 36 by above-mentioned each binder course (not shown), each solder bump 42 and each salient point weld pad (not shown).
In addition; include a bottom encapsulant (underfill material) layer 44 in the flip-chip encapsulating structure 30 in addition; bottom sealing material layer 44 fills up the space between substrate 36 and the tube core 32; avoid the influence of external environment with protection flip-chip encapsulating structure 30, and eliminate the stress (stress) of solder bump 42 junctions.Insulating protective layer 45 under substrate has a plurality of perforates, and with the soldered ball weld pad (solder ball pad) 46 that manifests substrate, this encapsulating structure 30 also has a plurality of soldered balls (solder balls) 48 that lay respectively at each soldered ball weld pad 46 below.
In sum, the substrate of prior art needs through reflow process repeatedly, is a kind of harsh test to the reliability of product.Especially regular meeting's generation substrate separates because of thermal coefficient of expansion (CTE) does not match with the bottom sealing material layer or causes substrate fracture phenomenons such as (crack) itself in lead-free process, can't guarantee the stabilizing quality of product.In addition, another shortcoming of prior art is that the substrate shipment is transported to the encapsulation field in single shipment mode and encapsulates, encapsulating factory then uses single mode to carry out follow-up encapsulation again, except that the equipment investment costliness, production capacity utilize low and relative cost high, import volume production in a large number is very big resistance.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of flip-chip package method, to overcome above-mentioned restriction and technical bottleneck.
According to disclosed flip-chip package method in the claim of the present invention, one substrate is provided earlier, and described substrate has a plurality of integrated circuit substrate unit, and be provided with articulamentum at least one metal in each integrated circuit substrate unit, and integrated circuit substrate unit surface is provided with a plurality of connection gaskets.Form insulation layer patterned subsequently, be covered on described substrate and the described connection gasket, and expose the part upper surface of described connection gasket and form opening respectively.In described opening, insert electric conducting material respectively afterwards, a plurality of chips (chip) are provided again, and the basal surface of described chip is provided with a plurality of conductive salient points, (mount) described chip can be installed in the surface of described integrated circuit substrate unit respectively by described insulating barrier, and the conductive salient point that makes this chip combines with the described electric conducting material of described electric conducting material in the integrated circuit substrate unit surface opening.Cut apart described substrate at last and become a plurality of flip-chip encapsulating structures, and each described flip-chip encapsulating structure surface is provided with at least one described chip.Wherein, the method that forms described insulating barrier is first insulating barrier that forms patterning and full solidification (curing) earlier, be covered on described substrate and the described connection gasket, and expose the part upper surface of described connection gasket and form described opening respectively, and then form patterning and second insulating barrier of precuring only, be covered on described first surface of insulating layer and expose described opening, be used for being used as the adhesion layer (adhesive layer) of described substrate and each described chip.
Because the present invention places chip on the precuring insulating barrier of substrate surface, finish combination and cutting technique again, therefore can significantly simplify encapsulation step, reduce material and use and avoid thermal coefficient of expansion not match and guarantee to encapsulate quality, effectively to reach the purpose of saving cost and quick volume production.
Description of drawings
Fig. 1 is the generalized section of prior art flip-chip encapsulating structure.
Fig. 2 to Fig. 7 is the process schematic representation according to first embodiment of flip-chip package method of the present invention.
Fig. 8 is according to the first flip-chip encapsulating structure schematic diagram of the present invention.
Fig. 9 to Figure 11 is the process schematic representation of second embodiment of flip-chip package method according to the present invention.
Figure 12 to Figure 15 is the process schematic representation of the 3rd embodiment of flip-chip package method according to the present invention.
Figure 16 to Figure 18 is the process schematic representation of the 4th embodiment of flip-chip package method according to the present invention.
Figure 19 is according to the second flip-chip encapsulating structure schematic diagram of the present invention
Description of reference numerals
30 flip-chip encapsulating structures, 32 chips
34 active surperficial 36 substrates
38 insulating protective layers, 42 solder bumps
44 bottom sealing material layers, 45 insulating protective layers
46 soldered ball weld pads, 48 soldered balls
60 substrate 60a integrated circuit substrate unit
62 connection gaskets, 64 insulating barriers
66 openings, 68 electric conducting materials
70 chips, 72 conductive salient points
74 soldered balls, 78 flip-chip encapsulating structures
80 substrate 80a integrated circuit substrate unit
82 connection gaskets, 84 first insulating barriers
86 second insulating barriers, 88 openings
90 electric conducting materials, 92 chips
94 conductive salient points, 100 substrates
100a integrated circuit substrate unit 102 connection gaskets
104 metal salient points, 106 insulating barriers
108 electric conducting materials, 110 chips
112 conductive salient points, 118 flip-chip encapsulating structures
120 substrate 120a integrated circuit substrate unit
122 connection gaskets, 124 metal salient points
126 first insulating barriers, 128 second insulating barriers
130 electric conducting materials, 132 chips
134 conductive salient points, 136 soldered balls
Embodiment
Please refer to Fig. 2 to Fig. 8, Fig. 2 to Fig. 8 is the process schematic representation according to first embodiment of flip-chip package method of the present invention.As shown in Figure 2, substrate 60 at first is provided, and for example MULTILAYER SUBSTRATE, and substrate 60 has a plurality of integrated circuit substrate unit 60a, and be provided with articulamentum (not shown) at least one metal among the integrated circuit substrate unit 60a, and integrated circuit substrate unit 60a surface is provided with a plurality of connection gaskets 62.As shown in Figure 3, then form insulation layer patterned 64, be covered on substrate 60 and the connection gasket 62, and expose the part upper surface of each connection gasket 62 and form opening 66 respectively.Wherein, insulating barrier 64 is the adhesion layer of precuring, and the material of formation insulating barrier 64 includes the fluoropolymer resin of sensing optical activity or non-sensing optical activity.In addition, the material that constitutes insulating barrier 64 is selected from ABF, aromatic series polyamide (Aramid), polypropylene (polypropylene, PP), polyimides (polyimide, PI), benzocyclobutene (Benzocyclobutene, BCB), liquid crystal polymer (LCP), polytetrafluoroethylene (Polytetrafluoroethylene, PTFE) organic polymer of Denging, resin or epoxy resin dielectric material.
As shown in Figure 4, insert electric conducting material 68 respectively in each opening 66 subsequently, the metal material of pastes such as scolding tin, copper cream or silver paste for example is as the adhesion that electrically connects with chip 70.Shown in Fig. 5,6, a plurality of chips 70 then are provided, and the basal surface of chip 70 is provided with a plurality of conductive salient points 72, and can be installed on each integrated circuit substrate unit 60a surface respectively, and the conductive salient point 72 of this chip 70 is combined with described electric conducting material 68 in the integrated circuit substrate unit 60a surface opening 66 by insulating barrier 64.The basal surface of its chips 70 can be provided with the adhesion layer (figure does not show) of precuring again, with a plurality of conductive salient points 72 chip 70 is installed on each integrated circuit substrate unit 60a surface respectively, and the conductive salient point 72 that makes this chip 70 combines with electric conducting material 68 in the integrated circuit substrate unit 60a surface opening 66, and is not limited to the disclosed practice of present embodiment.Because insulating barrier 64 is the adhesion layer of precuring, therefore when carrying out mounting process, chip 70 can be subjected to the external force extruding and be absorbed in insulating barrier 64.Be cured technology afterwards,, and make connection gasket 62, electric conducting material 68 and conductive salient point 72 form good bonding in order to the insulating barrier 64 of cured pre-cure.Then as shown in Figure 7, plant ball technology, form a plurality of soldered balls 74 with a plurality of soldered ball weld pad (not shown)s surface at the basal surface of integrated circuit substrate unit 60a.As shown in Figure 8, cut apart substrate 60 at last and be a plurality of flip-chip encapsulating structures 78, each flip-chip encapsulating structure 78 surface is provided with at least one chip 70.
As shown in Figure 8, the invention also discloses a kind of flip-chip encapsulating structure 78, include integrated circuit substrate unit 60a, and integrated circuit substrate unit 60a surface is provided with a plurality of connection gaskets 62; Insulation layer patterned 64 is covered on integrated circuit substrate unit 60a and the connection gasket 62, and forms opening respectively to expose the part upper surface of each connection gasket 62; Electric conducting material 68 fills in each opening; And chip 70, and the basal surface of chip 70 is provided with a plurality of conductive salient points 72, chip 70 can be installed on integrated circuit substrate unit 60a surface by insulating barrier 64, and the conductive salient point 72 that makes this chip 70 combines with electric conducting material 68 in the integrated circuit substrate unit 60a surface opening 66.Flip-chip encapsulating structure 78 also can be provided with a plurality of soldered balls 74, is arranged at the basal surface of integrated circuit substrate unit 60a, to electrically connect as itself and external device (ED).The basal surface of its chips 70 also can include the precuring adhesion layer, is arranged at (figure does not show) between the conductive salient point 72, to increase the tack of chip 70 and insulating barrier 64.
Please refer to Fig. 9 to Figure 11, Fig. 9 to Figure 11 is the process schematic representation according to second embodiment of flip-chip package method of the present invention.As shown in Figure 9, substrate 100 at first is provided, MULTILAYER SUBSTRATE for example, and substrate 100 has a plurality of integrated circuit substrate unit 100a, and also be provided with articulamentum (not shown) at least one metal among each integrated circuit substrate unit 100a, and each integrated circuit substrate unit 100a surface is provided with a plurality of connection gaskets 102.Then at each connection pad 102 central metal salient point 104 that form, to be used for increasing sticking together area and promoting evenly distribution of heat of follow-up electric conducting material 108 and connection gasket 102.Wherein, the material of formation metal salient point 104 is selected from the metal or the tin cream of the single or multiple lift combination of copper, nickel, gold, silver, copper, palladium, tin.
As shown in figure 10, then form insulation layer patterned 106, be covered on substrate 100 and the connection gasket 102, and form opening respectively to expose the part upper surface of each connection gasket 102.Wherein, insulating barrier 106 is the adhesion layer of precuring, and the material of formation insulating barrier 106 can be the materials such as fluoropolymer resin of aforementioned sensing optical activity or non-sensing optical activity.As shown in figure 11, subsequently respectively at the metallic conduction material of inserting in each opening as scolding tin, copper cream or silver paste etc. 108, as with the electric connection of chip 110.Then a plurality of chips 110 that are provided with a plurality of conductive salient points 112 are installed on integrated circuit substrate unit 100a surface by insulating barrier 106 with chip 110, and the conductive salient point 112 that makes this chip 110 combines with electric conducting material 108 in the integrated circuit substrate unit 100a surface opening.In addition, the basal surface of chip 110 can be provided with the adhesion layer (figure does not show) of precuring again, chip 110 is installed on each integrated circuit substrate unit 100a surface, and the conductive salient point 112 that makes this chip 110 combines with electric conducting material 108 in the integrated circuit substrate unit 100a surface opening, and is not limited to the disclosed practice of present embodiment.Be cured technology afterwards,, and make each connection gasket 102, each metal salient point 104, each electric conducting material 108 and each conductive salient point 112 form good bonding in order to the insulating barrier 106 of cured pre-cure.Carry out planting ball technology then, form a plurality of soldered balls with a plurality of soldered ball weld pad (not shown)s surface at substrate 100 basal surfaces.Cut apart substrate 100 at last and be a plurality of flip-chip encapsulating structures, and each flip-chip encapsulating structure surface is provided with at least one chip 110.
Please refer to Figure 12 to Figure 15, Figure 12 to Figure 15 is the process schematic representation according to the 3rd embodiment of flip-chip package method of the present invention.As shown in figure 12, substrate 80 at first is provided, MULTILAYER SUBSTRATE for example, and substrate 80 has a plurality of integrated circuit substrate unit 80a, and also be provided with articulamentum (not shown) at least one metal among each integrated circuit substrate unit 80a, and each integrated circuit substrate unit 80a surface is provided with a plurality of connection gaskets 82.As shown in figure 13, then form first insulating barrier 84 of patterning, be covered on substrate 80 and the connection gasket 82, and form opening 88 respectively to expose the part upper surface of connection gasket 82.Form second insulating barrier 86 of patterning subsequently, be covered in first insulating barrier, 84 surfaces, and expose each opening 88.Wherein, it should be noted that first insulating barrier 84 is completely crued material, and second insulating barrier 86 is the material of precuring, is used for being used as the adhesion layer of substrate 80 and each chip.In addition, first insulating barrier 84 and second insulating barrier 86 can be made up of identical or different material, and it can be made of the fluoropolymer resin of sensing optical activity or non-sensing optical activity, and its insulating layer material is the insulating barrier 64 of first embodiment as previously mentioned.
Subsequently as shown in figure 14, insert electric conducting material 90 respectively in each opening 88, the metal material of pastes such as scolding tin, copper cream or silver paste for example is as the adhesion that electrically connects with chip 92.As shown in figure 15, a plurality of chips 92 are provided, and the basal surface of chip 92 is provided with a plurality of conductive salient points 94, afterwards when carrying out the chip mounting process, each chip 92 can be subjected to the external force extruding and be absorbed in second insulating barrier 86 on substrate 80 surfaces, and chip 92 can be installed on each integrated circuit substrate unit 80a surface, and the conductive salient point 94 that makes this chip 92 combines with described electric conducting material 90 in the integrated circuit substrate unit 80a surface opening 88.Present embodiment is second insulating barrier, 86 installations that utilize precuring on chip 92 and the substrate 80.Be cured technology afterwards,, and make each connection gasket 82, each electric conducting material 90 and each conductive salient point 94 form good bonding in order to second insulating barrier 86 of cured pre-cure.In certain aforementioned technology, also can be earlier form adhesion layer (not shown), with the pull-out capacity of second insulating barrier 86 of effective increase follow-up itself and substrate surface precuring through precuring at the basal surface of chip 92.Plant ball technology (figure does not show) then, form a plurality of soldered balls with a plurality of soldered ball weld pad (not shown)s surface at substrate 80 basal surfaces, cut apart substrate 80 at last again and be a plurality of flip-chip encapsulating structures, and each flip-chip encapsulating structure surface is provided with at least one chip 92.
Please refer to Figure 16 to Figure 18, Figure 16 to Figure 18 is the process schematic representation according to the 4th embodiment of flip-chip package method of the present invention.As shown in figure 16, the substrate 120 that at first provides the surface to be provided with a plurality of connection gaskets 122, and substrate 120 has a plurality of integrated circuit substrate unit 120a, and also be provided with articulamentum (not shown) at least one metal among each integrated circuit substrate unit 120a.Then, be used for increasing sticking together area and promoting evenly distribution of heat of follow-up electric conducting material 130 and connection gasket 122 at each connection gasket 122 central metal salient point 124 that form.Subsequently as shown in figure 17, form first insulating barrier 126 of patterning, be covered on substrate 120 and the connection gasket 122, and form opening respectively to expose the part upper surface of connection gasket 122.And then second insulating barrier 128 of formation patterning, be covered in first insulating barrier, 126 surfaces, and expose each opening.Similarly, first insulating barrier 126 is completely crued material, and second insulating barrier 128 is the material of precuring, be used for being used as the adhesion layer of substrate 120 and each chip 132, and first insulating barrier 126 and second insulating barrier 128 can be made of also the identical or different materials such as fluoropolymer resin of aforementioned sensing optical activity or non-sensing optical activity.
As shown in figure 18, in each opening, insert electric conducting material 130 subsequently respectively, as with the electric connection of chip 132.Wherein electric conducting material 130 includes metal materials such as scolding tin, copper cream or silver paste.Again a plurality of chips 132 that are provided with a plurality of conductive salient points 134 can be installed on chip 132 each integrated circuit substrate unit 120a surface by insulating barrier 128, and the conductive salient point 134 that makes this chip 132 combines with described electric conducting material 130 in the integrated circuit substrate unit 120a surface opening.In addition, the basal surface of chip 132 can be provided with the adhesion layer (figure does not show) of precuring again, chip 132 is installed on each integrated circuit substrate unit 120a surface, and the conductive salient point 134 that makes this chip 132 combines with described electric conducting material 130 in the integrated circuit substrate unit 120a surface opening, and is not limited to the disclosed practice of present embodiment.Be cured technology afterwards,, and make each connection gasket 122, each metal salient point 124, each electric conducting material 130 and each conductive salient point 134 form good bonding in order to second insulating barrier 128 of cured pre-cure.Plant ball technology (figure does not show) then, form a plurality of soldered balls with a plurality of soldered ball weld pad (not shown)s surface at substrate 120 lower surfaces.Cut apart substrate 120 at last again and be a plurality of flip-chip encapsulating structures, and each flip-chip encapsulating structure surface is provided with at least one chip 132.
As shown in figure 19, the present invention discloses another flip-chip encapsulating structure 118, includes: integrated circuit substrate unit 120a, and integrated circuit substrate unit 120a surface is provided with a plurality of connection gaskets 122; First insulating barrier 126 of patterning is covered on integrated circuit substrate unit 120a and the connection gasket 122, and forms opening respectively to expose the part upper surface of each connection gasket 122; And second insulating barrier 128 of patterning, be covered in first insulating barrier, 126 surfaces, and expose opening; Electric conducting material 130 fills in each opening; Chip 132, and the basal surface of chip 132 is provided with a plurality of conductive salient points 134, chip 132 can be installed on integrated circuit substrate unit 120a surface by second insulating barrier 128, and the conductive salient point 134 that makes this chip 132 combines with described electric conducting material 130 in the integrated circuit substrate unit 120a surface opening.Flip-chip encapsulating structure 118 can be provided with a plurality of soldered balls 136 in addition in the basal surface of integrated circuit substrate unit 120a, to electrically connect as itself and external device (ED).Wherein the basal surface of each chip 132 can include a precuring adhesion layer (figure do not show) again and is arranged between the conductive salient point 134, to increase the tack of chip 132 and first insulating barrier 126 and second insulating barrier 128.In addition, the part surface of each connection gasket 122 can include metal salient point 124 again, in order to increase the area that sticks together of electric conducting material 130 and each connection gasket 122.
In sum, the present invention utilizes on the chip adhesion layer and completely crued first insulating barrier on the MULTILAYER SUBSTRATE and second insulating barrier of precuring through precuring, with effective increase pull-out capacity, and then chip is attached fully be attached to substrate, even be embedded in the insulating barrier on MULTILAYER SUBSTRATE surface, and do not need to utilize again the bottom sealing material layer to fill up space between substrate and the chip.Because the present invention does not need to form the bottom sealing material layer again and through reflow process repeatedly, so can effectively promote product quality and reliability yet.In addition, the present invention does not use under the situation of solder mask (solder mask) and bottom sealing material layer in the junction, more can effectively solve problems such as material thermal expansion coefficient does not match.
Be different from prior art, the present invention is after the substrate wiring is finished, directly with chip pressing in the precuring insulating barrier of substrate surface, finish combination, therefore carry out cutting technique again, can significantly simplify encapsulation step, reduce material and use and avoid thermal coefficient of expansion not match, to guarantee to encapsulate quality, and then the saving cost, and can improve production capacity (throughput).
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (35)
1, a kind of flip-chip package method includes:
Substrate is provided, and described substrate has a plurality of integrated circuit substrate unit, and each described integrated circuit substrate unit surface is provided with a plurality of connection gaskets;
Form insulation layer patterned, be covered on described substrate and the described connection gasket, and form opening respectively to expose the part upper surface of each described connection gasket;
In each described opening, insert electric conducting material respectively;
Provide a plurality of chips, and the basal surface of described chip is provided with a plurality of conductive salient points;
Described chip is installed in described integrated circuit substrate unit surface, and the conductive salient point that makes this chip combines with described electric conducting material in the integrated circuit substrate unit surface opening; And
Cutting apart described substrate is a plurality of flip-chip encapsulating structures, and each described flip-chip encapsulating structure surface is provided with at least one described chip.
2, flip-chip package method as claimed in claim 1, wherein, described insulating barrier is a precuring adhesion layer.
3, flip-chip package method as claimed in claim 2, wherein, when the described electric conducting material of the conductive salient point that described chip is installed in described opening, each described chip is subjected to the external force extruding and is absorbed in described precuring adhesion layer.
4, flip-chip package method as claimed in claim 1, wherein, described electric conducting material includes scolding tin, copper cream or silver paste metal material.
5, flip-chip package method as claimed in claim 1, wherein, the material that constitutes described insulating barrier includes the fluoropolymer resin of sensing optical activity or non-sensing optical activity.
6, flip-chip package method as claimed in claim 1, wherein, the basal surface of each described chip also includes the precuring adhesion layer, is arranged between the described conductive salient point.
7, flip-chip package method as claimed in claim 1, wherein, the part surface of each described connection gasket also includes metal salient point, in order to increase the area that sticks together of described electric conducting material and each described connection gasket.
8, flip-chip package method as claimed in claim 7, wherein, the material that constitutes described metal salient point is selected from the metal or the tin cream of the single or multiple lift combination of copper, nickel, gold, silver, copper, palladium, tin.
9, a kind of flip-chip package method includes:
Substrate is provided, and described substrate has a plurality of integrated circuit substrate unit, and each described integrated circuit substrate unit surface is provided with a plurality of connection gaskets;
Form first insulating barrier of patterning, be covered on described substrate and the described connection gasket, and form described opening respectively to expose the part upper surface of each described connection gasket;
Form second insulating barrier of patterning, be covered in described first surface of insulating layer, and expose each described opening;
In each described opening, insert electric conducting material;
Provide a plurality of chips, and the basal surface of described chip is provided with a plurality of conductive salient points;
Described chip is installed in described substrate unit surface, and the conductive salient point that makes this chip combines with described electric conducting material in the integrated circuit substrate unit surface opening; And
Cutting apart described substrate is a plurality of flip-chip encapsulating structures, and each described flip-chip encapsulating structure surface is provided with at least one described chip.
10, flip-chip package method as claimed in claim 9, wherein, described first insulating barrier is completely crued material.
11, flip-chip package method as claimed in claim 9, wherein, described second insulating barrier is the material of precuring in technology, is used for being used as the adhesion layer of described substrate and each described chip.
12, flip-chip package method as claimed in claim 9, wherein, when the described electric conducting material of the conductive salient point that described chip is installed in described opening, each described chip is subjected to the external force extruding and is absorbed in described second insulating barrier of described substrate surface.
13, flip-chip package method as claimed in claim 9, wherein, described first insulating barrier and second insulating barrier have the same composition material.
14, flip-chip package method as claimed in claim 9, wherein, described first insulating barrier and second insulating barrier have different composition materials.
15, flip-chip package method as claimed in claim 9, wherein, described electric conducting material includes scolding tin, copper cream or silver paste metal material.
16, flip-chip package method as claimed in claim 9 also includes the step of planting ball technology, in order to form a plurality of solder bumps on the described MULTILAYER SUBSTRATE surface that described chip is not installed.
17, flip-chip package method as claimed in claim 9, wherein, the basal surface of each described chip also includes the precuring adhesion layer, is arranged between the described conductive salient point.
18, flip-chip package method as claimed in claim 9, wherein, the part surface of each described connection gasket also includes metal salient point, in order to increase the area that sticks together of described electric conducting material and each described connection gasket.
19, as the flip-chip package method of claim 18, wherein, the material that constitutes described metal salient point is selected from the metal or the tin cream of the single or multiple lift combination of copper, nickel, gold, silver, copper, palladium, tin.
20, a kind of flip-chip encapsulating structure includes:
The integrated circuit substrate unit, and described integrated circuit substrate unit surface is provided with a plurality of connection gaskets;
Insulation layer patterned is covered on described integrated circuit substrate unit and the described connection gasket, and forms opening respectively to expose the part upper surface of each described connection gasket;
Electric conducting material fills in each described opening; And
Chip, and the basal surface of described chip is provided with a plurality of conductive salient points, by described insulating barrier described chip is installed on described integrated circuit substrate unit surface, and the conductive salient point that makes this chip combines with described electric conducting material in the integrated circuit substrate unit surface opening.
21, as the flip-chip encapsulating structure of claim 20, wherein, described electric conducting material includes scolding tin, copper cream or silver paste metal material.
22, as the flip-chip encapsulating structure of claim 20, wherein, described insulating barrier is the precuring adhesion layer.
23, as the flip-chip encapsulating structure of claim 20, wherein, the material that constitutes described insulating barrier includes the fluoropolymer resin of sensing optical activity or non-sensing optical activity.
24, as the flip-chip encapsulating structure of claim 20, wherein the basal surface of each described chip includes a precuring adhesion layer in addition and is arranged between the described conductive salient point.
25, as the flip-chip encapsulating structure of claim 20, wherein, the part surface of each described connection gasket also includes metal salient point, in order to increase the area that sticks together of described electric conducting material and each described connection gasket.
26, as the flip-chip encapsulating structure of claim 25, wherein, the material that constitutes described metal salient point is selected from the metal or the tin cream of the single or multiple lift combination of copper, nickel, gold, silver, copper, palladium, tin.
27, a kind of flip-chip encapsulating structure includes:
The integrated circuit substrate unit, and described integrated circuit substrate unit surface is provided with a plurality of connection gaskets;
First insulating barrier of patterning is covered on described integrated circuit substrate unit and the described connection gasket, and forms described opening respectively to expose the part upper surface of each described connection gasket;
Second insulating barrier of patterning is covered in described first surface of insulating layer, and exposes each described opening;
Electric conducting material fills in each described opening; And
Chip, and the basal surface of described chip is provided with a plurality of conductive salient points, described chip can be installed on described integrated circuit substrate unit surface by described second insulating barrier, and the conductive salient point that makes this chip combines with described electric conducting material in the integrated circuit substrate unit surface opening.
28, as the flip-chip encapsulating structure of claim 27, wherein, described electric conducting material includes scolding tin, copper cream or silver paste metal material.
29, as the flip-chip encapsulating structure of claim 27, wherein, described first insulating barrier is completely crued material.
30, as the flip-chip encapsulating structure of claim 27, wherein, described second insulating barrier is the material of precuring, is used for being used as the adhesion layer of described integrated circuit substrate unit and each described chip.
31, as the flip-chip encapsulating structure of claim 27, wherein, described first insulating barrier and second insulating barrier are the same composition material.
32, as the flip-chip encapsulating structure of claim 27, wherein, described first insulating barrier and second insulating barrier are different composition materials.
33, as the flip-chip encapsulating structure of claim 27, wherein, the basal surface of each described chip includes the precuring adhesion layer in addition, is arranged between the described conductive salient point.
34, as the flip-chip encapsulating structure of claim 27, wherein, the part surface of each described connection gasket also includes metal salient point, in order to increase the area that sticks together of described electric conducting material and each described connection gasket.
35, as the flip-chip encapsulating structure of claim 34, wherein, the material that constitutes described metal salient point is selected from the metal or the tin cream of the single or multiple lift combination of copper, nickel, gold, silver, copper, palladium, tin.
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| CNB2005101097791A CN100485894C (en) | 2005-09-20 | 2005-09-20 | Flip chip packaging method and packaging structure thereof |
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| TWI463610B (en) * | 2012-07-19 | 2014-12-01 | 矽品精密工業股份有限公司 | Substrate structure and die package integrating the substrate structure |
| JP6062393B2 (en) * | 2014-05-12 | 2017-01-18 | 株式会社豊田中央研究所 | Semiconductor device manufacturing method and semiconductor device |
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