CN100485869C - Polysilicon layer and preparation method - Google Patents
Polysilicon layer and preparation method Download PDFInfo
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- CN100485869C CN100485869C CNB2006100956449A CN200610095644A CN100485869C CN 100485869 C CN100485869 C CN 100485869C CN B2006100956449 A CNB2006100956449 A CN B2006100956449A CN 200610095644 A CN200610095644 A CN 200610095644A CN 100485869 C CN100485869 C CN 100485869C
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Abstract
The method for fabricating polycrystalline silicon layer includes following steps: first, providing a base plate, and forming a Non-crystalline silicon layer on the base plate; next, forming a patternized metal layer on the Non-crystalline silicon layer; then, carrying out a procedure of fast heating up annealing treatment in order to form a metal silicides between patternized metal layer and Non-crystalline silicon layer; moreover, the patternized metal layer and the metal silicides conduct heat energy to Non-crystalline silicon layer in order to convert Non-crystalline silicon layer to a polycrystalline silicon; final, removing patternized metal layer. It is not easy to generate phenomena of metal pollution by the polycrystalline silicon layer.
Description
Technical field
The invention relates to a kind of film and manufacture method thereof, and particularly relevant for a kind of polysilicon layer and manufacture method thereof.
Background technology
The communication interface of display behaviour and information is development trend at present with the flat-panel screens.Flat-panel screens mainly contains following several: organic electro-luminescent display (organic electro-luminescence display, OLED), plasma scope (plasma display panel, PDP), LCD (liquid crystaldisplay, LCD) and light emitting diode indicator (light emitting diode, LED) etc.
In aforementioned display device, (thin film transistor is TFT) as the switch element of display can to utilize thin-film transistor.Generally speaking, according to the channel layer Material Selection, thin-film transistor can be divided into two kinds of amorphous silicon film transistor (amorphous silicon TFT) and low-temperature polysilicon film transistors (low-temperature poly-silicon thin film transistor, LTPS TFT).Compared to general existing amorphous silicon film transistor, because the electron mobility of low-temperature polysilicon film transistor can reach more than the 200cm2/V-sec, so this low-temperature polysilicon film transistor area occupied is littler of to meet the demand of high aperture (aperture ratio).
In low-temperature polysilicon film transistor, mainly contain following several as the manufacture method of the polysilicon layer of channel layer.The first, hot boiler tube heating processing (furnace annealing process, FA) cooperate the solid-phase crystallization method (solid phase crystallization, SPC).The shortcoming of the method is: treatment temperature too high (greater than 600 ℃), and heat treatment time long (greater than 15 hours).Under the situation of using glass substrate, glass substrate produces distortion easily because of high temperature.
The second, and the radium-shine crystallisation of quasi-molecule (excimer laser crystallization, ELA).The shortcoming of the method is: the surface flatness of apparatus expensive, processing time length, polysilicon layer is poor.
The 3rd, and existing metal induced lateral crystallization method (metal induced lateral crystallization, MILC).The shortcoming of the method is: have metallic pollution in the polysilicon membrane.In addition, because individual die is too small, so grain size can only be represented with regional value.
The 4th, and quick power transfer tempering method (rapid energy transfer annealing, RETA).The shortcoming of the method is: adopt wafer as heating plate, so the method can't be applied on the large-area substrate.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of manufacture method of polysilicon layer, to improve the problem of metallic pollution.
In addition, another object of the present invention provides a kind of polysilicon layer, and it has the crystal grain of large-size.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of polysilicon layer, and it comprises the following steps.At first, provide a substrate, and on substrate, form an amorphous silicon layer.On amorphous silicon layer, form a patterned metal layer.Then, carry out pulse mode annealing in process (the pulsed rapid thermalannealing that is rapidly heated, PRTA) processing procedure, between patterned metal layer and amorphous silicon layer, to form a metal silicide (metal silicide), and patterned metal layer and metal silicide with thermal energy conduction to amorphous silicon layer, so that amorphous silicon layer converts a polysilicon layer to.At last, remove patterned metal layer.
In one embodiment of this invention, the material of patterned metal layer can be nickel, cobalt (Co), copper (Cu), tantalum (Ta), iron (Fe) or platinum (Pt).
In one embodiment of this invention, the be rapidly heated temperature of annealing in process processing procedure of pulse mode can be between 550 to 900 degree Celsius.
For reaching above-mentioned or other purposes, the present invention proposes a kind of polysilicon layer, and its manufacture method according to above-mentioned polysilicon layer forms, and the crystal grain of this polysilicon layer is spherical.
In one embodiment of this invention, the size of crystal grain is greater than 4000 dusts (angstrom).
In one embodiment of this invention, the surface roughness of polysilicon layer is less than 10 dusts.
Based on above-mentioned, the present invention adopts the pulse mode annealing in process that is rapidly heated to form metal silicide earlier, then patterned metal layer and metal silicide with thermal energy conduction to amorphous silicon layer, so that amorphous silicon layer converts a polysilicon layer to.Compared to existing metal induced lateral crystallization method, because the metal silicide that the present invention produced is difficult for the generation lateral transfer, so the present invention can improve the phenomenon of metallic pollution.In addition, compared to the radium-shine crystallisation of existing quasi-molecule, the present invention can produce the polysilicon layer with big crystallite dimension.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 F is the schematic diagram according to the manufacture method of a kind of polysilicon layer of one embodiment of the invention.
Fig. 2 is the be rapidly heated heating temperature curve figure of annealing in process of the pulse mode according to present embodiment.
Fig. 3 is the analysis chart of energy dissipation X-spectrometer of the polysilicon layer of present embodiment.
Embodiment
Figure 1A to Fig. 1 F is the schematic diagram according to the manufacture method of a kind of polysilicon layer of one embodiment of the invention.Please refer to Figure 1A, the manufacture method of the polysilicon layer of present embodiment comprises the following steps.At first, provide a substrate 110, and this substrate 110 can be glass (glass) substrate or quartz (quartz).Then, on substrate 110, form an amorphous silicon layer 120.In addition, the mode of formation amorphous silicon layer 120 for example is chemical vapour deposition (CVD) (chemical vapor deposition, CVD) processing procedure or plasma enhanced chemical vapor deposition (plasma enhanced CVD, a PECVD) processing procedure.
Please refer to Figure 1B, form a metal level 130 at amorphous silicon layer 120, and the material of this metal level 130 can be nickel, cobalt, copper, tantalum, iron, platinum or other metal materials.In addition, the mode of formation metal level 130 for example is a sputter process.
Please refer to Fig. 1 C, remove part metals layer 130, to form patterned metal layer 132.In addition, the method that removes part metals layer 130 for example is micro-photographing process and etch process.
Please refer to Fig. 1 D, then, carry out the pulse mode annealing in process processing procedure that is rapidly heated, between patterned metal layer 132 and amorphous silicon layer 120, to form a metal silicide 140.Then, continue to carry out the pulse mode annealing in process processing procedure that is rapidly heated, and patterned metal layer 132 with metal silicide 140 with thermal energy conduction to amorphous silicon layer 120, so that amorphous silicon layer 120 converts a polysilicon layer 150 to, shown in Fig. 1 E.
Fig. 2 is the be rapidly heated heating temperature curve figure of annealing in process of the pulse mode according to present embodiment.Please also refer to Fig. 1 D and Fig. 2, abscissa is the time, and unit is second.In addition, ordinate is a temperature, and unit is a Celsius temperature.For example, the be rapidly heated temperature of annealing in process processing procedure of pulse mode can be between 550 to 900 degree Celsius.In addition, with regard to each circulation, high temperature (900 ℃) for example is that to continue 5 seconds, the gradient of heating for example be that 70 ℃/second, the gradient of cooling are 35 ℃/second.More specifically, present embodiment is to utilize the pulse mode annealing in process processing procedure that is rapidly heated to produce earlier a spot of metal silicide 140, and this metal silicide 140 will be as the crystal seed point.Then, metal silicide 140 and patterned metal layer 132 are rapidly heated pulse mode, and infrared energy that the annealing in process processing procedure produced converts heat energy to and amorphous silicon layer 120 is given in conduction, so that amorphous silicon layer 120 carries out the crystallization action.In other words, this part again the mechanism of crystallization be a kind of similar solid-phase crystallization method (SPC-like).
Please refer to Fig. 1 F, remove patterned metal layer 132, and the method that removes patterned metal layer 132 for example is an etch process.So far, the manufacture method of the polysilicon layer 150 of present embodiment is roughly finished.
Because existing metal induced lateral crystallization method is to utilize the lateral transfer of metal silicide (migration), bring out amorphous silicon layer and produce crystallization again to reach, therefore (just not being patterned the zone that metal level 132 is covered among Fig. 1 D) in the transverse crystallizing zone has metallic pollution.Therefore, present embodiment further carries out energy dissipation X-spectrometer (Energy Dispersive X-ray Spectrometer, EDS) analysis for polysilicon layer.
Fig. 3 is the analysis chart of energy dissipation X-spectrometer of the polysilicon layer of present embodiment.Please refer to Fig. 3, abscissa is an energy, and unit is kilo electron volt (KeV).Ordinate be the quantity measured in the unit interval (countsper second, cps).Therefore the metal silicide 140 of present embodiment can't produce horizontal migration, and the signal of nickel element is not clearly (as the dashed region among Fig. 3) in the transverse crystallizing zone.In other words, in this transverse crystallizing zone, the content of nickel element is extremely low.
Please continue the 1F with reference to figure, the lattice of the polysilicon layer that the general radium-shine crystallisation of quasi-molecule is produced is a dendroid, yet the crystal grain of the formed polysilicon layer 150 of above-mentioned manufacture method is spherical.Because this metal silicide makes that the part nucleating point can form ahead of time in amorphous silicon layer, so that nucleation density greatly descends, so the crystal grain of polysilicon layer 150 can be bigger.The size of the crystal grain of the polysilicon layer that is produced compared to the radium-shine crystallisation of general quasi-molecule is approximately between 3000 dust to 4000 dusts, and the size of the crystal grain of the polysilicon layer 150 of present embodiment can be greater than 4000 dusts.In addition, the surface roughness of the polysilicon layer that the general radium-shine crystallisation of quasi-molecule is produced approximately be between tens of to hundreds of how rice (nanometer), and the surface roughness of the polysilicon layer 150 of present embodiment can be less than 10 dusts.
In sum, polysilicon layer of the present invention and manufacture method thereof have following advantage at least:
One, compared to existing solid-phase crystallization method, the processing time of the present invention is lacked (less than 2 minutes), and mode of heating is the pulse mode annealing in process processing procedure that is rapidly heated, so the present invention is suitable for forming polysilicon layer on various substrates.
Two, compared to the radium-shine crystallisation of existing quasi-molecule, equipment required for the present invention is comparatively cheap, and the processing time is lacked (less than 2 minutes).In addition, the surface flatness of the formed polysilicon layer of the present invention is preferable, approximately less than 10 dusts.
Three, compared to existing metal induced lateral crystallization method, because the metal silicide that the present invention produced is difficult for the generation lateral transfer, so the present invention can improve the phenomenon of metallic pollution.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (6)
1. the manufacture method of a polysilicon layer is characterized in that, comprising:
One substrate is provided, and on described substrate, forms an amorphous silicon layer;
On described amorphous silicon layer, form a patterned metal layer;
Carry out the pulse mode annealing in process that is rapidly heated, between described patterned metal layer and described amorphous silicon layer, to form a metal silicide, and described patterned metal layer and described metal silicide with thermal energy conduction to described amorphous silicon layer, so that described amorphous silicon layer converts a polysilicon layer to; And
Remove described patterned metal layer.
2. the manufacture method of polysilicon layer as claimed in claim 1 is characterized in that, the material of described patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
3. the manufacture method of polysilicon layer as claimed in claim 1 is characterized in that, described pulse mode be rapidly heated annealing in process temperature between Celsius 550 to 900 the degree between.
4. a polysilicon layer is characterized in that, its manufacture method according to the polysilicon layer of claim 1 forms, and the crystal grain of described polysilicon layer is spherical.
5. polysilicon layer as claimed in claim 4 is characterized in that the size of described crystal grain is greater than 4000 dusts.
6. polysilicon layer as claimed in claim 4 is characterized in that the surface roughness of described polysilicon layer is less than 10 dusts.
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| CNB2006100956449A CN100485869C (en) | 2006-06-22 | 2006-06-22 | Polysilicon layer and preparation method |
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| CNB2006100956449A CN100485869C (en) | 2006-06-22 | 2006-06-22 | Polysilicon layer and preparation method |
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| CN100485869C true CN100485869C (en) | 2009-05-06 |
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| CN117276410B (en) * | 2023-11-17 | 2024-03-29 | 浙江晶科能源有限公司 | Passivation contact solar cell and preparation method thereof |
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