CN100483665C - Semiconductor isolating structure and its forming method - Google Patents
Semiconductor isolating structure and its forming method Download PDFInfo
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- CN100483665C CN100483665C CNB2006100239855A CN200610023985A CN100483665C CN 100483665 C CN100483665 C CN 100483665C CN B2006100239855 A CNB2006100239855 A CN B2006100239855A CN 200610023985 A CN200610023985 A CN 200610023985A CN 100483665 C CN100483665 C CN 100483665C
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Abstract
This invention discloses a forming method for semiconductor isolation structure including: providing a semiconductor substrate, growing an oxidation layer on the substrate, utilizing a photo resist to form a mask pattern on the oxidation layer, localizing an active region and an isolation region by the mask pattern, injecting carbon atoms to the isolation region, removing the photo resist to anneal the substrate in mid temperature to distribute the carbon atoms uniformly so as to form an isolation structure, which includes a substrate and an active region formed on it, an isolation region containing injected ionized carbon atoms formed on the active region.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor isolating structure formation method and the isolation structure that forms with described method.
Background technology
Semiconductor integrated circuit includes source region and the isolated area between active area usually, and these isolated areas formed before making active device.The method that forms area of isolation in the prior art mainly contains carrying out local oxide isolation technology (LOCOS) or shallow ditch groove separation process (STI).LOCOS technology is at wafer surface deposit one deck silicon nitride, and then carries out etching, and the part recessed region is carried out the oxidation growth silica.Active device generates in the determined zone of silicon nitride.For isolation technology, the effective carrying out local oxide isolation of carrying out local oxide isolation in circuit still has problems.One of them problem is exactly " beak " (bird ' s beak) phenomenon in the silicon nitride marginal growth, as shown in Figure 1, its be since in the process of oxidation the hot expansibility difference between silicon nitride and the silicon cause.This " beak " taken actual space, increased the volume of circuit.Aspect of performance in oxidizing process, produces stress rupture to wafer.Therefore LOCOS technology only is applicable to the design and the manufacturing of large-size device.
Along with semiconductor technology enters the deep-submicron epoch, the element below the 0.18 μ m for example active area isolation layer of MOS circuit adopts shallow ditch groove separation process (STI) to make mostly.The STI isolation technology solves the effective ways that carrying out local oxide isolation causes " beak " problem in the MOS circuit.In this technology, on substrate, form earlier shallow trench, shallow trench with etching between the element separates, utilize chemical vapor deposition (CVD) in shallow trench, to insert dielectric medium again, silica for example, at sidewall oxidation with after inserting dielectric medium, make the wafer surface planarization with the method for cmp (CMP).
Because the depth-to-width ratio (Aspect Ratio) of the shallow trench of deep-submicron element is than higher, (High-Density-Plasma CVD HDP-CVD) fills silica so generally adopt the high-density plasma CVD (Chemical Vapor Deposition) method.HDP-CVD technology is gases such as the hydrogen that uses deposit to use with reacting gas and sputter simultaneously, helium, so that carry out deposit and sputter reaction simultaneously.In this sti oxide fill process, use silane (SiH
4), oxygen (O
2) and hydrogen (H
2) utilize high density plasma deposition (HDP-CVD) and sputter (Sputtering) technology to form silicon oxide film.Fig. 2 A to 2D is the schematic diagram that the silicon oxide film of filling in the sti trench groove filling process produces defective.For good trench fill during adjusting process, if sputtering raste is less than deposition rate, just owing under the situation of sputter, when the width of the groove 210 of substrate 200 little to a certain degree the time, the silica that sputters from the silicon oxide layer 220 of a side in the process that refluxes can be deposited on the silicon oxide layer in bight again, thereby form salient angle 230, shown in Fig. 2 A.Continued growth, its result can cause forming hole (void) 240 in the silicon oxide layer 220 of inserting groove, shown in Fig. 2 B.Therefore, the sputtering raste of HDP-CVD technology will suitably increase, so as the inclined-plane, both sides that makes groove top oxide layer mutually away from, converge the formation hole with the salient angle that prevents both sides to the center, as U.S. Pat 5,872,058 disclosed technical scheme is described.But sputtering raste can not be too high, if the situation of sputter occurred, in the sputter meeting generation top rake problem of bight metal and anti-reflective film (ARC) layer.During silicon oxide deposition layer 220, the substrate 200 of groove 210 top corner portion can be pruned, and shown in Fig. 2 C, causes active area to be destroyed, and causes the generation of leakage current in the case.When making the device of 10-100 nanometer level, becoming of sti trench groove is finer, it is difficult and complicated more that the control of fill process becomes, above-mentioned defective very easily appears in the filling of groove, and owing to the reason of operational characteristic itself, the phenomenon of boss can appear in the filling of groove inevitably, has influence on the performance of electronic component.Shown in Fig. 2 D, deep-submicron needs to develop very evenly smooth isolation and insulation system to nanoscale devices in the manufacturing of for example micro-electron transistor (a few electron transistor) and/or three dimensions stereo crystal pipe support structure (three dimension transistor architecture).If when with cmp (CMP) method boss being ground, very easily active area is caused damage, and the sheet resistance (sheet resistance) of atomic thin STI isolation structure is not high usually, is difficult to guarantee effective isolation.Therefore, when making deep-submicron, need find the isolation structure that the surface is more smooth, sheet resistance is higher to nanoscale devices.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of new semiconductor isolating structure and forming method thereof, with can make deep-submicron form to the process of nanoscale devices have an even surface, sheet resistance is higher, insulation property are better isolation structure.
For achieving the above object, the formation method that the invention provides a kind of semiconductor isolating structure comprises provides Semiconductor substrate; The insulating barrier of on substrate, growing; On insulating barrier, form the photoresist mask; Patterning photoresist mask, thereby at surface of insulating layer first area, location and second area; In the first area, inject particle; Remove photoresist; Substrate is annealed, thereby make even distribution of particle of injection form isolation structure.
The particle that is injected in the first area is the energetic ion carbon atom.
Described isolation structure is the isolation structure that has an even surface.
The injection energy of ionization carbon atom is 5KeV～180KeV.
The flux density of the implantation dosage of ionization carbon atom is 4 * 10
14～5 * 10
16Every square centimeter.
The injection degree of depth of ionization carbon atom is
Described annealing temperature is 500 ℃-800 ℃.
The volume density of injection zone intermediate ion carbon atom is 5 * 10
19～10
21Every cubic centimetre.
The area that described second area is determined is an active area.
Described insulating barrier is silicon oxide layer or silicon oxynitride layer.
Described Semiconductor substrate is the planar structure that includes source region and isolated area.
The formation method of another kind of semiconductor isolating structure provided by the invention is the insulating barrier of at first growing on substrate; On insulating barrier, form the photoresist mask; Patterning photoresist mask, thereby at surface of insulating layer first area, location and second area; Etching insulating barrier and substrate surface form shallow trench on the first area; In shallow trench, form oxide layer; In the shallow trench substrate of bottom portion, inject particle; Remove photoresist; Substrate is annealed, the particle of injection is evenly distributed; The backfill oxide layer forms isolation structure in shallow trench.
The particle that is injected in the shallow trench is the energetic ion carbon atom.
The injection energy of described ionization carbon atom is 5KeV～180KeV.
The flux density of the implantation dosage of ionization carbon atom is 4 * 10
14～5 * 10
16Every square centimeter.
The injection degree of depth of ionization carbon atom is
Described annealing temperature is 500 ℃-800 ℃.
The volume density that is injected into shallow trench intermediate ion carbon atom after the annealing is 5 * 10
19～10
21Every cubic centimetre.
The area that described second area is determined is an active area.
Described insulating barrier is silicon oxide layer or silicon oxynitride layer.
Described Semiconductor substrate is the planar structure that includes source region and isolated area.
Correspondingly, a kind of semiconductor isolating structure provided by the invention comprises Semiconductor substrate; The active area that on substrate, forms; And the isolated area that between active area, forms; The particle that comprises injection in the described isolated area, described particle are the ionization carbon atom.
The volume density of described ionization carbon atom in isolated area is 5 * 10
19～10
21Every cubic centimetre.
The injection degree of depth of described ionization carbon atom is
Described Semiconductor substrate is the planar structure that includes source region and isolated area.
Another kind of semiconductor isolating structure of the present invention comprises Semiconductor substrate; The active area that on substrate, forms; The shallow channel isolation area that between active area, forms; And the bottom isolated area of below shallow channel isolation area, forming by the injection particle.
Described particle is the ionization carbon atom.
The volume density of described ionization carbon atom in isolated area is 5 * 10
19～10
21Every cubic centimetre.
The injection degree of depth of described ionization carbon atom is
Described Semiconductor substrate is the planar structure that includes source region and isolated area.
Owing to adopted technique scheme, compared with prior art, the present invention has the following advantages:
Semiconductor device is comprising numerous active device regions and the isolated area that forms between active device region on the wafer.These isolated areas are to make active device at first to form before.Semiconductor isolating structure of the present invention and manufacture method thereof are to utilize the high energy ion carbon atom to be injected into the inner area of isolation that forms of wafer from wafer surface.Advantage of the present invention mainly shows:
(1) method of utilizing carbon ion to inject can form the very high area of isolation of sheet resistance.This is because the size of carbon ion is littler than silicon atom, after carbon atom is injected into suitable energy and dosage, carbon atom is diffused into the settling position in the lattice of holes of adjacent silicon crystal under annealing stage suitable temperature control subsequently, because carbon atom and silicon atom all are tetrads, carbon atom can form stable covalent bond with the carbon atom and/or the silicon atom that close on, and the energy gap, rank (energy bandgap) of carbon and silicon atom lattice structure can exceed one times in the gap, rank at least than silicon silicon atom lattice structure; At ambient temperature, constitute the high insulation area of isolation of sheet resistance, thereby improved the insulation isolation performance between the active area greatly;
(2) utilize the method formation isolated area of growth or filling very easily to cause the uneven phenomenon of isolated area.The method that semiconductor isolating structure of the present invention and manufacture method thereof adopt ion to inject forms isolated area, can control the width and the degree of depth of isolated area easily, in semiconductor device, adopt isolation structure of the present invention can between the active region of very high density, form the isolated area of nanoscale width, and the isolated area degree that has an even surface is very high, is very beneficial for the manufacturing of deep-submicron to nanoscale devices.
Description of drawings
Fig. 1 is the schematic diagram of " beak " (bird ' s beak) phenomenon in the silicon nitride marginal growth;
Fig. 2 A to 2D is the schematic diagram that the silicon oxide film of filling in the sti trench groove filling process produces defective;
Fig. 3 is the schematic diagram of isolation structure formation method first embodiment of the present invention;
Fig. 4 is the isolation structure profile that utilizes isolation structure formation method first embodiment of the present invention to form;
Fig. 5 is the schematic diagram of isolation structure formation method second embodiment of the present invention;
Fig. 6 is the isolation structure profile that utilizes isolation structure formation method second embodiment of the present invention to form;
Fig. 7 is the schematic diagram of isolation structure formation method the 3rd embodiment of the present invention;
Fig. 8 is the isolation structure profile that utilizes isolation structure formation method the 3rd embodiment of the present invention to form;
Fig. 9 is the flow chart of semiconductor isolating structure formation method of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Ion implantation is widely used in the large scale integrated circuit in the N type and P type MOS transistor and the transistorized manufacturing of CMOS.With suitable doping content suitable element ion is injected in the wafer for forming the switch passage and the oxide-semiconductor control transistors threshold voltage is very important below grid level oxide.By injecting different ions, can be used to form the current-voltage characteristic of active device structures and control device, for example reduce the hot carrier migration, reduce the generation of depletion layer leakage current etc.The invention provides a kind of notion of new isolation structure, in superficial growth on the silicon wafer of oxide layer, optionally use ionization carbon atom injection method between active device region, to form the isolated area of complanation.Use the carbon ion of different acceleration energies and dosage repeatedly to inject, pass through the annealing in process under proper temperature then,, form high-resistance insulation isolated area to reach the even distribution of the desired carbon ion degree of depth and volume density.The present invention has selected repeatedly carbon ion injection from low-yield to high-octane, cooperates with moderate to dosage highly to reach the preliminary carbon ion degree of depth and volume density distribution.High-temperature annealing in the employing reducing the effect of carbon ion in any oxonium ion and the interstitial void, and is avoided separating out of carbon ion, improves the ratio that carborundum and carbon carbon covalent bond form in the silicon wafer lattice.
The formation method of semiconductor isolating structure of the present invention is as a kind of new isolation structure formation method, the mode that adopts ion to inject, inject the high energy ion carbon atom to wafer surface, carbon ion is diffused into that wafer is inner to be formed covalent bond with silicon atom or the carbon ion that closes on and form isolation structure, and the active region that isolation structure is numerous is isolated from each other.Inject carbon ion dosage and inject energy by control, can reach the purpose that the control carbon ion injects the degree of depth and volume density.In middle high-temperature annealing process subsequently, carbon ion can spread in the silicon crystal of wafer because of being heated, and finally is evenly distributed in the specific region of substrate interior.Because carbon ion is less than the silicon atom on lattice top, carbon ion can enter in the lattice of silicon crystal, forms covalent bond with silicon atom, perhaps and between the carbon ion that closes on forms covalent bond.Carbon atom and silicon atom all are quadrivalent elements, so the covalent bond that forms between them is highly stable firm.Formed isolated area has the excellent insulation property energy.Here carbon ion of the present invention is injected the isolation structure that forms and be referred to as carbon ion injection isolation structure (CIII:carbon ion implantation isolation), be abbreviated as CI
3
Fig. 3 is the schematic diagram of isolation structure formation method first embodiment of the present invention.As shown in Figure 3, in first embodiment of isolation structure formation method of the present invention, at first in Semiconductor substrate 300 superficial growth oxide layers 310; Thickness of oxide layer is greatly about 80
-120
About, coating photoresist 330 on oxide layer 310 then, utilize exposure, develop, etc. technology form the window of isolated area 320 tops, regional 340 correspondences be active area.Do not remove the oxide layer 310 on isolated area 320 windows in the present embodiment.Inject carbon ion with the method that ion injects to isolated area 320 this moment, and carbon ion passes oxide layer 310 and enters into substrate formation CIII isolation structure.Be positioned at the photoresist mask pattern 330 above the active area 340, be used to prevent that carbon ion is injected with the source region., to the manufacture process of nanoscale devices,,, can reach and adjust the purpose that carbon ion injects the degree of depth and volume density at deep-submicron by the concentration of adjustment carbon ion injection and the energy of injection according to the needs of isolation structure design.The injection of carbon ion need be divided into usually repeatedly to be carried out to reach the even distribution of the degree of depth and volume density.The carbon ion acceleration energy can be divided into greater than 100KeV, between 50-100KeV, between 10-50KeV, is lower than 10KeV.During high-energy, use lower dosage.When low-yield, use higher dosage.Acceleration energy reaches 180KeV, and carbon ion can reach 5000
The degree of depth, the current density of implantation dosage is set to 4 * 10
14To 2 * 10
15Every square centimeter, be used to form the darker isolation structure of the degree of depth.Acceleration energy is lower than 10KeV, and carbon ion only injects under the oxide layer 100
, the current density of implantation dosage is set to 2 * 10
15To 4 * 10
16Every square centimeter, be used to form the more shallow isolation structure of the degree of depth.Utilizing repeatedly carbon ion to inject to reach the degree of depth is 100
～5000
Between even distribution.In the present embodiment, enter in the isolated area 320 in order to make carbon ion pass oxide layer 310, the strategy of high-energy low dosage is adopted in the injection of carbon ion.After carbon ion is injected into substrate interior, substrate is carried out middle high annealing, make carbon ion be subjected to thermal diffusion.Annealing temperature in the embodiment of the invention is about 600 ℃.Carbon ion spreads in silicon crystal in annealing process, because the carbon atomic ratio silicon atom is little, so carbon atom is easy to enter in the lattice of silicon crystal.Need prevent simultaneously that in annealing process the density that reaches capacity carbon silicon is separating out of the interior carbon ion of molten attitude altogether.As improve annealing temperature, then need shorten the time, short annealing.The present invention adopts carbon ion as injecting particle, and for 2 considerations: at first, the carbon atomic ratio silicon atom is little, enters easily in the lattice; Secondly, carbon and silicon all are quadrivalent elements, and carbon ion very easily forms stable carbon silicon covalent bond and carbon carbon covalent bond with the carbon ion and the silicon atom that close on, and the area of isolation of being made up of these covalent bonds has high sheet resistance (sheet resistance).Other element can't be compared with carbon aspect above-mentioned.Through after the above-mentioned technology, carbon ion is at CI
3Volume density in the isolation structure is 5 * 10
19～10
21Every cubic centimetre, inject the degree of depth and be about
Fig. 4 is the isolation structure profile that utilizes isolation structure formation method first embodiment of the present invention to form.As shown in Figure 4, the carbon ion of injection spreads at high-temperature annealing process, enters into the lattice of silicon crystal, has occupied the hole in the lattice, forms with carbon ion that closes on and silicon atom and stablizes firm covalent bond.Therefore, the zone 420 that carbon ion injects is the isolation structure of high-impedance state, and it is for providing the good isolation border between the active area on the substrate 400 430.Because carbon ion passes oxide layer 410 and enters into substrate, and oxide layer 410 is very smooth, so oxide layer 410 has guaranteed the flatness on isolation structure 420 surfaces.After arts demand removal oxide layer 410, active area 430 and isolation structure 420 surfaces are all very smooth.In semiconductor device, adopt isolation structure of the present invention to help the manufacturing of follow-up deep-submicron or nanoscale active device.
Fig. 5 is the schematic diagram of isolation structure formation method second embodiment of the present invention.As shown in Figure 5, in second embodiment of isolation structure formation method of the present invention, Semiconductor substrate 500 superficial growth oxide layers 510; Coating photoresist 530 on oxide layer 510 utilizes technologies such as mask, photoetching, etching to form the window of isolated area 520 tops, regional 540 correspondences be active area.In the present embodiment oxide layer above the isolated area 320 310 is removed.Therefore, in the present embodiment, in isolated area 320, inject carbon ion and can adopt the low-energy strategy of high dose.Carbon ion is injected into after the substrate interior, removes coating photoresist 530, about 600 ℃ substrate is carried out middle high annealing, makes carbon ion be subjected to thermal diffusion, enters contiguous lattice position.
Fig. 6 is the isolation structure profile that utilizes isolation structure formation method second embodiment of the present invention to form.As shown in Figure 6, the carbon ion of injection produces diffusion motion and enters into the lattice of silicon crystal at high-temperature annealing process, has occupied the hole in the lattice, forms with carbon ion that closes on and silicon atom and stablizes firm covalent bond.Therefore, the zone 620 of carbon ion injection is the CI of high-impedance state
3Isolation structure, it is for providing the good isolation border between the active area on the substrate 600 630.In addition, because the oxide layer on isolation structure 620 surfaces is removed, therefore the smooth degree of substrate 600 has guaranteed the flatness on isolation structure 620 surfaces, adopts isolation structure of the present invention to help the manufacturing of active device on the follow-up active area 630 in semiconductor device.
Fig. 7 is the schematic diagram of isolation structure formation method the 3rd embodiment of the present invention.As shown in Figure 7, in the 3rd embodiment of isolation structure formation method of the present invention, after Semiconductor substrate 700 superficial growth oxide layers 710, utilize technologies such as mask, photoetching, etching at substrate 700 surperficial utmost point shallow trenchs (ExtremeShallow Trench; EST) 720.Growth oxide layer 720a on shallow trench, backfill shallow trench then, present embodiment injects carbon ion in the base substrate of shallow trench 720, form the below, bottom and have CI
3The utmost point shallow trench isolation of isolation structure is from (ESTI).In the present embodiment, in shallow trench 720, inject carbon ion and also adopt the low-energy strategy of high dose.After carbon ion is injected into substrate interior, about 600 ℃, substrate is carried out middle high annealing, make carbon ion be subjected to thermal diffusion.Carbon ion spreads in silicon crystal in annealing process, carbon atom enters in the lattice of silicon crystal, form stable carbon silicon covalent bond and carbon carbon covalent bond with carbon ion that closes on and silicon atom, below shallow trench 720 bottoms, form the high CI of sheet resistance (sheetresistance)
3 Isolation structure 730.
Fig. 8 is the isolation structure profile that utilizes isolation structure formation method the 3rd embodiment of the present invention to form.As shown in Figure 8, the carbon ion of injection produces diffusion motion and enters into the lattice of silicon crystal at high-temperature annealing process, has occupied the hole in the lattice, forms with carbon ion that closes on and silicon atom and stablizes firm covalent bond; The CI that shallow trench internal oxidation layer 820a and backfill shallow trench 820 and below, bottom form
3Isolation structure 830.Just forming the CI that has very high surface resistance below the bottom between the active area 840
3ESTI isolated area isolation structure, that isolation performance is better, leakage current is littler.
Surface utmost point shallow trench (EST) can do than shallow many of shallow trench (ST), the ratio of the degree of depth and width (less than 3 to 1) is little more than shallow trench (ST); In the process that forms, can avoid producing the various defectives that similar Fig. 2 A to 2D describes the silicon oxide film generation of filling in the sti trench groove filling process.Such technological process can be accomplished littler isolated area and active area.
The degree of depth that carbon ion injects among second embodiment of the invention and the 3rd embodiment and carbon ion need different in the volume density of CI3 isolation structure because of design.But the degree of depth that carbon ion injects is all 100
～5000
Between; Carbon ion is at CI
3Volume density in the isolation structure all is 5 * 10
19～10
21Every cubic centimetre.
Fig. 9 is the flow chart of semiconductor isolating structure formation method of the present invention.As shown in Figure 9, CI of the present invention
3Isolation structure formation method comprises: Semiconductor substrate (step S101) is provided; The oxide layer of on substrate, growing (S102); On oxide layer, be coated with photoresist (S103); Utilize exposure, develop, etc. technology on oxide layer, form photo etched mask figure (S104); Utilization is positioned with source region and isolated area photo etched mask figure on the oxide layer of substrate surface; Pass oxide layer and in area of isolation, inject carbon ion (S105); Remove coating photoresist (S106), substrate is carried out high annealing, the carbon ion of injection is evenly distributed form CI
3Isolation structure (S107).Because the oxide layer surface is smooth, so CI
3Isolation structure is exactly the isolation structure that has an even surface.In manufacture process, the injection energy of carbon ion is 5KeV～180KeV; The flux density of the implantation dosage of carbon ion is 5 * 10
14～4 * 10
16Every square centimeter; The injection degree of depth of carbon ion is 100
～5000
Annealing temperature is 500 ℃-800 ℃; The volume density of carbon ion is 5 * 10 in the injection zone of annealing back
19～10
21Every cubic centimetre.Above-mentioned oxide layer is silica (SiO2) layer or silicon oxynitride (SiNO) layer.It is nano level CI that this method can form width
3Isolation structure.In addition, can also be on isolated area in step S105 etching oxidation layer and substrate surface form shallow trench, in the shallow trench substrate of bottom portion, inject carbon ion then, proceed follow-up processing step then, form the below, bottom and have CI
3The utmost point shallow channel isolation area (ESTI) of isolation structure.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1, a kind of formation method of semiconductor isolating structure comprises:
Semiconductor substrate is provided;
The insulating barrier of on substrate, growing;
On insulating barrier, form the photoresist mask;
Patterning photoresist mask, thus at surface of insulating layer first area, location and second area, the area that the first area is determined is an area of isolation, and the area that second area is determined is an active region;
Inject the energetic ion carbon atom in the first area, the injection of described carbon ion is adopted repeatedly and is injected, and the injection energy is 5KeV～180KeV, and the flux density of implantation dosage is 4 * 10
14～5 * 10
16Every square centimeter; Wherein, acceleration energy reaches 180KeV, and the current density of implantation dosage is set to 4 * 10
14To 2 * 10
15Every square centimeter, acceleration energy is lower than 10KeV, and the current density of implantation dosage is set to 2 * 10
15To 4 * 10
16Every square centimeter;
Remove photoresist;
Substrate is annealed, thereby make even distribution of particle of injection form isolation structure.
2, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: described isolation structure is the isolation structure that has an even surface.
3, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: the injection degree of depth of ionization carbon atom is
4, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: described annealing temperature is 500 ℃-800 ℃.
5, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: the volume density of injection zone intermediate ion carbon atom is 5 * 10
19～10
21Every cubic centimetre.
6, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: described insulating barrier is silicon oxide layer or silicon oxynitride layer.
7, semiconductor isolating structure formation method as claimed in claim 1 is characterized in that: described Semiconductor substrate is the planar structure that includes source region and isolated area.
8, a kind of semiconductor isolating structure comprises:
Semiconductor substrate;
The active area that on substrate, forms; With
The isolated area that between active area, forms;
Described isolated area forms by injecting the ionization carbon atom, and the injection of described carbon ion is adopted repeatedly and injected, and the injection energy is 5KeV～180KeV, and the flux density of implantation dosage is 4 * 10
14～5 * 10
16Every square centimeter; Wherein, acceleration energy reaches 180KeV, and the current density of implantation dosage is set to 4 * 10
14To 2 * 10
15Every square centimeter, acceleration energy is lower than 10KeV, and the current density of implantation dosage is set to 2 * 10
15To 4 * 10
16Every square centimeter.
9, semiconductor isolating structure as claimed in claim 8 is characterized in that: the volume density of described ionization carbon atom in isolated area is 5 * 10
19～10
21Every cubic centimetre.
10, semiconductor isolating structure as claimed in claim 8 is characterized in that: the injection degree of depth of described ionization carbon atom is
11, semiconductor isolating structure as claimed in claim 8 is characterized in that: described Semiconductor substrate is the planar structure that includes source region and isolated area.
12, a kind of semiconductor device that comprises isolation structure as claimed in claim 8.
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| TWI501419B (en) * | 2011-08-23 | 2015-09-21 | Lextar Electronics Corp | Leds and methods for manufacturing the same |
| CN103515281B (en) * | 2012-06-20 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of fleet plough groove isolation structure |
| US9070802B2 (en) * | 2013-08-16 | 2015-06-30 | Himax Imaging, Inc. | Image sensor and fabricating method of image sensor |
| CN105845795A (en) * | 2015-01-13 | 2016-08-10 | 北大方正集团有限公司 | Diode and manufacturing method therefor |
| US9824943B2 (en) * | 2015-10-20 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for forming the same |
| CN106876320B (en) * | 2015-12-11 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN112086518A (en) * | 2019-06-12 | 2020-12-15 | 芯恩（青岛）集成电路有限公司 | MOS device, phase inverter and preparation method thereof |
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