CN100483549C - 电阻存储器件及其操作和形成方法及包含它的计算机系统 - Google Patents

电阻存储器件及其操作和形成方法及包含它的计算机系统 Download PDF

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CN100483549C
CN100483549C CNB028273702A CN02827370A CN100483549C CN 100483549 C CN100483549 C CN 100483549C CN B028273702 A CNB028273702 A CN B028273702A CN 02827370 A CN02827370 A CN 02827370A CN 100483549 C CN100483549 C CN 100483549C
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G·哈斯
J·巴克
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Micron Technology Inc
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    • G—PHYSICS
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    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G—PHYSICS
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    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
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Abstract

公开了一种方法和设备，用于使用互补PCRAM元件来感测可编程导体随机存取存储器(PCRAM)的阻态，一个保持被感测的阻态和另一个保持互补阻态。感测放大器通过高和低电阻元件来检测电压释放，以确定被读取元件的阻态。

Description

电阻存储器件及其操作和形成方法及包含它的计算机系统
技术领域
本发明涉及一种用于感测可编程导体随机存取存储器(PCRAM)元件的电阻的方法和设备。
背景技术
PCRAM器件将二进制数据存储为两个不同的阻值，一个比另一个更高。该阻值代表特定的二进制值逻辑“0”或逻辑“1”。当感测PCRAM器件的阻值时，一般将经历读操作的存储单元电阻与参考单元电阻作比较来确定被读取单元的阻值，以及它的逻辑态。此方法在美国专利No.5,883,827中被公开。然而，此方法具有一些局限性。
如果参考单元有缺陷，并且阵列中的一列存储单元使用相同的缺陷参考单元，则整列存储单元将得到错误的阻值读取结果。另外，需要专用电路来将阻值写入参考单元，这样设置的感测放大器的电路将复杂而庞大。
典型地，PCRAM器件的感测方案还倾向于具有不同于一般使用在典型DRAM电路中的独特结构。尽管PCRAM与DRAM的不同之处在于它们在电阻性存储元件中存储二进制值而不是存储为电容器上的电荷，尽管PCRAM为非易失性的，其中DRAM中使用的电容器结构是易失性的，然而期望的是，如果两种器件的读取和写入电路尽可能的类似，这样现有的DRAM存储器件结构可以容易地适应于读取和写入PCRAM器件。
发明内容
本发明提供一种PCRAM存储器件和其操作方法，其利用了类似于一些DRAM存储器件中使用的读取结构。使用了包括第一和第二可编程导体存储元件的一对互补PCRAM存储单元，每个连接到相应的存取晶体管。写操作期间，第一和第二存储元件以互补二进制值写入，就是说：如果第一存储元件被写入高阻态，那么第二存储元件被写入低阻态；反之，如果第一存储元件被写入低阻态，则第二存储元件被写入较高的阻态。
例如在第一存储元件的读操作期间，感测放大器被连接使得其相应的输入被耦合以接收通过第一和第二存储元件释放的相应的预充电压。感测放大器读取通过两个存储元件的释放电压来确定哪一个是更大的电压，从而确定被读取存储单元的阻值(高或低)和逻辑态(高或低)。
附图说明
通过下面联系相应附图提供的本发明的典型实施例的详细描述，本发明的上述和其他特征与优点将变得更加明晰。附图中：
图1显示一种实例性的PCRAM器件；
图2为描述本发明一个方面的示意图。
图3为描述本发明另一方面的示意图。
图4为描述本发明另一方面的示意图。
图5显示了本发明使用的电容器的放电率特性曲线.
图6显示计算机系统中使用的本发明。
具体实施方式
本发明使用一种感测放大器结构，它与一些常规DRAM器件中使用的结构有些类似，用来感测PCRAM存储单元的阻态。在本发明中，二进制值在第一PCRAM单元中存储为阻值，同时其互补阻值存储在第二PCRAM单元中。在第一PCRAM单元读出期间，两个PCRAM单元均被使用以将预充电压释放到各自的感测放大器的输入，该感测放大器读取释放电压来确定阻值，从而确定经历读操作的第一PCRAM单元中存储的二进制值。
图1图示了一种提供在根据本发明构造的一部分PCRAM存储器件内部的示例性单元设置。图中的PCRAM存储元件102具有一个硫属化合物玻璃体和下方103和上方104导体。众所周知，可编程导体存储单元具有两个稳定的阻态：一个高阻和一个低阻。一般地，当闲置时存储器具有高阻态，但是可以在导体103和104上适当地施加偏置电压来将其编程为低阻态。典型地，PCRAM存储元件的低阻态其特征在于，在导体103和104之间穿过硫属化合物玻璃体或沿硫属化合物玻璃体表面的树枝晶生长。当没有这种树枝晶生长时高阻态存在。生长的树枝晶是相对不易失的，原因在于在除去偏置电压后树枝晶将保持在适当的位置持续相对长的时间，例如几天或几周。
图1进一步显示，PCRAM存储元件102通过导电栓塞101耦合到存取晶体管207上，此晶体管通过形成晶体管207的栅极结构的字线105驱动。存取晶体管通过导电栓塞101耦合到PCRAM存储元件的其中一个导体103上。PCRAM元件的另一个导体104通过一个公共单元板109连接到偏置电压上，其是对于存储器件中提供的其他PCRAM存储元件所共用的。
图1图示了一个普通的PCRAM结构，其中两个相邻的存储单元207、211耦合到公共位线118上。这样，图1还显示了另一个通过字线107驱动的存取晶体管211，它通过导电栓塞99与另一个PCRAM存储元件104相连接，该PCRAM存储元件104还依次连接到公共单元板109。存取晶体管211还具有连接到位线118的一个端子。
图2显示一个使用图1描述的单元结构的存储器阵列的电路图方案。这样，图2的上面部分图示了耦合到相应的PCRAM存储元件102和106的晶体管207和211，该存取晶体管207和211将存储元件102和106耦合到位线118。
同样在图2中显示的，在存储阵列中还配置有互补位线D1*120，另一组存取晶体管连接到其上，其依次连接到其他PCRAM存储元件。为了简化讨论，一个单独互补PCRAM单元对表示为300。它包括晶体管207和关联的PCRAM存储元件102，其耦合到位线118(D1)，还包括存取晶体管209和关联的PCRAM存储元件124，其耦合到位线120(D1*)。
写操作期间，耦合到晶体管207的行线105和耦合到晶体管209的行线113被启动，以使如果PCRAM存储元件102被写为高阻态，PCRAM元件124被写为低阻态，反之亦然。用这种方法，PCRAM存储元件102和124一起被存取并总是存储互补的电阻数字值。因而假设PCRAM存储元件102是被写入和读取的基本元件，耦合到位线118和120的感测放大器210将通过比较存储器读操作期间位线118上释放的预充电压与位线120上释放的预充电压来读取PCRAM存储元件102的值。
因而，存储器读取之前，预充电压通过预充电路301施加到互补位线118和120上。通过启动晶体管305的预充线上的逻辑电路来启动预充电路，以提供电压(例如Vcc/2)到两个位线118和120。
还可以提供平衡电路303，该平衡电路303是在预充电路启动后通过平衡信号而被启动的，以确保线118和120上的电压相同。线118和120上的电压通过线上的寄生电容保持。预充和平衡(如果存在的话)电路被启动之后，可以在互补单元对300上执行读操作。在图3中更详细地说明了此读操作，图3为感测放大器210输入通路的简化。
对于互补位线118和120的寄生电容表示为C1和C1*。相应的存取晶体管207和209如图示连接到它们各自的字线105和113。还示出了PCRAM存储元件102和124。正如注意到的，二进制值在例如存储器PCRAM存储元件102中被存储为阻值.它或为高阻值或为低阻值，而互补阻值将被存储在PCRAM存储元件124中。
在读操作期间，施加在互补位线118和120上的预充电压被允许通过存取晶体管207和209和通过存储元件102和124的相应阻值来释放。因为阻值不同，一个高一个低，因此位线D1和D1*(118，120)上的电压在读操作期间将分开。尽管初始施加在互补位线118和120上的电压为Vcc/2，但是在读操作期间此电压实际上会稍微高出大约.3mV，原因是位线118和120上的寄生电容C1和C1*的存在，以及晶体管207和209内部固有的栅-漏电容。
图5图示了读操作期间互补位线118和120上的电压。字线105和113的启动示出为脉冲信号，并且最初存在于两个位线D1和D1*上的Vcc/2+大约.3mV的电压开始衰减。因为一个PCRAM存储元件，如102，具有比另一个更高的电阻，与低电阻如124相关联的位线上的电压将比耦合到更高阻值的位线如D1上的电压衰减更快。这在图5中示出。
线D1和D1*上的两个电压的偏差逐渐增加。在字线105和113启动后预设时间处，感测放大器210被启动.感测放大器具有如图4所示DRAM排列中通常使用的结构。这样的感测放大器包括N感测放大器锁存器302和P感测放大器锁存器304。此结构如图4所示。
再回到图5，N感测放大器在t1时刻首先被启动。当N感测放大器启动时，具有较低电压的位线，在本例中如D1*，立即被拉到地。随后，P感测放大器在t2时刻被启动，其驱动较高电压线(如D1)到Vcc。因此在t2时刻，感测放大器210输出表示PCRAM存储元件102在高阻态的值Vcc。
尽管图5图示了当PCRAM存储元件102具有比存储元件104更高的电阻时产生的信号时序，但是显然，如果PCRAM存储元件102具有低阻态并且PCRAM存储元件124具有高阻态，则信号电平将颠倒.也就是说，图5中示出的信号图将使得位线D1*朝向Vcc而位线D1朝向地。
图5还说明了本发明的另一个方面。如图所示，对于读操作，行线105、113的电压从接近地电平升高到接近Vcc的正电平。此电压在感测放大器被使能之前(t1之前)回到接近地电平。结果，没有读PCRAM存储元件的重写。如果期望这种PCRAM单元的重写，那么在感测放大器210工作期间，具有被写到低阻态的存储元件的行线105、113上的电压可能处于接近Vcc的电压电平，这会自动地将读单元重写(刷新)到低阻态。
因为可编程导体存储元件为电阻性的而不是电容性的存储元件，可能它们会比DRAM中典型的电容性存储元件花费更长的时间将位线拉高到Vcc和到地。假如这是真实的，比最新一代DRAM感测放大器运行稍慢的老式DRAM感测放大器设计还可以用于PCRAM存储单元。这样做的好处在于，这些老式的DRAM感测放大器已经表明可以有效率地进行工作，并且它们的测试架构是已经证实的。因此，可以制作由使用DRAM感测放大器的PCRAM存储元件构成的混合存储器，这样既具有PCRAM技术的优点，还可以快速和廉价的生产。
尽管如图2所示，互补可编程接触存储元件102和106以及相关联的存取晶体管和位线D和D*被配置在同一存储阵列中，但是，互补存储单元、存取晶体管和位线还可以被配置在相应的不同存储阵列中.
图6为使用根据本发明一个实施例建立的PCRAM存储器件200的基于处理器的系统400的框图.基于处理器的系统400可以是计算机系统、处理控制系统或使用处理器和关联存储器的任意其他系统。系统400包括中央处理单元(CPU)402，例如，通过总线420与PCRAM存储器件408和I/O器件404进行通信的微处理器。需要注意总线420可以是通常用在基于处理器系统中的一系列总线和桥，但仅仅为方便起见，总线420表示为单一总线。第二I/O器件406也被表示出来，但并不是实现本发明所必须的.基于处理器的系统400还包括只读存储器(ROM)410，并可以包括如本领域公知的，通过总线420还与CPU402进行通信的外围设备，例如软驱412和光盘(CD)ROM驱动器414。
为了容易与总线420连接或断开，一个或更多的存储设备200可以配置在插入式的存储模块256上，如SIMM、DIMM或者其他插入式存储模块。虽然参考特定的典型实施例已经描述和说明本发明，但应该理解只要不脱离本发明的精神和范围，很多修正和替换都可以进行。因此，本发明并不受前述的限制，而仅受到附属的权利要求书的限定。

Claims (69)

1.一种操作可编程导体存储器件的方法，包括：
在第一和第二可编程导体存储元件中存储二进制值为相应的阻态，其中存储在第一可编程导体存储元件中的阻态与同时存储在第二可编程导体存储元件中的阻态互补；
通过经所述存储元件释放相应的电压并比较释放电压，确定存储在所述可编程导体存储元件之一中的二进制值；以及
重写仅在存储了低阻态的所述第一和第二可编程导体存储元件其中之一中存储的二进制值。
2.如权利要求1中的方法，其中所述释放包括：
将互补位线预充到一个电压值；和
通过所述第一和第二可编程导体存储元件来分别释放每个所述互补位线上的电压值。
3.如权利要求2中的方法，其中通过启用分别关联于每个所述存储元件的存取晶体管，所述互补位线上的所述预充电压值通过所述相应的第一和第二可编程导体存储元件释放。
4.如权利要求3中的方法，还包括在启用所述存取晶体管之前完成所述预充。
5.如权利要求4中的方法，还包括在启用所述存取晶体管之前平衡所述位线。
6.如权利要求3中的方法，其中所述比较包括：
确定与一个存储元件关联的释放电压是否是两个释放电压中的较高者或者较低者，如果与所述一个存储元件关联的释放电压为较高电压则输出第一二进制值，如果与所述一个存储元件关联的释放电压为较低电压则输出第二二进制值。
7.如权利要求6中的方法，还包括将具有较高释放电压的位线设定为第一预设电压态，并且将具有较低释放电压的位线设定为第二预设电压态。
8.如权利要求7中的方法，其中所述第一预设电压比所述第二预设电压更高。
9.如权利要求8中的方法，其中所述第二预设电压为地电压。
10.如权利要求7中的方法，还包括在所述位线被设为所述第一和第二预设电压态之前，禁用所述存取晶体管.
11.如权利要求7中的方法，还包括当所述位线被设为所述第一和第二预设电压态时，启用至少其中一个所述存取晶体管。
12.如权利要求1的方法，其中所述重写的操作包括：
在执行所述确定操作中所使用的传感放大器电路的操作期间，将耦合到所述一个可编程导体存储元件的行线的电压电平从地电平增大到系统电压电平。
13.一种可编程电阻存储器件，包括：
第一和第二位线；
与一对互补存储单元相关联的第一和第二可编程电阻存储元件，用于分别存储数据位的互补二进制数字值为不同的电阻值；
第一和第二存取器件，用于分别将所述第一和第二存储元件耦合到所述第一和第二位线；以及
传感放大器，具有分别耦合到所述第一和第二位线的输入端，用于读取在所述存储元件其中之一中存储为电阻值的所述数据位。
14.如权利要求13的器件，还包括预充电电路，用于在读操作之前将所述位线预充电到公共预充电电压。
15.如权利要求13的器件，还包括一对分别耦合到所述第一和第二存取器件的行线；以及
用于同时激活所述第一和第二行线、并因此激活所述第一和第二存取器件的电路。
16.如权利要求15的器件，其中所述第一和第二存取器件是存取晶体管。
17.如权利要求15的器件，其中当所述存取器件被激活时，所述位线上的所述预充电电压通过所述第一和第二可编程电阻存储元件的相应电阻来释放，所述传感放大器确定所述可编程电阻存储元件中所述的一个是否存储高阻态或是低阻态，并且输出对应于所存储阻态的二进制值。
18.如权利要求14的器件，其中所述位线具有存储了所述预充电电压的相关的寄生电容。
19.如权利要求18的器件，其中所述寄生电容存储了大于所述预充电电压的电压值。
20.如权利要求15的器件，其中以在读操作期间防止所述可编程电阻存储元件中的至少一个自动刷新的方式，来激活所述行线。
21.如权利要求13的器件，其中所述第一和第二可编程电阻存储元件位于不同的存储器阵列中。
22.如权利要求14的器件，还包括平衡电路，用于平衡所述位线上的电压。
23.一种存储器件，包括：
多个第一和第二可编程电阻存储单元对，每对存储单元包括：
与一对互补存储单元相关联的第一和第二可编程电阻存储元件，用于分别存储数据位的互补二进制数字值为不同的电阻值；
第一和第二存取器件，用于分别将所述第一和第二可编程电阻存储元件耦合到第一和第二位线；以及
传感放大器，具有分别耦合到所述第一和第二位线的输入端，用于读取在所述第一和第二可编程电阻存储元件其中之一中存储为电阻值的所述数据位。
24.如权利要求23的器件，还包括预充电电路，用于在读操作之前将所述位线预充电到公共预充电电压。
25.如权利要求23的器件，还包括一对分别耦合到所述第一和第二存取器件的行线；以及
用于同时激活所述第一和第二行线、并因此激活所述第一和第二存取器件的电路。
26.如权利要求25的器件，其中所述第一和第二存取器件是存取晶体管。
27.如权利要求25的器件，其中当所述存取器件被激活时，所述位线上的所述预充电电压通过所述第一和第二可编程电阻存储元件的相应电阻来释放，所述传感放大器确定所述第一和第二可编程电阻存储元件中所述的一个是否存储高阻态或是低阻态，并且输出对应于所存储阻态的二进制值。
28.如权利要求27的器件，其中所述位线具有存储了所述预充电电压的相关的寄生电容。
29.如权利要求28的器件，其中所述寄生电容存储了大于所述预充电电压的电压值。
30.如权利要求23的器件，其中所述第一和第二可编程电阻存储元件位于公共的存储器阵列中。
31.如权利要求23的器件，其中所述第一和第二可编程电阻存储元件位于不同的存储器阵列中。
32.如权利要求24的器件，还包括平衡电路，用于平衡所述位线上的预充电电压。
33.如权利要求23的器件，其中所述存储器件设置在存储器模块上.
34.如权利要求33的器件，其中所述存储器模块是插入式存储器模块。
35.一种计算机系统，包括：
处理器；
耦合到所述处理器的存储器系统，所述存储器系统包括：
第一和第二位线；
与一对互补存储单元相关联的第一和第二可编程电阻存储元件，用于分别存储数据位的互补二进制数字值为不同的电阻值；
第一和第二存取器件，用于分别将所述第一和第二可编程电阻存储元件耦合到所述第一和第二位线；以及
传感放大器，具有分别耦合到所述第一和第二位线的输入端，用于读取在所述第一和第二可编程电阻存储元件其中之一中存储为电阻值的所述数据位。
36.如权利要求35的系统，还包括预充电电路，用于在读操作之前将所述位线预充电到公共预充电电压。
37.如权利要求35的系统，还包括一对分别耦合到所述第一和第二存取器件的行线；以及
用于同时激活所述第一和第二行线、并因此激活所述第一和第二存取器件的电路。
38.如权利要求37的系统，其中所述第一和第二存取器件是存取晶体管。
39.如权利要求37的系统，其中当所述存取器件被激活时，所述位线上的所述预充电电压通过所述第一和第二可编程电阻存储元件的相应电阻来释放，所述传感放大器确定所述第一和第二可编程电阻存储元件中所述的一个是否存储高阻态或是低阻态，并且输出对应于所存储阻态的二进制值。
40.如权利要求36的系统，其中所述位线具有存储了所述预充电电压的相关的寄生电容。
41.如权利要求40的系统，其中所述寄生电容存储了大于所述预充电电压的电压值。
42.如权利要求35的系统，其中所述第一和第二可编程电阻存储元件位于公共的存储器阵列中。
43.如权利要求35的系统，其中所述第一和第二可编程电阻存储元件位于不同的存储器阵列中。
44.如权利要求35的系统，还包括平衡电路，用于平衡所述位线上的电压。
45.一种操作可编程电阻存储器件的方法，包括：
在第一和第二可编程电阻存储元件中存储二进制值为相应的阻态，其中存储在第一可编程电阻存储元件中的阻态与同时存储在第二可编程电阻存储元件中的阻态互补；
通过经所述可编程电阻存储元件释放相应的电压并比较释放电压，确定存储在所述可编程电阻存储元件之一中的二进制值；以及
在用于执行所述确定操作的传感放大器的激活期间，将耦合到所述第一和第二可编程电阻存储元件每一个的字线的电压电平维持在地电平。
46.一种操作可编程电阻存储器件的方法，包括：
在第一和第二可编程电阻存储元件中存储二进制值为相应的不同阻态，
通过经所述第一和第二可编程电阻存储元件释放相应的电压并比较释放电压，确定存储在所述存储元件之一中的二进制值。
47.如权利要求46的方法，其中所述释放包括：
预充电互补的位线，其分别可切换地耦合到所述第一和第二可编程电阻存储元件、耦合到公共电压值；以及
通过所述第一和第二可编程电阻存储元件中的每一个，分别释放所述互补位线每一个上的公共电压值。
48.如权利要求47的方法，其中通过启用分别与每个所述可编程电阻存储元件相关联的存取晶体管，将所述互补位线上的所述预充电电压值通过所述相应的可编程电阻存储元件而释放.
49.如权利要求48的方法，还包括在启用所述存取晶体管之前完成所述预充电。
50.如权利要求49的方法，还包括在启用所述存取晶体管之前平衡所述位线。
51.如权利要求48的方法，其中所述比较包括：
确定与一个存储元件关联的释放电压是否是两个释放电压中的较高者或者较低者，如果与所述一个存储元件关联的释放电压为较高电压则输出第一二进制值，如果与所述一个存储元件关联的释放电压为较低电压则输出第二二进制值。
52.如权利要求51中的方法，还包括将具有较高释放电压的位线设定为第一预设电压态，并且将具有较低释放电压的位线设定为第二预设电压态.
53.如权利要求52中的方法，其中所述第一预设电压比所述第二预设电压更高.
54.如权利要求53中的方法，其中所述第二预设电压为地电压。
55.如权利要求52中的方法，还包括在所述位线被设为所述第一和第二预设电压态之前，禁用所述存取晶体管。
56.如权利要求52中的方法，还包括在当所述位线被设为所述第一和第二预设电压态的时间期间，启用至少其中一个所述存取晶体管。
57.一种制造可编程电阻存储器件的方法，所述方法包括：
形成第一和第二位线；
形成与一对互补存储单元相关联的第一和第二可编程电阻存储元件，用于分别存储数据位的互补二进制数字值为不同的电阻值；
形成第一和第二存取晶体管，用于分别将所述第一和第二存储元件耦合到所述第一和第二位线；
形成预充电电路，用于将所述第一和第二位线预充电到第一电压；
形成相应的行线，用于操作所述存取晶体管以将所述存储元件耦合到相应的位线；以及
形成传感放大器，其具有分别耦合到所述位线的输入端。
58.如权利要求57的方法，还包括形成行解码器，用于解码行地址信号，并且选择性地且同时地启用所述字线。
59.如权利要求57的方法，其中所述可编程电阻存储元件是制作在公共的存储器阵列中的。
60.如权利要求57的方法，其中所述可编程电阻存储元件是制作在不同的存储器阵列中的。
61.如权利要求57的方法，还包括形成用于平衡所述位线的平衡电路。
62.一种操作可编程电阻存储器件的方法，该方法包括：
在与一对互补存储单元相关联的第一和第二可编程电阻存储元件中，分别存储数据位的互补二进制数字值为不同的电阻值；以及
读取在所述存储元件其中之一中存储为电阻值的所述数据位。
63.如权利要求62的方法，还包括：
在所述读操作之前，将可切换地耦合到所述第一和第二可编程电阻存储元件的相应位线预充电到公共预充电电压。
64.如权利要求63的方法，还包括：
通过所述第一和第二可编程电阻存储元件的相应电阻，来释放所述位线上的所述预充电电压；
确定所述其中一个存储元件是否存储高阻态或是低阻态；以及
输出对应于所存储阻态的二进制值。
65.如权利要求63的方法，其中所述预充电的操作还包括：
以与所述位线相关联的寄生电容来存储所述预充电压。
66.如权利要求63的方法，还包括：
平衡所述位线上的所述预充电压。
67.一种形成存储器件的方法，该方法包括：
形成存储单元阵列，其中所述形成操作还包括：
形成第一和第二位线；
形成与一对互补存储单元相关联的第一和第二可编程电阻存储元件，用于分别存储数据位的互补二进制数字值为不同的电阻值；
形成第一和第二存取晶体管，用于分别将所述第一和第二存储元件耦合到所述第一和第二位线；
形成预充电电路，用于将所述第一和第二位线预充电到第一电压；
形成相应的行线，用于操作所述存取晶体管以将所述存储元件耦合到相应的位线；以及
形成传感放大器，其具有分别耦合到所述位线的输入端。
68.如权利要求67的方法，其中所述第一形成操作还包括形成行解码器，用于解码行地址信号，并且选择性地且同时地启用所述字线。
69.如权利要求67的方法，其中所述第一形成操作还包括形成用于平衡所述位线的平衡电路。
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CN1672214A (zh) 2005-09-21
WO2003044802A2 (en) 2003-05-30
EP1454325A2 (en) 2004-09-08
US20080225571A1 (en) 2008-09-18
KR20080039548A (ko) 2008-05-07

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