CN100481376C - 半导体器件及其制造方法、电路板和电子装置 - Google Patents

半导体器件及其制造方法、电路板和电子装置 Download PDF

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Publication number
CN100481376C
CN100481376C CNB011165960A CN01116596A CN100481376C CN 100481376 C CN100481376 C CN 100481376C CN B011165960 A CNB011165960 A CN B011165960A CN 01116596 A CN01116596 A CN 01116596A CN 100481376 C CN100481376 C CN 100481376C
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semiconductor device
electric connection
semiconductor
connection part
electrode
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CN1311528A (zh
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桥元伸晃
花冈辉直
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体器件的制造方法，包括：在半导体芯片的第1面侧形成使凸起突出的步骤，以及在与第1面相反的第2面侧通过使从第2面凹陷的位置露出来形成导电层的步骤；来自导电层的孔的露出部和凸起作为电气连接部。

Description

半导体器件及其制造方法、电路板和电子装置
技术领域
本发明涉及半导体器件及其制造方法、电路板和电子装置。
背景技术
近年来，正在开发叠置多个半导体芯片的半导体器件。大多采用将导线或引线键合在半导体芯片的电极上来实现电连接，但由于设置导线等，所以对小型化有限制。
此外，正在开发在半导体芯片上形成贯通孔，在贯通孔中填充焊锡，并且形成凸起，从而实现上下半导体芯片之间的电连接。这样一来，在层叠的半导体芯片之间，形成与凸起的高度相当的间隙，所以在薄形化方面有限制。
发明内容
本发明是解决该问题的发明，其目的在于提供可以小型化和薄形化的半导体器件及其制造方法、电路板和电子装置。
(1)本发明的半导体器件的制造方法包括：在设置有电极的半导体元件的水平表面上，形成与所述电极电连接的导电层的步骤；
避开所述电极的上面，在所述导电层上形成第1电气连接部的步骤；以及
在所述半导体元件的设置有电极的水平表面的背面上形成孔，使得从垂直于半导体器件的表面的方向上看与所述第1电气连接部重叠的所述导电层的一部分表面露出，作为第2电气连接部的步骤。根据本发明，将第2电气连接部形成在半导体元件的孔的内部。因此，由于使其它部件的电气连接部进入到半导体元件来实现电连接，所以可以将半导体元件和其它部件之间的间隔变窄，可以小型化和薄形化。
(2)在本半导体器件的制造方法中，将所述电极形成为环状，覆盖所述电极以及所述电极的内侧的开口部地形成所述导电层，在与所述开口部对应的区域内形成所述孔。
(3)在本半导体器件的制造方法中，形成所述孔，使得所述第2电气连接部的区域从垂直于半导体器件的方向上看包括所述第1电气连接部的区域。
(4)在本半导体器件的制造方法中，在形成所述第1和第2电气连接部后，从形成所述电极面的背面研磨薄化所述半导体元件。
(5)在本半导体器件的制造方法中，作为所述第1电气连接部，也可以形成凸起。
(6)在本半导体器件的制造方法中，也可以预先形成比所述孔直径小的小孔，并扩大所述小孔来形成所述孔。
这样一来，可以用比形成孔小的能量来形成小孔，通过先形成小孔即可减小形成孔时的能量。
(7)在本半导体器件的制造方法中，用激光束来形成所述小孔，通过湿式腐蚀来扩大所述小孔也可以。
如果这样，可以容易地形成孔。此外，即使用激光形成的小孔的内壁表面粗糙，由于通过湿式腐蚀来扩大，所以可以形成光滑的内壁表面的孔。
(8)在本半导体器件的制造方法中，所述半导体元件可以是半导体芯片。
(9)在本半导体器件的制造方法中，所述半导体元件是半导体晶片的一部分，对所述半导体晶片进行所述步骤。
(10)本发明的叠置型的半导体器件的制造方法是层叠多个按上述方法制造的半导体器件的叠置型的半导体器件制造方法，包括：
在多个所述半导体器件中，将第1半导体器件的所述第1电气连接部和层叠在所述第1半导体器件上的第2半导体器件的所述第2电气连接部进行电连接的步骤。
在本半导体器件的制造方法中应用三维安装。
(11)在本半导体器件的制造方法中，与所述第1半导体器件的所述第1电气连接部相比，所述第2半导体器件的所述孔形成得大。
这样一来，可以避免第1半导体器件的第1电气连接部和第2半导体元件的内部电路之间的短路。
(12)本发明的半导体器件包括：半导体元件；
形成在设置有电极的所述半导体元件的水平表面上、与所述电极电连接的导电层；以及
避开所述电极上面，形成在所述导电层上的第1电气连接部；
在所述半导体元件的设置有电极的水平表面的背面上形成孔，使得从垂直于半导体器件的表面的方向上看与所述第1电气连接部重叠的所述导电层的一部分表面露出，作为第2电气连接部。根据本发明，第2电气连接部被形成在半导体元件的孔的内部。因此，由于可以使其它部件的电气连接部从第2表面进入至凹陷位置来实现电连接，所以可以使半导体元件和其它部件之间的间隔变窄，可以小型化和薄形化。
(13)在本半导体器件中，所述电极被形成环状，形成覆盖所述电极以及所述电极的内侧的开口部的所述导电层，在与所述开口部对应的区域内形成所述孔也可以。
(14)在本半导体器件中，形成所述孔，使得所述第2电气连接部的区域从垂直于半导体器件的方向上看包括所述第1电气连接部的区域。
(15)在本半导体器件中，所述半导体元件是半导体芯片就可以。
(16)在本半导体器件中，包括半导体晶片在内，所述半导体元件可以是所述半导体晶片的一部分。
(17)在本半导体器件中，所述第1电气连接部是凸起。
(18)本发明的电路板安装有上述半导体器件。
(19)本发明的电子装置具有上述半导体器件。
(20)本发明的叠置型半导体器件是层叠多个上述半导体器件而形成的叠置型的半导体器件，在多个所述半导体器件中，第1半导体器件的所述第1电气连接部和所述第1半导体器件相邻的第2半导体器件的所述第2电气连接部电连接着。
(21)在本半导体器件中，与所述第1半导体器件的所述第1电气连接部相比，所述第2半导体器件的所述孔可以形成得大。
如果这样，可以避免第1半导体器件的第1电气连接部和第2半导体元件的内部电路之间的短路。
(22)本发明的电路板安装有上述叠置型半导体器件。
(23)本发明的电子装置具有上述叠置型半导体器件。
附图说明
图1A～图1B表示应用本发明的第1实施例的半导体器件的制造方法的图。
图2A～图2C表示应用本发明的第1实施例的半导体器件的制造方法的图。
图3A～图3C表示应用本发明的第1实施例的半导体器件的制造方法的图。
图4A～图4C表示应用本发明的第1实施例的半导体器件的制造方法的图。
图5表示应用本发明的第1实施例的半导体器件的图。
图6A～图6C表示应用本发明的第2实施例的半导体器件的制造方法的图。
图7A～图7C表示应用本发明的第2实施例的半导体器件的制造方法的图。
图8A～图8C表示应用本发明的第2实施例的半导体器件的制造方法的图。
图9A～图9C表示应用本发明的第3实施例的半导体器件的制造方法的图。
图10A～图10B表示应用本发明的第3实施例的半导体器件的制造方法的图。
图11A～图11C表示应用本发明的第3实施例的半导体器件的制造方法的图。
图12A～图12B表示应用本发明的第3实施例的半导体器件的制造方法的图。
图13表示应用本发明的另一实施例的半导体器件的制造方法的图。
图14表示安装本实施例的半导体器件的电路板的图。
图15表示具有本实施例的半导体器件的电子装置的图。
图16表示具有本实施例的半导体器件的电子装置的图。
具体实施方式
以下，参照附图来说明本发明的优选实施例。
(第1实施例)
图1A和图1B表示本实施例中使用的半导体芯片10的局部图。图1A是半导体芯片10的剖面图，图1B是图1A的IB-IB线剖面图。半导体芯片10一般是长方体(包括立方体)，但未限定其形状，也可以是球状。
半导体芯片10在形成图中未示出的由晶体管和存储器等元件组成的集成电路的表面上有绝缘膜(层间膜)12。绝缘膜12大多是作为半导体芯片10的基本材料的氧化硅膜(SiO2)和氮化硅膜(SiN)。
在绝缘膜12上形成电极(焊盘)14，电极14在图中未示出的部分与集成电路电连接。电极14大多由铝来形成。电极14沿半导体芯片10表面的至少一边(大多数情况下为2边或4边)排列。此外，电极14有排列在半导体芯片10表面的端部的情况和排列在中央部的情况等。由于电极14按照集成电路的制造工艺方法来构成，所以可以在多个层形成。
电极14的平面形状如图1A虚线所示，为环形状。具体地说，电极14例如在形成矩形形状的中央部上形成开口部(例如，圆形)。
在绝缘膜12上形成钝化膜16。钝化膜16覆盖电极14的外形端部，还覆盖电极14的开口部的端部。在开口部内也形成钝化膜16。其结果，电极14在图1A中阴影线的部分中露出。钝化膜16例如可以由SiO2、SiN、聚胺树脂等来形成。
(半导体器件的制造方法)
在本实施例中，使用上述半导体芯片10按以下的方法来制造半导体器件。
如图2A所示，形成覆盖电极14的导电层18。如后面所述，最好所形成的导电层18具有可以跨过孔26(参照图4B)的内侧的强度(例如约1μm以上的厚度)。导电层18最好从电极14的外形端部突出来形成。导电层18还覆盖环状电极14(参照图1A)的开口部来形成。导电层18可以由无电解电镀来形成。
例如，作为用镍来形成导电层18的方法，可以在电极14上实施锌酸盐处理，将铝的表面置换为锌，然后将电极14浸泡在无电解镍电镀液中，经过锌和镍之间的置换反应而将镍沉积在电极14上。镍也生长在环状的电极14的开口部上。
或者，也可以将电极14浸泡在仅有选择地吸附在铝上的钯溶液中，然后浸泡在无电解镍电镀液中，以钯为核析出镍。
为在镍层上还形成金层，要进一步浸泡在无电解金电镀液中，便在镍层的表面上再形成金层。通过形成金层，可以进一步可靠地提高与在其上形成的凸起之间的电连接。一般的说，在电极14上，由于镍比金容易在短时间内析出，所以与用金来形成整个导电层18相比，用镍形成第1层(下层)，而用金形成第2层(上层)更好。
在将半导体芯片10浸泡在无电解电镀液中的情况下，也可以预先用保护膜(例如抗蚀剂等)来覆盖半导体芯片10的里面和侧面。此外，在无电解电镀液中浸泡半导体芯片10期间最好进行遮光。由此，可以防止因随着在溶液中浸泡半导体芯片10引起的溶液中的电极间的电位变化而改变电镀层厚度。这也适合于以下的任何无电解电镀。
如图2B所示，在半导体芯片10的形成电极14的面上形成抗蚀剂20，并对它进行构图。
作为形成抗蚀剂20的方法，可以使用旋转涂敷法、浸渍法、喷射涂敷法等。形成抗蚀剂20覆盖电极14。抗蚀剂20用于覆盖在后面的腐蚀步骤中不腐蚀的部分。抗蚀剂20可以是光抗蚀剂、电子线抗蚀剂、X线抗蚀剂中的任意一个，也可以是正型或负型中的任意一个。本实施例中使用的抗蚀剂20是正型的抗蚀剂。抗蚀剂20在涂敷后为了不附着在其它部件上，所以进行预烘焙使溶剂蒸发。
作为对抗蚀剂20进行构图的方法，在抗蚀剂20上配置掩模(图中未示出)，照射能量。能量根据抗蚀剂20的性质而异，是光、电子线、X线中的任意一个。掩模的形状由构图形状来决定，根据抗蚀剂20是正型还是负型而为相反形状。然后，对抗蚀剂20进行显像并进行后烘焙。
在构图过的抗蚀剂20上，在形成凸起22的区域中形成开口部。凸起22形成在电极14的外形的内侧。在本实施例中，将凸起22形成在电极14的中央开口部的内侧。此外，凸起22形成在从中央开口部的端部空出间隔的位置上。
如图2C所示，在抗蚀剂20的开口部上，通过由无电解电镀来形成金属层，从而形成凸起22。然后，如图3所示，除去抗蚀剂20。凸起22是从半导体芯片10的第1面(例如形成电极14的面)突出形成的第1电气连接部。
在用镍形成凸起22时，使用无电解镍电镀液。在无电解电镀中金属各向同性生长，但由于在抗蚀剂20的开口部内使金属生长，所以可以抑制向横(宽度)方向的扩大，而在高度方向上形成金属层。因此，可以形成直径小的凸起22。
再有，凸起22可以由镍、金、镍和金的混合物中的任意一个来形成，可以是单层也可以构成多层。例如，在镍构成的第1层上，也可以设置金构成的第2层。在镍层上还形成金层时，将镍层浸渍在无电解金电镀液中，在镍层的表面上再形成金层。通过形成金层，可以更可靠地形成与其它部件之间的电连接。一般来说，由于镍可以比金以短时间析出，所以与用金来形成整个凸起22相比，用镍形成第1层(下层)，而用金形成第2层(上层或表面层)就可以。
如图3B所示，在半导体芯片10上形成小孔24(例如，直径约20μm)。小孔24从半导体芯片10的第2面(例如，与形成电极的第1面相反的面)形成。小孔24以至少达到绝缘膜12的深度来形成较好，贯通绝缘膜12更好，而贯通钝化膜18也可以。这种情况下，从半导体芯片10的第1面来形成小孔24也可以。小孔24最好不是贯通孔，但即使是贯通孔，也不妨碍本发明的应用。在形成小孔24时，可以使用激光(例如，YAG激光或CO2激光)。小孔24按比后面记述的孔小的直径来形成。小孔24最好形成在凸起22的区域内。这样的话，即使难以控制小孔24的深度，也可以防止在凸起22内部形成小孔24，避免小孔24成为贯通孔。
接着，如图3C所示，在半导体芯片10上形成孔26。将上述小孔24扩大来形成孔26。例如，采用湿式腐蚀，可以腐蚀小孔24的内壁面。作为腐蚀液，例如可以使用氢氧化钾(KOH)、混合氟酸和氟化氨的水溶液(缓冲的氟酸)。虽然用铝形成的电极14会被腐蚀液腐蚀，但在这里电极14是被绝缘膜12和钝化膜16及导电层18覆盖着的。导电层18最好由腐蚀液难以腐蚀的材料(例如，镍或金)来形成。
为了阻止孔26的开口部的扩大，预先形成了不被腐蚀的膜28。膜28可以是氧化膜(氧化硅膜等)，可以通过CVD来形成。再有，膜28也可以在形成小孔24前形成。
孔26可以按具有开口端部和比开口端部直径大的中间部(例如，约40～50μm的直径)的形状来形成。例如，如图3C所示，可以从半导体芯片10的内表面的各处形成直径朝着厚度方向的中央变大的孔26。详细地说，孔26按从半导体芯片10的第2面(形成开口端部的面)至厚度方向的中央呈倒锥形倾斜的面、和从半导体芯片10的第1面(形成电极14的面)至厚度方向的中央呈倒锥形倾斜的面来形成。在采用湿式腐蚀的情况下，孔26就能形成这样的形状。
在上述例中，可以采用湿式腐蚀，也可以采用干式腐蚀，还可以组合两者。干式腐蚀可以是反应性离子腐蚀(RIE)。此外，在上述例中，形成小孔24并扩大它来形成孔26，但也可以不形成小孔24而直接形成孔26。这种情况下，可以采用各向异性腐蚀。
如图4A所示，研磨半导体芯片10。详细地说，研磨半导体芯片10的第2面(与电极14相反侧的面)，使其厚度变薄(反向弯曲)。在孔26是上述形状的情况下，通过研磨半导体芯片10直至孔26的最大直径位置，如图4A所示，可以增大研磨后的孔26的开口。
孔26使导电层18的设置凸起22部分的至少一部分内面露出。孔26最好比凸起22形成得大。此外，孔26按围住整个凸起22来形成。图4A所示的孔26是呈锥形的孔，但在本发明中该形状不是必须的，也可以使壁面沿深度方向垂直地形成孔26。
如图4B所示，在孔26的内侧使导电层18露出。例如，在孔26的内侧除去绝缘膜12和钝化膜16。在除去时，可以采用干式腐蚀。这样一来，通过孔26而露出的导电层18的部分成为第2电气连接部。第2电气连接部形成在从第2面(与电极14相反侧的面)凹陷的位置上。
此外，在凸起22上用后续步骤层叠的半导体芯片的电极大的情况下，由于其孔也可增大，所以凸起22还可进一步增大。可省略图2B所示的使用了抗蚀剂的光刻步骤，即不用掩模就可以形成凸起22。
(半导体器件)
图4B表示经上述步骤制造的半导体器件的图。该半导体器件包括具有多个电极14的半导体芯片10和从半导体芯片10的第1面(例如，形成电极14的面)突出的凸起22(第1电气连接部)。在第1面上预先形成导电层18，凸起22通过导电层18与各电极14电连接。导电层18通过半导体芯片10的第2面(与第1面相反的面)上形成的孔26而露出一部分。导电层18的露出部分成为第2电气连接部。第2电气连接部(导电层18的露出部分)形成在从第2面凹陷的位置。
此外，孔26或第2电气连接部(导电层18的露出部分)比导电层18的设置凸起22的部分形成得大。在孔26的内侧，导电层18为浮置的状态，凸起22由导电层18(仅由导电层18)来支撑。因此，凸起22上施加的应力通过导电层18被缓和。
其它的结构如上述制造方法中说明的那样。根据本实施例，在凹陷位置形成第2电气连接部(导电层18的露出部)。因此，如图4C所示，在多个半导体器件被叠置时(形成栈时)，凸起22(第1电气连接部)等端子变为从半导体芯片10的表面(第2面)进入的状态。这样一来，可以实现三维安装的半导体器件(叠置型半导体器件)的小型化和薄形化。
再有，在凸起22(第1电气连接部)和导电层18的露出部(第2电气连接部)之间的接合上，可以采用Ni-Ni、Au-Au、Au-Sn、焊锡等的金属接合，仅施加热、超声波振动、或施加超声波振动和热等来接合两者。接合后，两者的材料扩散，形成金属接合。
由于孔26形成在半导体芯片10中，所以最好使孔26的内面和凸起22之间电绝缘。为此，可以在孔26的内面形成绝缘膜，但也可以使孔26形成得比连接到导电部18的露出部的凸起22大。这样，凸起22便可从孔26中分离配置。通过分离孔26和凸起22，在孔26的内面不形成可靠性高的(厚的)绝缘膜也可以。但是，即使不积极地形成绝缘膜，在孔26的内面上大多用氧化膜等形成绝缘膜。
上下半导体芯片10可以用粘结剂等来粘结。作为粘结剂，可以使用各向异性导电粘结剂(ACA)，例如各向异性导电膜(ACF)或各向异性导电膏(ACP)。各向异性导电粘结剂是将导电粒子(填料)分散在粘合料中，也有添加分散剂的情况。通过导电粒子，可以实现凸起22(第1电气连接部)和导电层18的露出部(第2电气连接部)之间的电连接。作为各向异性粘结剂的粘合料，大多使用热固化性的粘结剂。
在图4C中，表示层叠采用本发明的多个半导体器件的叠置型半导体器件。该叠置型半导体器件在叠置多个半导体器件时(形成栈时)，凸起22(第1电气连接部)等端子为从半导体芯片10的表面(第2面)进入的状态。因此，该叠置型半导体器件是小型化和薄形化的半导体器件。
图5中进一步示出层叠半导体芯片30的半导体器件。详细地说，在层叠的多个半导体芯片10内，将半导体芯片30接合在位于形成孔26侧最外层的半导体芯片10上。半导体芯片30不限于应用本发明的半导体芯片，可以是裸芯片(倒装芯片)，也可以是实施任何封装的半导体芯片。半导体芯片30有多个凸起32，各凸起32通过半导体芯片10的孔26被接合到导电层18上。
(第2实施例)
图6A～图8C是说明应用本发明的第2实施例的半导体器件的说明图。
本实施例中使用的半导体芯片110有多个电极114。与第1实施例中说明的环状电极14不同，各电极114不必在中央形成孔，平面形状可以是矩形，可以是圆形，也可以是其它形状。多个电极114在半导体芯片110的一个面上，可以形成在中央部分，也可以形成在端部。在半导体芯片110形成矩形的情况下，电极114沿4边或平行的2边形成就可以。在半导体芯片110中，预先形成绝缘膜112和钝化膜116，具体来说，与第1实施例中的说明相同。
(半导体器件的制造方法)
在本实施例中，使用上述半导体芯片110，按以下方法来制造半导体器件。以下的方法也可以应用于第1和第2实施例。
如图6A所示，从电极114上在其相邻的区域(在图6A所示的例中，在钝化膜116上)中形成导电层118。导电层118在电极114上的大小为足够实现其与电极114之间良好的电连接，在与电极114的相邻区域中，可以形成凸起122，并且比孔126(参照图7C)形成得大。导电层118的其它结构和形成方法可以应用第1实施例的导电层18的内容。
如图6B所示，在半导体芯片110的形成电极114的面上形成抗蚀剂120，并对它进行构图。就其细节来说，可以采用与第1实施例的抗蚀剂20有关的内容。在抗蚀剂120中，在导电层118之上的避开电极114上面的位置上形成开口部。
如图6C所示，在抗蚀剂120的开口部中，通过无电解电镀来形成金属层，从而形成凸起122(第1电气连接部)。然后，如图7A所示，除去抗蚀剂120。就凸起122的结构和其形成方法来说，可以采用第1实施例的说明凸起22的内容。再有，凸起122在导电层118上，形成在避开电极114上面的位置。
如图7B所示，在半导体芯片110上形成小孔124。就小孔124来说，可以采用第1实施例的小孔24的内容。再有，将小孔124形成在凸起122的下方。
接着，如图7C所示，在半导体芯片110上形成孔126。使上述小孔124扩大来形成孔126。就孔126的形状和其形成方法来说，可以采用第1实施例中说明的孔26的形状和其形成方法。为了阻止孔126的开口部的扩大，预先形成不被腐蚀的膜128。
如图8A所示，对半导体芯片110进行研磨，如图8B所示，在孔126的内侧使导电层118露出。就这些方法来说，可以采用第1实施例中说明的内容。于是，通过孔126使导电层118的露出部分成为第2电气连接部。第2电气连接部形成在从第2面(与电极114相反侧的面)凹陷的位置上。在本实施例中，由于不限定电极114的形状，所以可以使用一般使用的半导体芯片。其它效果与第1实施例相同。
(半导体器件)
图8B表示应用本发明的半导体器件的图。本实施例的半导体器件在电极114附近、即避开电极114上面的位置上形成凸起122。根据本实施例，在凹陷位置上形成第2电气连接部(导电层118的露出部)。因此，如图8C所示，在叠置多个半导体芯片110时(形成栈时)，凸起122(第1电气连接部)等的端子变为从半导体芯片110的表面进入的状态。于是，可以使三维安装的半导体器件(叠置型半导体器件)实现小型化和薄形化。再有，电气的制造结构和半导体芯片的粘结手段与第1实施例中说明的相同。
(第3实施例)
图9A～图12B是说明应用本发明的第3实施例的半导体器件的图。在本实施例中，使用在第2实施例中说明的半导体芯片110。
(半导体器件的制造方法)
如图9A所示，在电极114上形成导电层218。导电层218最好完全覆盖电极114的表面。例如，如果电极114的端部用钝化膜116来覆盖，则至少在从钝化膜116露出的部分上形成导电层218。再有，形成从电极114突出的导电层218也可以。导电层218的其它结构和形成方法可以采用第1实施例的导电层18的内容。
如图9B所示，在形成半导体芯片110的电极114的面上形成抗蚀剂220，对它进行构图。就其细节来说，可以采用第1实施例的抗蚀剂20的内容。抗蚀剂220在导电层218上面，在电极114的上方形成开口部。在与形成半导体芯片110的电极114的面相反的面上，也可以形成抗蚀剂221。这也适用于第1和第2实施例。
然后，如图9B所示，在抗蚀剂220和导电层218的上面设置催化剂210。在本实施例中，催化剂210是钯。作为催化剂210的形成方法，例如将半导体芯片110浸泡在包含钯和锡的混合溶液中，然后，通过用盐酸等的酸来处理，就可以仅将钯设置在抗蚀剂220和导电层218的上面。
接着，通过剥离抗蚀剂220，可以仅在要形成凸起222(参照图9C)的区域上设置催化剂210。在剥离抗蚀剂220时，可以照射紫外线，也可以浸泡在弱碱性的溶液中来使抗蚀剂220剥离。由此，可以容易并可靠地使抗蚀剂220剥离。再有，在剥离抗蚀剂220的同时，也将在其相反侧形成的抗蚀剂221剥离。
然后，进行无电解电镀，形成如图9C所示的凸起222。在用镍来形成凸起222的情况下，通过将半导体芯片110浸泡在镍电镀液中，以作为催化剂210的钯为核来还原溶液中的镍离子，使镍析出。或者，用铜或金形成凸起222也可以。此外，作为形成凸起222的导电材料，可以使用多个不同种类的金属(例如，Ni+Cu、Ni+Au+Cu)，由此，可以用多层来形成凸起222。
在上述实施例中，在对抗蚀剂220进行构图后设置催化剂210。然后通过使抗蚀剂220剥离，使催化剂210在凸起222的形成区域露出。与本实施例不同，在半导体芯片110上面，将催化剂210设置在整个面上后，通过除了凸起222的形成区域以外对抗蚀剂220进行构图并设置，结果也可以在凸起222的形成区域中使催化剂210露出。这种情况下，在结束形成凸起222后，对抗蚀剂50进行剥离。
接着，以凸起222作为掩模，或者如果需要，在凸起222上设置图中未示出的保护膜，如图10A所示，对导电层218进行腐蚀。这样得到的导电层218为不从凸起222中突出的形状，即为仅形成在凸起222下的形状。此外，如图10A所示，在与半导体芯片110的电极114相反侧的面上，预先形成后述的不被湿式腐蚀的膜228。该膜228是氧化硅膜等，可以通过CVD来形成。
如图10B所示，用激光等来形成小孔224，然后，如第1实施例中说明的那样，进行湿式腐蚀，研磨半导体芯片110的内表面(与电极114相反侧的面)。于是，如图11A所示，在半导体芯片110上形成孔226。就孔226的形状来说，也可以采用第1实施例中说明的内容。
如图11B所示，至少在孔226的内面形成绝缘膜228。然后，如图11C所示，通过孔226来腐蚀在电极114下形成的绝缘膜112，使电极114通过孔226露出。
如图12A所示，至少在孔226的内侧的包括电极114的露出面的区域上设置催化剂240。对于催化剂240的内容和设置它的方法来说，可以采用图9B所示的催化剂210的内容和设置它的方法。再有，预先形成孔226，在台阶差大的情况下，也可以形成干膜来代替液状的抗蚀剂。
然后，如图12B所示，通过孔226在电极114的内表面(露出面)上形成导电层242。如图12B所示，与半导体芯片110的形成凸起222的面相反侧的面(也可以是绝缘膜230的表面)相比，导电层242形成在凹陷的位置上。导电层242由金属导电膏、软钎料等钎焊料形成，大多用电镀、印刷、分配器等方法来形成。也可以将该导电层242作为电气、机械的接合部件与凸起222进行接合。
根据本实施例，在凹陷位置形成第2电气连接部(导电层242)。因此，在叠置多个半导体器件时(形成栈时)，凸起222(第1电气连接部)等端子变为从半导体芯片110的表面进入的状态。于是，可以实现三维安装的半导体器件(叠置型半导体器件)的小型化和薄形化。再有，就电气的制造结构和半导体芯片的粘结方法来说，与第1实施例中说明的相同。
(其它实施例)
上述步骤是针对半导体芯片10进行的，但也可以对半导体晶片进行上述步骤。例如，如图13所示，对半导体晶片.300进行上述步骤，可以形成第1电气连接部(凸起22)和第2电气连接部(导电层18的露出部)。对该半导体晶片300进行切割，可以得到半导体器件。
图14表示安装本实施例的半导体器件1的电路板1000。电路板1000一般是使用例如玻璃环氧基板等有机系基板。在电路基板1000上按期望的电路来形成例如铜等组成的布线图形，通过将这些布线图形与半导体器件1的连接部(例如，作为第1电气连接部的凸起22)进行机械连接来实现它们之间的电导通。
作为具有应用本发明的半导体器件1的电子装置，图15示出笔记本型个人计算机2000，而图16示出携带电话3000。
再有，将上述实施例的‘半导体芯片’置换为‘电子元件’，可以制造电子部件。作为使用这样的电子元件制造的电子部件，例如有光元件、电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、可变电阻、电位器或保险丝等。

Claims (23)

1.一种半导体器件的制造方法，其特征在于包括：
在设置有电极的半导体元件的水平表面上，形成与所述电极电连接的导电层的步骤；
避开所述电极的上面，在所述导电层上形成第1电气连接部的步骤；以及
在所述半导体元件的设置有电极的水平表面的背面上形成孔，使得从垂直于半导体器件的表面的方向上看与所述第1电气连接部重叠的所述导电层的一部分表面露出，作为第2电气连接部的步骤。
2.如权利要求1所述的半导体器件的制造方法，其特征在于：
将所述电极形成为环状，覆盖所述电极以及所述电极的内侧的开口部地形成所述导电层，在与所述开口部对应的区域内形成所述孔。
3.如权利要求1所述的半导体器件的制造方法，其特征在于：
形成所述孔，使得所述第2电气连接部的区域从垂直于半导体器件的方向上看包括所述第1电气连接部的区域。
4.如权利要求1所述的半导体器件的制造方法，其特征在于：
在形成所述第1和第2电气连接部后，从形成所述电极的面的背面研磨薄化所述半导体元件。
5.如权利要求1所述的半导体器件的制造方法，其特征在于：
形成凸起作为所述第1电气连接部。
6.如权利要求1所述的半导体器件的制造方法，其特征在于：
预先形成比所述孔直径小的小孔，并扩大所述小孔来形成所述孔。
7.如权利要求6所述的半导体器件的制造方法，其特征在于：
用激光束来形成所述小孔，通过湿式腐蚀来扩大所述小孔。
8.如权利要求1所述的半导体器件的制造方法，其特征在于：
所述半导体元件是半导体芯片。
9.如权利要求1所述的半导体器件的制造方法，其特征在于：
所述半导体元件是半导体晶片的一部分，对所述半导体晶片进行所述步骤。
10.一种叠置型的半导体器件的制造方法，将按照从权利要求1至权利要求9中任一项所述的方法制造的半导体器件层叠多个来制造叠置型半导体器件，其特征在于该方法包括：
在多个所述半导体器件内，将第1半导体器件的所述第1电气连接部和在所述第1半导体器件上层叠的第2半导体器件的所述第2电气连接部进行电连接的步骤。
11.如权利要求10所述的叠置型的半导体器件的制造方法，其特征在于：
与所述第1半导体器件的所述第1电气连接部相比，所述第2半导体器件的所述孔形成得大。
12.一种半导体器件，其特征在于包括：
半导体元件；
导电层，形成在设置有电极的半导体元件的水平表面上，与所述电极进行电连接；以及
第1电气连接部，避开所述电极上面，形成在所述导电层上；
在所述半导体元件的设置有电极的水平表面的背面上形成有孔，使得从垂直于半导体器件的表面的方向上看与所述第1电气连接部重叠的所述导电层的一部分表面露出，作为第2电气连接部。
13.如权利要求12所述的半导体器件，其特征在于：
将所述电极形成为环状，覆盖所述电极以及所述电极的内侧的开口部地形成所述导电层，在与所述开口部对应的区域内形成所述孔。
14.如权利要求12所述的半导体器件，其特征在于：
形成所述孔，使得所述第2电气连接部的区域从垂直于半导体器件的方向上看包括所述第1电气连接部的区域。
15.如权利要求12所述的半导体器件，其特征在于：
所述半导体元件是半导体芯片。
16.如权利要求12所述的半导体器件，其特征在于：
包括半导体晶片，所述半导体元件是所述半导体晶片的一部分。
17.如权利要求12所述的半导体器件，其特征在于：
所述第1电气连接部是凸起。
18.安装有权利要求12至权利要求16中任一项所述的半导体器件的电路板。
19.具有权利要求12至权利要求16中任一项所述的半导体器件的电子装置。
20.一种叠置型的半导体器件，层叠多个权利要求12至权利要求16中任一项所述的半导体器件而形成的叠置型半导体器件，其特征在于：
在多个所述半导体器件内，将第1半导体器件的所述第1电气连接部和所述第1半导体器件相邻的第2半导体器件的所述第2电气连接部进行电连接。
21.如权利要求20所述的叠置型半导体器件，其特征在于：
与所述第1半导体器件的所述第1电气连接部相比，所述第2半导体器件的所述孔形成得大。
22.安装有权利要求20所述的半导体器件的电路板。
23.具有权利要求20所述的半导体器件的电子装置。
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