CN100476693C - Idle state of processor - Google Patents

Idle state of processor Download PDF

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Publication number
CN100476693C
CN100476693C CNB018187986A CN01818798A CN100476693C CN 100476693 C CN100476693 C CN 100476693C CN B018187986 A CNB018187986 A CN B018187986A CN 01818798 A CN01818798 A CN 01818798A CN 100476693 C CN100476693 C CN 100476693C
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China
Prior art keywords
programmable processor
idle
idle condition
execution pipeline
processor
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Expired - Fee Related
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CNB018187986A
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Chinese (zh)
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CN1656435A (en
Inventor
C·P·罗思
R·P·辛格
T·托马斯因
D·B·威特
R·科拉戈特拉
J·雷维利亚
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Analog Devices Inc
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Analog Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the method discussed is applicable to placing a programmable processor in a power idle state and returning the processor to an operating state.

Description

The idle condition of processor
Background
The present invention relates to programmable processor is arranged in the idle condition.
Programmable processor for example is applicable to the microprocessor in computing machine or the digital information processing system, can have the ability that per second is carried out 1,000,000 electronic operations.In some applications, processor also can only be carried out operation seldom in the given time, but processor still is full power and prepares to carry out required operation.When for example processor is worked with the powered battery device, just do not wish that power consumption is arranged.
Description of drawings
Fig. 1 is the block scheme of explanation streamline programmable processor example.
Fig. 2 is the synoptic diagram of illustrated example execution pipeline.
Fig. 3 is that explanation is arranged on processing flow chart in the idle condition with processor.
Fig. 4 is the logical diagram of idle handler.
Fig. 5 is explanation is returned processor from idle condition a processing flow chart.
Fig. 6 is explanation is returned processor from idle condition a processing flow chart.
Embodiment
Under some occasion, wish that the operation of processor can suspend.When the operation suspension of processor, the power that offers processor can reduce, thereby improves the efficient of the energy and prolong the power of battery.Technology discussed below can provide the method that produces the idle condition be applicable to processor, and in idle condition, processor is only carried out less operation or handled operation, does not accept to be used for the instruction that will carry out, and/or ignores interruption.The another kind of technology of being discussed is applicable to that processor " wakes " its idle condition and make it to turn back to its duty.
Fig. 1 is the block scheme of explanation programmable processor 10, and programmable processor 10 has execution pipeline 14 and control module 12.Control module 12 is being controlled instruction and data flowing by streamline 14 in a clock period.For example, in the processing procedure of instruction, control module 12 can instigate each parts of streamline 14 that instruction is deciphered, and carries out corresponding operation, and these operations can comprise, for example the result are overwritten in the storer.Many operations of processor 10 all are subjected to clock control, and are to provide clock signal by clock controller 15.
Be marked as " idle output " 17 lines and connecting streamline 14 and idle controller 11, be shown control module 12 parts among Fig. 1.Idle controller 11 can produce idle condition.In addition, idle controller 11 also can insert (assert) idle carry-out bit 17, in order to the expression idle condition.The insertion of idle output 17 can postpone streamline 14, also can cause the time-out of streamline 14 operations.The time-out of operation can be the part that processor 10 is arranged on idle condition.Hereinafter will do more detailed description to idle controller 11 and idle output 17.
In some applications, programmable processor 10 is worked with primary processor 18.Processor 10 can be the slave unit or the one parts of primary processor 18.In other was used, programmable processor 10 can not worked with other processor 18 yet.System represented among Fig. 1 just is used for illustrative purposes, does not limit the scope of the invention.In addition, these application can comprise Fig. 1 other parts of not showing, for example, static RAM, bus controller, interruptable controller and input-output device.
Primary processor 18 can detect idle output 17.By detecting idle output 17, primary processor 18 measurement processor 10 are in running order or are in idle condition.Primary processor 18 can further adopt the mode of inserting wakeup signal 84 to wake processor 10.
The instruction that is stored in the instruction cache 16 can be encased in the first order of streamline 14, and can be by the processing of subsequent stages.At different levels can almost the processing simultaneously with other level.In a clock period of system, data can transmission between streamline 14 at different levels.The result of instruction can appear at the end of streamline 14 in the mode of high-speed and continuous.
Fig. 2 has illustrated the streamline 14 of giving an example.For example, streamline can have Pyatyi: instruction is obtained (IF), instruction decode (DEC), address arithmetic (AC), carries out (EX) and is write back (WB).Instruction can be obtained from storer by acquiring unit 20 in the first order (IF) or obtain from instruction buffer 16, and deciphers 22 during the second level (EDC) in address register 24.In the next clock period, this result transmission is to the third level (AC), and in the third level, data address generator 26 calculates any storage address that is used for executable operations.In execution level (EX), performance element 28 can be operated, for example, and the addition of two numbers or multiply each other.In the end in the one-level (WB), write back to this result in the data-carrier store again or write back in the data register 30.
The application that has comprised programmable processor 10 can run into the situation that task that processor 10 will not carry out does not have consumed power yet.Under this situation, help processor 10 and enter into lower powered idle pulley.The startup of idle pulley can be passed through, for example, user instruction processor 10 enters into low power state, perhaps, enter into low power state by primary processor 18 instruction processing unit 10 after processor 10 has no longer included a period of time of will carrying out of task, but scope of the present invention not merely is limited in this on the one hand.Fig. 3 has illustrated that the processor 10 of in running order (50) can enter into the processing of low-power idle pulley.When prompting idle condition (52), for example, can propose by the user or by primary processor 18, processor 10 can disabled interrupt (54).A kind of method of disabled interrupt is to carry out the instruction of CLI (remove and interrupt), and this instruction has changed the employed interrupt mask of interruptable controller.Owing to carried out the CLI instruction, processor 10 can be ignored interruption, enters into idle condition simultaneously.Processor 10 also can be ignored interruption when being in idle condition.
Processor 10 is placed on known idle condition (56) subsequently.The processor 10 that is arranged at known idle condition allows processor 10 to exit from idle mode in the last moment of this known state, and does not need to carry out the operation that resets.Fig. 3 has shown a kind of method (56) that processor 10 is arranged at idle condition.Idle request can propose (52) by sending idle instruction to streamline 14.What just as discussed below, idle instruction can produce idle marker position 80 is provided with (see figure 4) (58).Idle marker position 80 can point out this processor 10 to enter into idle condition.Idle marker position 80 can be stored in storage component part, for example register 102 (see figure 4)s.
The back of idle instruction can be system synchronization (SSYNC) instruction (60) in streamline 14.In general, the SSYNC instruction can specify the processing operation of all waits to finish before next one operation beginning.Therefore, the SSYNC instruction allows the instruction in streamline 14 to occur, but can suspend streamline 14 obtains new instruction, the affirmation 82 (seeing Fig. 1 and Fig. 4) until the system of receiving from command high speed buffer device 16.The affirmation 82 of system can represent that the system operation of all waits all finishes.In other words, send the SSYNC signal by streamline 14 and can suspend this signal streamline 14 afterwards, make IF level, DEC level and AC level no longer work, the instruction that allows simultaneously to be waited for before this signal can be finished its execution.For example, an instruction before the SSYNC instruction is that the Request System bus is not suspended, but allows to finish this execution, thereby preserves the agreement of bus.SSYNC can suspend in the EX level, instructs until system validation SSYNC.
SSYNC instruction can be carried out and the irrelevant operation of the processor 10 that is in idle condition, but when carrying out when the idle instruction combined command (58) of idle marker position 80 is set, SSYNC instructs will produce idle condition, as following shown.SSYNC instruction can produce the known state of processor 10, because SSYNC instruction time-out streamline 14, until all operations of finishing before the SSYNC instruction.In addition, before SSYNC instruction arrived the WB level, all or the part operation in the streamline can " be deleted " or be cancelled in the SSYNC instruction.
System validation signal 82 can be used for instruction processorunit 10 and other system unit such as primary processor 18 and bus controller has been carried out the SSYNC instruction of above being narrated.In case processor 10 receives system validation signal 82, the SSYNC instruction can enter the WB level usually, and finishes its operation.Yet, because idle instruction has been provided with idle marker position 80 (58), suspend, and the SSYNC instruction is retained in the EX level so streamline 14 can kept.System validation signal 82 can be accepted (62) by idle controller 11.In addition, can detect the state (64) of idle marker position 80, insert (assert) idle output signal (66) thereby export 17 places in the free time.As long as inserted idle output 17, then streamline 14 can kept the state that suspends.Because streamline 14 is in halted state, can suspends in the EX level so SSYNC instructs, and cannot enter into the WB level.
Idle controller 11 can be removed idle marker position (68).The logical circuit of idle controller 11 can be carried out the detection (64) of idle marker position 80, idle output 17 (66) is set and removes idle marker position 80 (68), just as discussed below.In addition, primary processor 18 can detect idle output 17, and then can measurement processor 10 whether be in idle condition, and closes the clock (70) that offers processor 10.Except clock was closed, primary processor 18 can reduce to offer the power (70) of processor 10, for example, supply voltage is arranged to " electric pressure of idle pulley ".The idle pulley voltage level is general all less than " voltage level of mode of operation " of processor 10 energy operate as normal, still also is enough to keep the duty of register.Because the consumption of power is square proportional with voltage, so in this special embodiment, be reduced to idle pulley voltage level (for example, 0.7 volt) from mode of operation voltage level (for example, 1.3 volts) and just can save appreciable power.Processor 10 can adopt clock to cut out the mode that reduces with power power-supply to be in lower powered idle pulley.
Fig. 4 is the logical diagram according to the idle controller 11 of the embodiment of the invention.Fig. 4 has illustrated the technology that realizes that above-mentioned discussion method adopts.When processor 10 was being worked, all positions all can not obtain confirming among the figure.Idle marker position 80 can not be provided with, and idle output pin 17 can not confirmed.When idle instruction entered into the WB level, a data bit can obtain at label 96 places confirming.This can promptly be latched by the memory element such as register 102.In the next clock period, register 102 can be provided with idle marker position 80.Because or door 98 feedback, can be so that idle marker position 80 keeping this confirmation, after free time output 17 obtains confirming.
Confirm to have received with door (80) the affirmation signal of SSYNC just can produce high data bit when idle marker position 80, this data bit latchs in register 94.In the next clock period, idle output 17 can be set.High free time output 17 can anti-phasely be transferred to afterwards and door 100, and this just will be arranged in the register 102 less than the position of confirming, thereby can dispose idle marker position 80 in a clock period subsequently.Because or door 90 feedback can make idle output 17 keep height, after call signal 84 is identified.Before call signal 84 was identified, processor 10 just can remain the free time.
Fig. 5 has illustrated that a kind of processor that is applicable to turns back to the embodiment of duty method.Primary processor 18 can recover to provide clock to processor 10, also power power-supply can be returned to operation level, for example, and on the voltage level (110) that power power-supply is arranged on mode of operation.Primary processor 18 also can produce wakeup signal 84 (112).As shown in Figure 4, wakeup signal 84 be transferred to and door 92 after can be anti-phase, goes out and asserts and (deassert) dispose idle carry-out bit 17 (114) in the clock period subsequently latching data bit in register 94.
Disposing idle output 17 can make streamline 14 avoid suspending.Because sent the affirmation signal 82 of system, the SSYNC instruction enters into the WB level, deleted in the streamline 14 all operations (116) at this moment, by obtaining in command high speed buffer device 16, make the instruction stream that enters streamline 14 start working again (118) immediately following the instruction after the SSYNC instruction.Immediately following the instruction after the SSYNC instruction generally is the instruction of STI (recovering to interrupt), and it recovers interrupt mask (120).Subsequently, streamline 14 comes processing instruction (122) with the order of program, in other words, in case after waking, work is restarted in the position that processor 10 can be left when processor 10 enters idle pulley.
When being in idle pulley, processor 10 can be ignored interruption.The interruption (110) that processor 10 also can be ignored before clock recovery to be received.After clock recovery, can gather interruption, but can not work, until interrupting recovering (120).Interrupting recovering (120) afterwards, can come handling interrupt with the method for routine by the interruptable controller of processor 10.
Fig. 6 has illustrated that another kind makes processor return to the embodiment of duty.Fig. 6 is similar to Fig. 5, interrupts (126) except primary processor 18 produces.Interruption can occur in and shown in Figure 6 recover (120) any one-level before with interrupt mask afterwards in clock recovery (110).As above mentioned, when control is when being transferred to interrupt service routine (124) by interruptable controller, can gathers and interrupt but cannot work before interrupting recovering (120).Therefore, processor 10 can be carried out the instruction of interrupt service routine (124), rather than carries out processing instruction with the order of program.
Some embodiments of the present invention have been discussed.The foregoing description and other embodiment are among the scope of following claim.

Claims (31)

1. method of operating programmable processor comprises:
Forbid programmable processor is interrupted;
Programmable processor is arranged at idle condition;
The output terminal of programmable processor assert the expression idle condition signal; And
The control programmable processor is ignored at described programmable processor and is placed idle condition and ignore interruption during the duty that enters of programmable processor after this idle condition, before interrupt recovering.
2. method according to claim 1 is characterized in that, further is included in the clock signal input of forbidding in the idle condition programmable processor.
3. as method as described in the claim 2, it is characterized in that, further be included in the clock signal input back of forbidding programmable processor and reduce power supply programmable processor.
4. method according to claim 1 is characterized in that the step that programmable processor is arranged at idle condition comprises:
In described programmable processor, idle marker is set;
The disposal system synchronic command, described system synchronization instruction causes the generation of system validation signal; And
In case detect after idle marker and the system validation signal, programmable processor be arranged to idle condition.
5. as method as described in the claim 4, it is characterized in that the step of described disposal system synchronic command makes programmable processor to enter idle condition before producing the system validation signal.
6. method according to claim 1 is characterized in that described programmable processor comprises execution pipeline, and this method further is included in described programmable processor is placed all operations of deleting after the idle condition at execution pipeline.
7. method according to claim 1 is characterized in that, further comprises the reception wakeup signal.
8. device that comprises programmable processor, described programmable processor comprises:
Execution pipeline, described execution pipeline comprises acquiring unit, is used to obtain pending instruction;
And
The idle controller that is coupled with described execution pipeline;
Wherein, described idle controller is applicable in response to idle instruction and the instruction of system synchronization subsequently, suspends execution pipeline by acquiring unit is not worked, and described idle controller also is applicable in response to the signal that recovers programmable processor from idle condition and makes acquiring unit work; And
Interruption during the duty that programmable processor entered before wherein said programmable processor was applicable to and ignores after an idle condition and this idle condition, interrupts recovering.
9. as device as described in the claim 8, it is characterized in that described idle controller comprises output terminal, described idle controller is applicable to according to idle instruction and the instruction of system synchronization subsequently, the signal of asserting an indication idle condition at output terminal.
10. as device as described in the claim 9, it is characterized in that described output terminal and memory device are coupled.
11. as device as described in the claim 8, described idle controller comprises wakes input end, described idle controller is applicable to according to ending the time-out of execution pipeline waking the received signal of input end.
12. as device as described in the claim 8, it is characterized in that, described idle controller is used for according to idle instruction the idle marker position being set before suspending described execution pipeline, and instructs according to system synchronization after suspending described execution pipeline and remove described idle marker position.
13. the system with two programmable processors, it comprises:
First programmable processor, described first programmable processor is used to enter idle condition and the interruption that receives during the duty of idle output signal, described first programmable processor first programmable processor before also being used to ignore after idle condition and idle condition, interrupting recovering is provided;
Second programmable processor, it and described first programmable processor are coupled;
Be used for providing the clock controller of clock signal to described first programmable processor; And
Static RAM, it and described first programmable processor are coupled;
Wherein, described second programmable processor does not work the clock signal that offers described first programmable processor according to detected idle output signal.
14., it is characterized in that described first programmable processor comprises execution pipeline and the idle controller that is coupled with described execution pipeline as system as described in the claim 13.
15. as system as described in the claim 13, it is characterized in that described second programmable processor is used for providing wakeup signal to described first programmable processor, and, when described first programmable processor detected wakeup signal, described first programmable processor was used to exit from idle status.
16. a method of operating programmable processor, it comprises:
Make described programmable processor enter idle condition and ignore after idle condition and idle condition, interrupt recovering before the duty of programmable processor during the interruption that receives;
The notice programmable processor exits from idle status; And
At least one interruption after the operation programmable processor exits from idle status with response.
17., it is characterized in that, further be included under the operate as normal level, to described programmable processor power supply as method as described in the claim 16.
18. as method as described in the claim 16, it is characterized in that, further comprise:
After entering idle condition, programmable processor provides interruption to programmable processor;
The operation programmable processor is to catch described interruption; And
After programmable processor exits from idle status, transfer control in the interrupt service routine to handle described interruption.
19. as method as described in the claim 16, it is characterized in that described programmable processor comprises execution pipeline, this method further is included in the notice programmable processor and deletes all operations in execution pipeline after exitting from idle status.
20. as method as described in the claim 19, it is characterized in that, obtain an instruction by described execution pipeline after further being included in all operations of deleting in execution pipeline.
21. as method as described in the claim 16, it is characterized in that described programmable processor provides idle output signal, this method is deleted idle output signal after further being included in and notifying described programmable processor to exit from idle status.
22. a method of operating programmable processor, it comprises:
Operate programmable processor with duty;
Described programmable processor is arranged on idle condition; And
Make the power consumption of described programmable processor in idle condition less than the power consumption in the duty, and described programmable processor ignore after idle condition and this idle condition and interrupt recovering before the duty of programmable processor at least one interruption.
23. as method as described in the claim 22, it is characterized in that, further be included in described programmable processor is placed the clock signal input of forbidding after the idle condition described programmable processor.
24. as method as described in the claim 23, it is characterized in that, further be included in the power supply that reduces after the clock signal input of forbidding described programmable processor programmable processor.
25., it is characterized in that described programmable processor comprises execution pipeline, and when described programmable processor was in idle condition, described execution pipeline did not carry out any operation as method as described in the claim 22.
26. as method as described in the claim 22, it is characterized in that, further comprise the signal that when described programmable processor is in idle condition, sends an indication idle condition.
27. as method as described in the claim 22, it is characterized in that, further comprise:
When described programmable processor is in idle condition, send wakeup signal to described programmable processor;
Make described programmable processor turn back to duty; And
Make described programmable processor handling interrupt.
28. as method as described in the claim 27, it is characterized in that described programmable processor comprises execution pipeline, the step that makes described programmable processor turn back to duty further comprises all operations of deletion in execution pipeline.
29. a method of operating programmable processor is characterized in that it comprises:
Programmable processor is set to idle condition, wherein after idle condition and this idle condition, interrupt recovering before during the duty of programmable processor described programmable processor ignore and do not act on interruption;
When programmable processor is in idle condition, catch at least one interruption;
Make described programmable processor return duty; And
At least one interruption that processing is caught during programmable processor is in idle condition.
30. method as claimed in claim 29 is characterized in that, described programmable processor comprises clock, wherein closes the back and received at least one interruption before clock recovery at clock.
31. method as claimed in claim 29 is characterized in that, receives at least one interruption after clock recovery.
CNB018187986A 2000-11-13 2001-11-13 Idle state of processor Expired - Fee Related CN100476693C (en)

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