CN100470793C - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

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Publication number
CN100470793C
CN100470793C CNB2006100592086A CN200610059208A CN100470793C CN 100470793 C CN100470793 C CN 100470793C CN B2006100592086 A CNB2006100592086 A CN B2006100592086A CN 200610059208 A CN200610059208 A CN 200610059208A CN 100470793 C CN100470793 C CN 100470793C
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Prior art keywords
chip
semiconductor
semiconductor substrate
connection pads
wiring plate
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Expired - Fee Related
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CNB2006100592086A
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Chinese (zh)
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CN1835229A (en
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波多野正喜
高冈裕二
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Sony Corp
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Sony Corp
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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04C—STRUCTURAL ELEMENTS; BUILDING MATERIALS
    • E04C2/00—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels
    • E04C2/02—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials
    • E04C2/26—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups
    • E04C2/284—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups at least one of the materials being insulating
    • E04C2/292—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups at least one of the materials being insulating composed of insulating material and sheet metal
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor chips to each other, and a plurality of chip-connection pads connected to the chip-to-chip interconnection; and a wiring board that has a plurality of lands of which pitch is larger than a pitch of the chip-connection pads, wherein a major surface of each of the plurality of semiconductor chips is connected to the chip-connection pads via a first connector so that the plurality of semiconductor chips are mounted on the semiconductor substrate, and an external-connection pad is formed on the major surface other than a region facing the semiconductor substrate, and is connected to the land on the wiring board via a second connector.

Description

The method of semiconductor device and manufacturing semiconductor device
Technical field
The present invention relates to be called as semiconductor device and the manufacture method thereof of system in the so-called encapsulation (system in package), a plurality of semiconductor chips are installed in the packing forms in the system in encapsulation.The present invention relates more specifically to a kind of like this semiconductor device and manufacture method thereof, and this semiconductor device has such structure, wherein Semiconductor substrate is used to be electrically connected a plurality of semiconductor chips.
Background technology
Electronic equipment is just requiring semiconductor chip used in the equipment also to have higher function towards the recent trend of higher function development.But, attempt the large scale exploitation of the higher functional requirement chip of method (wherein the function system of large scale is to be formed on the chip) realization with system on chip (SoC), caused long and problem with high costs of construction cycle.Therefore proposed the method for system (SiP) in the encapsulation, wherein a plurality of semiconductor chips are mounted on the plug-in type substrate (interposer substrate) and assembly gained is used as package parts.
For example, the open No.2004-79745 (hereinafter to be referred as patent documentation 1) of Japan Patent discloses a kind of SiP method, and the ground flip chip bonding that wherein keeps to the side in plug-in type silicon substrate top is installed a plurality of chips.
To this SiP structure be described with reference to Figure 16.Plug-in type silicon substrate 53 has surperficial interconnection layer 50 and throughhole portions 56.The surface interconnection layer 50 have be used for the trickle interconnection (interconnection that for example has sub-micro rice noodles and space) that between a plurality of chips, interconnects and the little spacing that is used to be connected to chip (for example 60 μ m or littler spacing) pad.Throughhole portions 56 is by for example electroplating the current-carrying part that forms as follows: fill along its thickness direction and pass the through hole of plug-in type silicon substrate 53 and the dielectric film of planting between the sidewall of through hole and current-carrying part.The pad of throughhole portions 56 guidings from surperficial interconnection layer 50 (rearranges to forming, rearranged) interconnection of the pad 49 on the lower surface (apparent surface on the surface of chip is installed) of plug-in type silicon substrate 53, and have relatively large spacing (for example 100 μ m or bigger spacing), allow to be connected to the organic substrate 57 of plug-in type.
A plurality of semiconductor chip 2a and 2b are connected on the surperficial interconnection layer 50 of plug-in type silicon substrate 53 by solder bump (solder bump) 51 flip chip bondings, so that be installed on the plug-in type silicon substrate 53.With filling out slit between resin material (underfill resin material) 54 filling semiconductor chip 2a and 2b and the plug-in type silicon substrate 53 in the end.
Plug-in type silicon substrate 53 is electrically connected and is installed on organic plug-in type substrate 57 by solder bump 58 on the pad on the face that is provided in the following table 49, the organic plug-in type substrate 57 and weld zone (lands) 59.With filling out the slit that resin material 55 is filled between plug-in type silicon substrate 53 and the organic plug-in type substrate 57 in the end.
In addition, as another technology, the open flat 8-250653 of No. (hereinafter to be referred as patent documentation 2) of Japan Patent has disclosed the SiP method that a kind of use does not have the plug-in type silicon substrate of throughhole portions.Figure 17 shows the structure of this SiP.A plurality of semiconductor chip 62a and 62b are connected to plug-in type silicon substrate 61 by solder bump 64.Plug-in type silicon substrate 61 is connected to organic plug-in type substrate 63 by the same surface that semiconductor chip 62a and 62b are installed via solder bump 65.
Summary of the invention
But, the SiP method of patent documentation 1 need form the through hole that penetrates plug-in type silicon substrate 53 and formation and be buried in current-carrying part 56 in the through hole.Be used to form the silicon etching of through hole and will spend expensive and long period, the problem that this has caused the manufacturing cost of entire semiconductor device to increase by electroplating deposition current-carrying part 56 in through hole.
In addition, plug-in type silicon substrate 53 meets the chip of design rule of semiconductor chip 2a and 2b to chip interconnect layer 50 except fine design rule, also have pad 49 on its lower surface, pad 49 has the big spacing of the design rule (design rule) that meets organic plug-in type substrate 57.Because pad 49 has so big spacing, it is big that the size of plug-in type silicon substrate 53 in its in-plane is easy to become, and this has also caused expensive.
In the SiP of patent documentation 2 method, plug-in type silicon substrate 61 has the pad that is used to be connected to organic plug-in type substrate 63 on it is equipped with the same surface of semiconductor chip 62a and 62b.Semiconductor chip 62a and 62b are connected to organic plug-in type substrate 63 by the interconnection that is formed on the plug-in type silicon substrate 61.Therefore, it is big that the interconnection length between semiconductor chip 62a and 62b and the organic plug-in type substrate 63 is easy to become, and this causes the signal transmission delay between semiconductor chip 62a and 62b and the organic plug-in type substrate 63 easily.
In addition, plug-in type silicon substrate 61 is except being used for semiconductor chip 62a and the 62b interconnection connected to one another, also having being used for semiconductor chip 62a and 62b are connected to the interconnection of outside (being organic plug-in type substrate 63 in this embodiment).These existence that are drawn out to outside interconnection have reduced the flexibility of chip to the route layout of chip interconnect, so chip is easy to change greatly to the length of chip interconnect, this is easy to cause the signal transmission delay between semiconductor chip 62a and the 62b.
Consider the problems referred to above and made the present invention that its purpose is the semiconductor device and the manufacture method thereof that a kind of cheapness are provided and can suppress signal transmission delay.
Following examples have been adopted in order to address the above problem the present invention.
Particularly, semiconductor device according to an embodiment of the invention comprises: a plurality of semiconductor chips; Semiconductor substrate has on its same surface and is used for chip that described a plurality of semiconductor chips are electrically connected to each other to chip interconnect and be connected to a plurality of chip connection pads of described chip to chip interconnect; And wiring plate, having a plurality of weld zones, the spacing of described weld zone is greater than the spacing of described chip connection pads.The first type surface of each of described a plurality of semiconductor chips is connected to described chip connection pads by first connector, so that described a plurality of semiconductor chips are installed on the Semiconductor substrate.On the described first type surface except that in the face of forming external connection pads the zone of described Semiconductor substrate and being connected to described weld zone on the described wiring plate by second connector.
In addition, semiconductor device according to another embodiment of the invention comprises: a plurality of semiconductor chips; And Semiconductor substrate, on its same surface, have and be used for chip that described a plurality of semiconductor chips are electrically connected to each other to chip interconnect and be connected to a plurality of chip connection pads of described chip to chip interconnect.The first type surface of each of described a plurality of semiconductor chips is connected to described chip connection pads by connector, so that described a plurality of semiconductor chips are installed on the Semiconductor substrate.Forming a plurality of external connection pads on the described first type surface except that facing the zone of described Semiconductor substrate, the spacing of described external connection pads is greater than the spacing of described chip connection pads.
In addition, the method for manufacturing semiconductor device according to still another embodiment of the invention may further comprise the steps: form chip to chip interconnect and a plurality of chip connection pads that is connected to described chip to chip interconnect on the same surface of Semiconductor substrate; And except facing the zone of described Semiconductor substrate, forming a plurality of external connection pads on the first type surface of a plurality of semiconductor chips.External connection pads has the spacing greater than the spacing of described chip connection pads.Described method is further comprising the steps of: form a plurality of weld zones on wiring plate, the spacing of described weld zone equals the spacing of described external connection pads; Each described first type surface of described a plurality of semiconductor chips is connected to described chip connection pads by first connector, so that described a plurality of semiconductor chips are installed on the described Semiconductor substrate; And the described external connection pads on the described semiconductor chip is connected to described weld zone on the described wiring plate by second connector.
Described a plurality of semiconductor chip is electrically connected to each other and is directly connected to described wiring plate to chip interconnect by the chip that is formed on the described Semiconductor substrate, and the centre does not have Semiconductor substrate.
Semiconductor substrate only has a plurality of semiconductor chips function connected to one another.Wiring plate be welded on the surperficial facing surfaces that is formed with the weld zone of semiconductor chip, form the weld zone of the design rule meet the wiring plate that is called as so-called motherboard (motherboard).Therefore wiring plate is serving as the plug-in part (interposer) of interconnect semiconductor chip and motherboard.
Be formed at trickle and closely spaced electrode pad on the first type surface of semiconductor chip and be connected to (rearrange into) external connection pads, this external connection pads has size and the spacing that meets outside design rule.
Needn't on Semiconductor substrate, form the pad that its bigger size and spacing meet the design rule of wiring plate and be used to be connected to wiring plate.That is the chip connection pads that only has the more fine sizes that is used to be connected to semiconductor chip and spacing on the Semiconductor substrate is just enough as pad.Therefore, can reduce the planar dimension of Semiconductor substrate, this makes the cost of Semiconductor substrate reduce.
Semiconductor chip is connected to outside (wiring plate) by the external connection pads that directly is arranged on the semiconductor chip, and the centre does not need Semiconductor substrate.Therefore, with above-mentioned patent documentation 2 (wherein, semiconductor chip is connected to wiring plate by Semiconductor substrate) compare, can reduce the length of the interconnection between semiconductor chip and the wiring plate (wiring board), this can suppress the delay of signal transmission between semiconductor chip and the wiring plate.
In addition, with regard to interconnection, only have chip on the Semiconductor substrate to chip interconnect, and be not used in the interconnection that semiconductor chip is connected to wiring plate.Therefore, can concentrate chip (collectively) to be formed on the specific region on the Semiconductor substrate to chip interconnect, and its highway route design can not be subjected to being used for semiconductor chip is connected to the interference of the interconnection of wiring plate.Therefore, can reduce the length of chip to chip interconnect, this makes it possible to suppress the delay of the signal transmission between the semiconductor chip.
If Semiconductor substrate is placed in the cavity (hollow) that is formed in the wiring plate, the thickness that just can suppress entire semiconductor device increases.In addition, if by providing resin material that Semiconductor substrate is fixed to wiring plate in the cavity, just can reduce to act on stress on the welding portion by first and second connectors, this can improve the soldering reliability of welding portion.
In addition, if before semiconductor chip is welded to Semiconductor substrate, in advance Semiconductor substrate is placed in the cavity that is formed in the wiring plate, can use so and the similar method of existing installation method, wherein, select semiconductor chip one by one, be installed on the Semiconductor substrate to use existing erecting device such as vacuum suction instrument (vacuum suction tool).This method has been avoided the reduction of cost increase and installation effectiveness.
According to embodiments of the invention, Semiconductor substrate only has the function that a plurality of semiconductor chips are electrically connected to each other, and the electrode pad on the semiconductor chip is not directed into the function of the pad that is used to be connected to the outside spacing with amplification.Therefore, needn't form the through hole that penetrates Semiconductor substrate and be buried in conductive member in the through hole, so can corresponding reduction technology cost and time.As a result, can reduce the cost of entire semiconductor device.Semiconductor chip is connected to outside (wiring plate) by the external connection pads that directly is arranged on the semiconductor chip, and the centre does not need Semiconductor substrate.Therefore, can reduce the length of the interconnection between semiconductor chip and the wiring plate, this can suppress the delay of the signal transmission between semiconductor chip and the wiring plate.In addition, with regard to interconnection, only have chip on the Semiconductor substrate to chip interconnect, and be not used in the interconnection that semiconductor chip is connected to wiring plate.Therefore, can concentrate chip on the specific region that is formed on the Semiconductor substrate to chip interconnect, and its highway route design can not be subjected to being used for semiconductor chip is connected to the interference of the interconnection of wiring plate.Therefore, can reduce the length of chip to chip interconnect, this makes it possible to suppress the delay of the signal transmission between the semiconductor chip.
Description of drawings
Fig. 1 is the partial cross section's perspective view according to the semiconductor device of first embodiment of the invention.
Fig. 2 is the sectional view according to the semiconductor device of first embodiment.
Fig. 3 is first sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 4 is second sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 5 is the 3rd sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 6 is the 4th sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 7 is the 5th sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 8 is the 6th sectional view according to the manufacturing step of the semiconductor device of first embodiment.
Fig. 9 is the partial cross section's perspective view according to the semiconductor device of second embodiment of the invention.
Figure 10 is the sectional view according to the semiconductor device of second embodiment.
Figure 11 is first sectional view according to the manufacturing step of the semiconductor device of second embodiment.
Figure 12 is second sectional view according to the manufacturing step of the semiconductor device of second embodiment.
Figure 13 is the sectional view according to the semiconductor device of third embodiment of the invention.
Figure 14 is the plane graph that change is shown, and wherein a plurality of semiconductor chips are installed on the Semiconductor substrate.
Figure 15 is a sectional view, shows the semiconductor device as the change of the embodiment of the invention.
Figure 16 is a sectional view, shows the semiconductor device as the first conventional example.
Figure 17 is a sectional view, shows the semiconductor device as the second conventional example.
Embodiment
To lead to reference to the accompanying drawings and be described in more detail below embodiments of the invention.Should be pointed out that to the invention is not restricted to following embodiment, but can make many changes based on technological thought of the present invention.
[first embodiment]
Fig. 1 is the partial cross section's perspective view that illustrates according to the semiconductor device 1 of first embodiment of the invention.Fig. 2 is the sectional view that semiconductor device 1 is shown.
The wiring plate 7 that semiconductor device 1 comprises Semiconductor substrate 3, be installed in a plurality of semiconductor chip 2a on the Semiconductor substrate 3 and 2b and be connected to semiconductor chip 2a and 2b.
Semiconductor substrate 3 has on its same surface and is used for chip that semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 and be connected to a plurality of chip connection pads 5 of chip to chip interconnect 4.
The first type surface of semiconductor chip 2a and 2b (form IC surface) is connected to chip connection pads 5 on the Semiconductor substrate 3 by first connector 8 and 9.So semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 by the chip that is formed on the Semiconductor substrate 3.The space around welding portion between semiconductor chip 2a and 2b and the Semiconductor substrate 3 is filled out resin material 14 end of by and is filled, and this resin material 14 is being protected welding portion.
A plurality of external connection pads 13 are formed at above the first type surface of semiconductor chip 2a and 2b on the zone outside the zone of Semiconductor substrate 3.A plurality of weld zones 6 are formed on the wiring plate 7.The spacing of the chip connection pads 5 on the gap ratio Semiconductor substrate 3 of external connection pads 13 and weld zone 6 ( first connector 8 and 9 spacing) is big.External connection pads 13 is connected to weld zone 6 by second connector 12, so semiconductor chip 2a and 2b are electrically connected to wiring plate 7.The space around welding portion between semiconductor chip 2a and 2b and the wiring plate 7 is filled out resin material 15 end of by and is filled, and this resin material 15 is being protected welding portion.
One example of the manufacture method of semiconductor device 1 below will be described.
With reference to figure 3, Semiconductor substrate 3 is for example silicon substrate.What form on one surface is chip to chip interconnect 4 and is connected to a plurality of chip connection pads 5 of chip to chip interconnect 4.Use the technology and equipment of typical semi-conductor wafer technology to form chip to chip interconnect 4 and chip connection pads 5.Chip to chip interconnect 4 have sandwich construction for example insulating barrier be plugged between the interconnection layer.As the material of chip to chip interconnect 4 and chip connection pads 5, for example copper or aluminium just can.When Semiconductor substrate 3 was formed by silicon, insulating barrier can be formed by silica or silicon nitride, perhaps can be formed by the resin material such as polyimides.Chip can be formed by individual layer to chip interconnect 4.Chip has the pattern (line-and-space pattern) (minimum line width) in line on sub-micron (0.1 to the 1 μ m) magnitude and space to chip interconnect 4.Chip connection pads 5 has the several micron spacing in 60 mu m ranges.Typical semiconducter process can easily be formed on interconnection and the pad that has such design rule on the Semiconductor substrate 3 (for silicon substrate).
Semiconductor substrate 3 is not limited to silicon substrate, but can be the another kind of Semiconductor substrate that is made of germanium, compound semiconductor etc.In the present embodiment, the semiconductor chip 2a and the 2b that are installed on the Semiconductor substrate 3 are silicons, therefore use silicon substrate as Semiconductor substrate 3, are complementary so that guarantee the linear expansion coefficient between semiconductor chip 2a and 2b and the Semiconductor substrate 3.If Semiconductor substrate 3 has identical or approaching linear expansion coefficient with the semiconductor chip 2a that is mounted thereon with 2b, just can suppress when the two stands temperature cycles, to act on the stress on the welding portion, this can improve soldering reliability.Therefore preferred semiconductor substrate 3 and semiconductor chip 2a and 2b are made of same material or are made of the material with approaching linear expansion coefficient.
Then be formed on the chip connection pads 5 with reference to figure 4, the first connectors 9.First connector 9 is by the hemisphere solder bump of for example electroplating or printing forms.First connector 9 can be formed by the metal or alloy outside the scolder, and its shape can be a cylindricality.
After forming first connector 9, use the back side (being formed with the apparent surface of chip) of back grinder (back grinder) polishing semiconductor substrate 3, so Semiconductor substrate 3 has been thinned to the surface of chip interconnect 4, chip connection pads 5 and first connector 9.Subsequently, use cleavage saw, laser or another kind of means, make Semiconductor substrate 3 be divided into single chip along its thickness direction cutting semiconductor substrate 3.
Then with reference to figure 5, a plurality of (being two in the present embodiment) semiconductor chip 2a and 2b are soldered to Semiconductor substrate 3 through cleavage by first connector 8 and 9.
The first type surface of each semiconductor chip 2a and 2b (form IC surface) has interconnection 10 and a plurality of pad 11 that is connected to interconnection 10 on it.The electrode pad (not shown) of semiconductor chip 2a and 2b 10 is connected to pad 11 by interconnecting, and pad 11 has the spacing bigger than the spacing of electrode pad.That is electrode pad is rearranged is pad 11.Interconnection 10 and pad 11 are to form chip and form in the step of the step of chip interconnect 4 and chip connection pads 5 being similar on Semiconductor substrate 3.Pad 11 on semiconductor chip 2a and the 2b is identical with the number that the pad 5 on the Semiconductor substrate 3 has identical spacing and pad 11 and pad 5.
Pad 11 on semiconductor chip 2a and the 2b has first connector 9 that forms on the chip connection pads 5 that first connector (for example solder bump), 8, the first connectors 8 are similar to Semiconductor substrate 3 on it.Heat fused connector 8 and 9 when connector 8 and 9 contacts with each other, this makes connector 8 and 9 be welded to one another.So the interconnection 10 on semiconductor chip 2a and the 2b is electrically connected to chip on the Semiconductor substrate 3 to chip interconnect 4.So two semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 by the chip on the Semiconductor substrate 3.
Gap between Semiconductor substrate 3 and semiconductor chip 2a and the 2b is filled out resin material 14 end of with and is filled, thereby covers near the welding portion first connector 8 and 9, and this has protected welding portion to avoid the influence of stress, dust, water etc.Fill out resin material 14 in order to form the end, for example liquid or paste thermosetting resin are provided in the gap between Semiconductor substrate 3 and semiconductor chip 2a and the 2b, make chip 2a and 2b be positioned at substrate 3 tops, the resin that hot curing then provided.
Except being used to be connected to the pad 11 of Semiconductor substrate 3, each semiconductor chip 2a and 2b also have a plurality of external connection pads 13 on the same surface that forms pad 11.External connection pads 13 forms simultaneously with forming pad 11, and is connected to interconnection 10.External connection pads 13 is positioned at semiconductor chip 2a and 2b goes up except that in the face of on the zone the zone of Semiconductor substrate 3, particularly is positioned on the marginal portion of semiconductor chip 2a and 2b.External connection pads 13 has greater than the size of pad 11 and spacing (for example 100 μ m or bigger spacing).External connection pads 13 is welded to wiring plate shown in Figure 67 by second connector 12.
Wiring plate 7 is the organic wiring plates such as the glass epoxy resin wiring plate.A plurality of weld zones 6 are formed on the surface of wiring plate 7.Weld zone 6 have be formed at semiconductor chip 2a and 2b on the identical spacing of external connection pads 13, and its number is also identical with external connection pads 13.What form on the apparent surface of wiring plate 7 formation weld zones 6 is a plurality of weld zones 17, and weld zone 17 has the spacing bigger than the spacing of weld zone 6. Weld zone 6 and 17 is electrically connected to each other by conductive member 18, and conductive member 18 is filled the path that is formed in wiring plate 7 and the interconnection 19.Weld zone 17 provides as resetting of weld zone 6, in having provided the spacing bigger than the spacing of weld zone 6. Weld zone 6 and 17, conductive member 18 and interconnecting 19 is made of the metal material such as copper.Interconnection 19 has sandwich construction, and insulating barrier is inserted between the interconnection layer.
The spacing of interconnection 19 line and space pattern and weld zone 6 and 17 is based on the design rule that adopts in typical organic wiring plate.For example, weld zone 6 and 17 spacing are at least 100 μ m.As wiring plate 7, can use the ceramic wiring plate rather than the organic wiring plate that constitute by aluminium oxide etc.
The cavity 16 bigger than Semiconductor substrate 3 that be planar dimension that forms in the core of wiring plate 7 is as the through hole that penetrates wiring plate 7 on its thickness direction.This cavity 16 can be formed by machine tool, laser, etching or another kind of means.
What form on the weld zone 6 of wiring plate 7 is for example as the solder bump of second connector 12.For example, utilize soldered ball support (mounter) soldered ball to be fixed on the weld zone 6, make it to become hemisphere by solder reflow subsequently by shifting (transfer) method or another kind of method.Perhaps, second connector 12 can be the post metal salient point that forms by plating, printing etc.
Semiconductor substrate 3 places cavity 16, the second connectors, the 12 contact semiconductor chip 2a of wiring plate 7 and the external connection pads 13 on the 2b.In this state, second connector, 12 heat fused, the external connection pads on semiconductor chip 2a and the 2b 13 is connected to weld zone 6 on the wiring plate 7 by second connector 12.So just obtained the semiconductor device 1 shown in Fig. 1 and 2.
Two semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 by the chip that is formed on the Semiconductor substrate 3, and are directly connected to wiring plate 7, and the centre does not have Semiconductor substrate 3.
Wiring plate 7 be welded on the surperficial facing surfaces of semiconductor chip 2a and 2b, form the weld zone 17 of the design rule that meets the wiring plate that is called as so-called motherboard.Therefore wiring plate 7 has played the function of the plug-in part of interconnection semiconductor chip 2a and 2b and motherboard.Semiconductor substrate 3 only has the semiconductor chip of making 2a and 2b function connected to one another.
As a result, the trickle and closely spaced electrode pad that is formed on the first type surface of semiconductor chip 2a and 2b 10 etc. is connected to the weld zone 17 that (rearranging) size and spacing meet the design rule of motherboard by interconnecting.
What form on the weld zone 17 of wiring plate 7 is connector such as soldered ball or metal salient point, and weld zone 17 is connected to weld zone and the interconnection that is formed on the motherboard by connector.Except semiconductor device 1, many parts (other semiconductor device, resistor, capacitor, connector etc.) have been installed also on motherboard.These parts are electrically connected to semiconductor device 1 by the interconnection that is formed on the motherboard.
As the another kind of structure of semiconductor device, also has the structure that does not have wiring plate 7 as shown in figure 15.Particularly, the external connection pads 13 on semiconductor chip 2a and the 2b can be directly installed on the motherboard by the connector such as soldered ball or metal salient point.But, because the restriction of the size of chip 2a and 2b, the external connection pads 13 of semiconductor chip 2a and 2b can not have very large size and spacing.Therefore, this possibility is arranged, that is, can not be used to this direct connection to have the motherboard of big design rule.Therefore, preferred such structure, wherein the external connection pads 13 on semiconductor chip 2a and the 2b is rearranged weld zone 17 for the spacing with amplification by wiring plate 7, because this structure can avoid causing little processing of the motherboard of extra cost.
Manufacture method is not limited to above-mentioned example.As shown in Figure 7, on pad 11 and 13, form respectively after all first connectors 8 and second connector 12, can on semiconductor chip 2a and 2b, carry out welding (see figure 8) and semiconductor chip 2a and 2b and wiring plate 7 welding of passing through second connector 12 of semiconductor chip 2a and 2b and Semiconductor substrate 3 by first connector 8.
As mentioned above, in the semiconductor device 1 of present embodiment, Semiconductor substrate 3 only has the function that a plurality of semiconductor chip 2a and 2b are electrically connected to each other, and the electrode pad on semiconductor chip 2a and the 2b is not directed into the pad of the spacing with expansion to be connected to outside function.Therefore, different with conventional example shown in Figure 16, needn't form the through hole that penetrates Semiconductor substrate 3 and be buried in conductive member in the through hole, so can corresponding reduction technology cost and time.As a result, can reduce the total cost of semiconductor device 1.
In addition, needn't on Semiconductor substrate 3, form the pad that its large scale and spacing meet the design rule of wiring plate 7 and be used to be connected to wiring plate 7.That is, only having pad 5 on the Semiconductor substrate 3 just enough as pad, pad 5 is used to be connected to semiconductor chip 2a and 2b, thereby has small size and spacing.Therefore, allow Semiconductor substrate 3 to have little planar dimension.This little planar dimension makes the cost of Semiconductor substrate 3 reduce.
In addition, semiconductor chip 2a and 2b are connected to wiring plate 7 by the external connection pads 13 that directly is arranged on semiconductor chip 2a and the 2b, and the centre does not have the interconnection on the Semiconductor substrate 3.Therefore, compare with conventional example (wherein semiconductor chip 62a is connected to wiring plate 63 with 62b by Semiconductor substrate 61) shown in Figure 17, can reduce the length of the interconnection between semiconductor chip and the wiring plate, this makes it possible to suppress the delay of signal transmission between semiconductor chip and the wiring plate.
In addition, as for interconnection, the Semiconductor substrate of present embodiment 3 only has chip on it and does not have the aforesaid interconnection that is used for semiconductor chip 2a and 2b are connected to wiring plate 7 to chip interconnect 4.Therefore, can concentrate chip on the specific regions that are formed on the Semiconductor substrate 3 to chip interconnect 4, and its highway route design can not be subjected to being used for semiconductor chip 2a and 2b are connected to the interconnection interference of wiring plate 7.Therefore, can reduce the length of chip to chip interconnect 4, this makes it possible to suppress the delay of the signal transmission between semiconductor chip 2a and the 2b.
[second embodiment]
Fig. 9 is the partial cross section's perspective view that illustrates according to the semiconductor device 21 of second embodiment of the invention.Figure 10 is the sectional view that semiconductor device 21 is shown.Give identical label with part identical among first embodiment, its detailed description will be omitted.
The wiring plate 27 that the semiconductor device 21 of present embodiment comprises Semiconductor substrate 3, be installed in a plurality of semiconductor chip 2a on the Semiconductor substrate 3 and 2b and be connected to semiconductor chip 2a and 2b.
Semiconductor substrate 3 has on its same surface and is used for chip that semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 and be connected to a plurality of chip connection pads 5 of chip to chip interconnect 4.The first type surface of semiconductor chip 2a and 2b (form IC surface) is connected to chip connection pads 5 on the Semiconductor substrate 3 by first connector 8 and 9.So semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 by the chip that is formed on the Semiconductor substrate 3.
A plurality of external connection pads 13 are formed at above the first type surface of semiconductor chip 2a and 2b on the zone outside the zone of Semiconductor substrate 3.A plurality of weld zones 6 are formed on the wiring plate 27.The spacing of the chip connection pads 5 on the gap ratio Semiconductor substrate 3 of external connection pads 13 and weld zone 6 ( first connector 8 and 9 spacing) is big.External connection pads 13 is connected to weld zone 6 by second connector 12, so semiconductor chip 2a and 2b are electrically connected to wiring plate 27.
Gap between gap between Semiconductor substrate 3 and semiconductor chip 2a and the 2b and semiconductor chip 2a and 2b and the wiring plate 27 is filled out resin material 24 end of with and is filled, and is protecting welding portion between semiconductor chip 2a and 2b and the Semiconductor substrate 3 and the welding portion between semiconductor chip 2a and 2b and the wiring plate 27.
Semiconductor substrate 3 places the cavity 26 that is formed at wiring plate 27 in such a way, makes chip connection pads 5 and first connector 9 that is formed on the chip connection pads 5 be exposed to empty 26 tops.Cavity 26 is formed the depression with bottom.Resin material is provided in to be fixed in the cavity 26 between the bottom of cavity 26 inner wall surface and Semiconductor substrate 3 and the side and Semiconductor substrate 3.Provide in 26 the resin material can be by realizing with providing material 24 to provide the end to fill out resin material 24 therein between semiconductor chip 2a and 2b and Semiconductor substrate 3 and in the gap between semiconductor chip 2a and 2b and the wiring plate 27 in the cavity.Perhaps, providing before the end fills out resin material 24, can be provided for the another kind of resin material in cavity 26 independently therein.
As mentioned above, present embodiment has such structure: wherein, Semiconductor substrate 3 is buried in the wiring plate 27, so that become one with wiring plate 27.Therefore, with first embodiment (wherein, semiconductor chip 2a is only supported by wiring plate 7 by welding portion by second connector 12 with Semiconductor substrate 3 with 2b) compare, by second connector 12 act on the welding portion stress (particularly, be when wiring plate stands temperature cycles because the big organic wiring plate of linear expansion coefficient shrinks and the stress of generation) can be reduced, this can improve the soldering reliability of welding portion.In addition, because Semiconductor substrate 3 is supported among the cavity 26 of wiring plate 27, therefore can also prevent to be subjected to excessive stress by undersized first connector 8 and 9 welding portions that form between semiconductor chip 2a and 2b and Semiconductor substrate 3, this can improve the soldering reliability of welding portion.As a result, compare, can improve the welding reliability between semiconductor chip 2a and 2b, Semiconductor substrate 3 and the wiring plate 27 with first embodiment.
Other advantages of second embodiment are identical with first embodiment.
Will be with reference to Figure 11 and the 12 manufacture method examples of describing according to the semiconductor device 21 of second embodiment.
As shown in figure 11, what form at the core of wiring plate 27 is cavity 26, and the planar dimension in cavity 26 is a bit larger tham Semiconductor substrate 3, as the depression with bottom.This cavity 26 can be passed through machine tool, laser, etching or another kind of method and form.
After liquid state or paste resin material supplies are on the bottom in cavity 26 and sidewall surfaces, Semiconductor substrate 3 is placed in the cavity 26, as shown in figure 12, then resin material for example is heating and curing, so that Semiconductor substrate 3 is fixed to wiring plate 27.Perhaps, can after Semiconductor substrate 3 being placed in empty 26, provide resin material in the gap between Semiconductor substrate 3 and cavity 26, can be solidified then.
In this state, by first connector 8 and 9 semiconductor chip 2a and 2b are welded to chip connection pads 5 on the Semiconductor substrate 3, chip connection pads 5 position slightly has been formed with the surface of the wiring plate 27 of weld zone 6 thereon.With this welding simultaneously, the external connection pads on semiconductor chip 2a and the 2b 13 is welded to weld zone 6 on the wiring plate 27 by second connector 12.First and second connectors 8,9 and 12 are provided with enough height, allow the chip connection pads 5 on the Semiconductor substrate 3 high together, perhaps be positioned at the below slightly on the surface that forms the weld zone, that is, be arranged in cavity 26 with the surface of the wiring plate 27 that forms the weld zone.
If be buried in Semiconductor substrate 3 in the wiring plate 27 so in advance before the welding between semiconductor chip 2a and 2b and Semiconductor substrate 3 and be fixed to the upper, just can select semiconductor chip 2a and 2b one by one, to use existing erection unit, it is installed on the Semiconductor substrate 3 such as the vacuum suction instrument.
On the contrary,, then the assembly of gained is welded to wiring plate 27, so just has following problem if in advance semiconductor chip 2a and 2b are welded on the Semiconductor substrate 3.Particularly, during the assembly of gained is welded to wiring plate 27, when a plurality of semiconductor chip 2a of vacuum suction and 2b, may be because of from the gas leakage of the gap of chip chamber and cause attracting to lose efficacy.In addition, for the assembly that prevents to be attracted tilts with respect to the face of weld in the cavity 26, must make the thickness equilibrium of a plurality of semiconductor chip 2a and 2b.
On the other hand, if in advance Semiconductor substrate 3 is buried in the wiring plate 27 as mentioned above, just can use the vacuum suction instrument to select semiconductor chip 2a and 2b one by one and be installed on the Semiconductor substrate 3 in existing mode.
[the 3rd embodiment]
Figure 13 shows the semiconductor device 31 according to third embodiment of the invention.Give identical label with part identical among first and second embodiment, its detailed description will be omitted.
The wiring plate 37 that the semiconductor device 31 of present embodiment comprises Semiconductor substrate 3, be installed in a plurality of semiconductor chip 2a on the Semiconductor substrate 3 and 2b and be connected to semiconductor chip 2a and 2b.
Semiconductor substrate 3 has on its same surface and is used for chip that semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect 4 and be connected to a plurality of chip connection pads 5 of chip to chip interconnect 4.The first type surface of semiconductor chip 2a and 2b (form IC surface) is connected to chip connection pads 5 on the Semiconductor substrate 3 by first connector 8 and 9.So semiconductor chip 2a and 2b are electrically connected to each other to chip interconnect by the chip that is formed on the Semiconductor substrate 3.
A plurality of external connection pads 13 are formed at above the first type surface of semiconductor chip 2a and 2b on the zone outside the zone of Semiconductor substrate 3.A plurality of weld zones 6 are formed on the wiring plate 37.The spacing of the chip connection pads 5 on the gap ratio Semiconductor substrate 3 of external connection pads 13 and weld zone 6 ( first connector 8 and 9 spacing) is big.External connection pads 13 is connected to weld zone 6 by second connector 38, so semiconductor chip 2a and 2b are electrically connected to wiring plate 37.
Gap between gap between Semiconductor substrate 3 and semiconductor chip 2a and the 2b and semiconductor chip 2a and 2b and the wiring plate 37 is filled out resin material 36 end of with and is filled, and is protecting welding portion between semiconductor chip 2a and 2b and the Semiconductor substrate 3 and the welding portion between semiconductor chip 2a and 2b and the wiring plate 37.
In the present embodiment, Semiconductor substrate 3 is not placed in the wiring plate 37, has formed on the surface of weld zone 6 and be mounted on its of wiring plate 37.Therefore, different with first and second embodiment, needn't in wiring plate, form the cavity, this can correspondingly reduce technology cost and time.But, compare with first and second embodiment, there is shortcoming in the 3rd embodiment aspect the thickness of entire semiconductor device reducing, and Semiconductor substrate 3 lays respectively in wiring plate 7 and 27 in first and second embodiment.
In addition, the distance between the weld zone 6 on external connection pads on semiconductor chip 2a and the 2b 13 and the wiring plate 37 is big, and this requires to connect inevitably, and their second connector 38 is corresponding has a large scale.These second big connectors 38 force external connection pads 13 and weld zone 6 to have large scale and spacing.On the contrary, first and second embodiment allow second connector 12, external connection pads 13 and weld zone 6 to the three embodiment to have littler size and spacing, therefore can realize the facet size.
The semiconductor chip number that is installed on the Semiconductor substrate 3 is not limited to two, but can be three or more.Figure 14 shows an example, and wherein four semiconductor chip 70a are installed on the Semiconductor substrate 3 to 70d.In 70d, for instance, a semiconductor chip serves as memory element at a plurality of semiconductor chip 70a, and another semiconductor chip serves as logic element.As long as at least one semiconductor chip is connected to outside wiring plate in these a plurality of chips, these semiconductor chips 70a just can comprise the semiconductor chip 70b that is not directly connected to outside wiring plate to 70d.
Although used particular term to describe the preferred embodiments of the present invention, such description should be appreciated that under the situation of the spirit or scope that do not deviate from claim and can make a change and change only for purpose of explanation.
The present invention comprises the relevant theme of submitting in Japan Patent office with on March 16th, 2005 of Japanese patent application JP2005-075165, at this it is introduced in full to do reference.

Claims (6)

1. semiconductor device comprises:
A plurality of semiconductor chips;
Semiconductor substrate has on its same surface and is used for chip that described a plurality of semiconductor chips are electrically connected to each other to chip interconnect and be connected to a plurality of chip connection pads of described chip to chip interconnect; And
Wiring plate has a plurality of weld zones, and the spacing of described weld zone is greater than the spacing of described chip connection pads, wherein
The first type surface of each of described a plurality of semiconductor chips is connected to described chip connection pads by first connector, so that described a plurality of semiconductor chips are installed on the described Semiconductor substrate, and
On the described first type surface except that in the face of being formed with external connection pads the zone of described Semiconductor substrate and being connected to described weld zone on the described wiring plate by second connector.
2. according to the semiconductor device of claim 1, wherein
Described Semiconductor substrate is arranged in the cavity that is formed at described wiring plate.
3. according to the semiconductor device of claim 2, wherein
In described cavity, provide resin material in mode, and described Semiconductor substrate is welded to described wiring plate by described resin material around described Semiconductor substrate.
4. semiconductor device comprises:
A plurality of semiconductor chips; And
Semiconductor substrate has on its same surface and is used for chip that described a plurality of semiconductor chips are electrically connected to each other to chip interconnect and be connected to a plurality of chip connection pads of described chip to chip interconnect, wherein
The first type surface of each of described a plurality of semiconductor chips is connected to described chip by connector and connects brave dish, so that described a plurality of semiconductor chips are installed on the described Semiconductor substrate, and
Be formed with a plurality of external connection pads on the described first type surface except that facing the zone of described Semiconductor substrate, the spacing of described external connection pads is greater than the spacing of described chip connection pads.
5. method of making semiconductor device may further comprise the steps:
On the same surface of described Semiconductor substrate, form chip to chip interconnect and a plurality of chip connection pads that is connected to described chip to chip interconnect;
Form a plurality of external connection pads at a plurality of semiconductor chips in the face of the first type surface the zone of described Semiconductor substrate, the spacing of described external connection pads is greater than the spacing of described chip connection pads;
Form a plurality of weld zones on wiring plate, the spacing of described weld zone equals the spacing of described external connection pads;
Each described first type surface of described a plurality of semiconductor chips is connected to described chip connection pads by first connector, so that described a plurality of semiconductor chips are installed on the described Semiconductor substrate; And
Described external connection pads on the described semiconductor chip is connected to described weld zone on the described wiring plate by second connector.
6. according to the method for the manufacturing semiconductor device of claim 5, wherein
Before being installed in described semiconductor chip on the described Semiconductor substrate, be installed in described Semiconductor substrate on the described wiring plate or be placed in the described wiring plate, make described chip connection pads with its of described wiring plate on have a described weld zone a surperficial identical side be exposed.
CNB2006100592086A 2005-03-16 2006-03-15 Semiconductor device and method of manufacturing semiconductor device Expired - Fee Related CN100470793C (en)

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