CN100470782C - Chip encapsulation structure - Google Patents

Chip encapsulation structure Download PDF

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Publication number
CN100470782C
CN100470782C CNB2006100301150A CN200610030115A CN100470782C CN 100470782 C CN100470782 C CN 100470782C CN B2006100301150 A CNB2006100301150 A CN B2006100301150A CN 200610030115 A CN200610030115 A CN 200610030115A CN 100470782 C CN100470782 C CN 100470782C
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China
Prior art keywords
chip
contact
busbar
bonding wire
many interior
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CNB2006100301150A
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Chinese (zh)
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CN101127337A (en
Inventor
吴燕毅
李欣鸣
黄志龙
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Unimos Microelectronics(shanghai) Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Shanghai Ltd
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Priority to CNB2006100301150A priority Critical patent/CN100470782C/en
Publication of CN101127337A publication Critical patent/CN101127337A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The utility model discloses a chip packaging structure, which comprises a lead holder, at least a first weld wire, at least a second weld wire, a plurality of third weld wire and a packaging colloid; wherein, the lead holder comprises a chip base, a plurality of inner pins and at least a bus bar; the inner pins are arranged at the external periphery of the chip base, the bus bar is arranged between the chip base and the inner pins. Height difference is maintained between the bus bar and the inner pins; the bus bar is designed in a settlement manner. The chip is arranged on the chip base, and comprises at least a first contact and a second contact; the first weld wire is connected between the first contact and the bus bar; the second weld wire is connected between the bus bar and one of the inner pins; the third weld wire is connected between other inner pins and the second contact. The packaging colloid covers the chip base, the inner pins, the bus bar, the chip, the first weld wire, the second weld wire and the third weld wires.

Description

Chip-packaging structure
Technical field
The present invention is relevant for a kind of chip-packaging structure, and is particularly to a kind of chip-packaging structure with busbar.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cutting wafer steps such as (wafer sawing).Wafer has an active surface (activesurface), the surface with active member (active device) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active surface of wafer also disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (leadframe) or a base plate for packaging (packagesubstrate).The mode that chip can routing engages (wire bonding) or chip bonding (flip chip bonding) is connected on the carrier, make these weld pads (bonding pad) of chip can be electrically connected at the contact of carrier, to constitute a chip-packaging structure.
Look schematic diagram on Fig. 1 existing chip packaging body.Fig. 2 is the generalized section of Fig. 1 chip packing-body.Please jointly with reference to Fig. 1 and Fig. 2, for the convenience on illustrating, Fig. 1 and Fig. 2 are the schematic diagrames of perspective packing colloid 140, and only go out the profile of packing colloid 140 with dotted lines.Chip packing-body 100 comprises a lead frame 110, a chip 120, many first bonding wires (bonding wire) 130, many second bonding wires 132, many articles the 3rd bonding wires 134 and a packing colloid (encapsulant) 140.Lead frame 110 comprises a chip carrier (diepad) 112, many interior pins 114 and many busbars 116.Interior pin 114 is disposed at the periphery of chip carrier 112.Busbar 116 is between chip carrier 112 and interior pin 114, and busbar 116 and interior pin 114 coplines.
Chip 120 has an active surface 122 respect to one another and a back side 124.Chip 120 is disposed on the chip carrier 112, and the back side 124 is towards chip carrier 112.Chip 120 has a plurality of ground contacts 126 and a plurality of non-ground contacts 128, and wherein these non-ground contacts 128 comprise a plurality of power supply contacts and a plurality of signal contact.Ground contact 126 all is positioned on the active surface 122 with non-ground contact 128.
First bonding wire 130 is electrically connected at busbar 116 with ground contact 126.Second bonding wire 132 is electrically connected at the grounding pin in the pin 114 in these with busbar 116.134 of the 3rd bonding wires are electrically connected at pin in remaining 114 the second corresponding contact 128 respectively.Packing colloid 140 is coated on chip carrier 112, interior pin 114, busbar 116, chip 120, first bonding wire 130, second bonding wire 132 and the 3rd bonding wire 134 in it.
It should be noted that therefore the 3rd bonding wire 134 must be crossed over busbar 116 because the interior pin 114 of existing chip encapsulating structure 100 is coplanar with busbar 116.In other words, the height of the 3rd bonding wire 134 is higher, and therefore in the processing procedure of inserting packing colloid 140, packing colloid 140 causes the skew or the fracture of the 3rd bonding wire 134 easily.
Summary of the invention
Purpose of the present invention is providing a kind of chip-packaging structure exactly, to improve reliability.
Another object of the present invention is exactly in that a kind of chip-packaging structure is provided, with reduced volume.
The present invention proposes a kind of chip-packaging structure, and it comprises a lead frame, a chip, at least one first bonding wire, at least one second bonding wire, many articles the 3rd bonding wires and a packing colloid.Lead frame comprises a chip carrier, many interior pins and at least one busbar.Interior pin configuration is in the periphery of chip carrier.Busbar and is kept one first difference in height between busbar and the interior pin between chip carrier and interior pin, and busbar is put (down-set) design for heavy.Chip has an active surface respect to one another and a back side.Chip configuration is on chip carrier, and the back side is towards chip carrier.Chip has at least one first contact and a plurality of second contact, and first contact and second contact are positioned on the active surface.First bonding wire is connected between first contact and the busbar.Second bonding wire connects busbar and interior pin between one of them.These the 3rd bonding wires connect respectively between other the interior pins and second contact.Packing colloid is coated on chip carrier, interior pin, busbar, chip, first bonding wire, second bonding wire and the 3rd bonding wire in it.
In one embodiment of this invention, keep one second difference in height between interior pin and the chip carrier, and chip carrier is the heavy meter that installs.
In one embodiment of this invention, first contact comprises power supply contact, ground contact or signal contact.
The present invention more proposes a kind of chip-packaging structure, and it comprises a chip, a lead frame, at least one first bonding wire, at least one second bonding wire, many articles the 3rd bonding wires and a packing colloid.Chip has an active surface and at least one first contact and a plurality of second contact that are disposed at active surface.Chip is bonded to the lead frame below.Lead frame comprises many interior pins and at least one busbar.One end of interior pin is positioned on the active surface, and is positioned at the periphery of first contact and second contact.Busbar and is positioned at the top of active surface between interior pin and first contact and second contact.Keep a difference in height between busbar and the interior pin, and busbar is lifting (up-set) design.First bonding wire is connected between first contact and the busbar.Second bonding wire is connected in busbar and interior pin between one of them.The 3rd bonding wire is connected between other the interior pins and second contact.Packing colloid is coated on interior pin, busbar, chip, first bonding wire, second bonding wire and the 3rd bonding wire in it.
In one embodiment of this invention, first contact comprises power supply contact, ground contact or signal contact.
Owing to have a difference in height between the present invention's busbar and the interior pin, so the present invention can dwindle the volume of lead frame, so chip packing-body proposed by the invention has the advantage of miniaturization.
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Look schematic diagram on Fig. 1 existing chip packaging body.
Fig. 2 is the generalized section of Fig. 1 chip packing-body.
Fig. 3 is the schematic side view of the chip packing-body of one embodiment of the invention.
Fig. 4 be Fig. 3 chip packing-body on look schematic diagram.
Fig. 5 is the schematic side view of the chip packing-body of another embodiment of the present invention.
Fig. 6 be Fig. 5 chip packing-body on look schematic diagram.
Embodiment
Fig. 3 is the schematic side view of the chip packing-body of one embodiment of the invention.Fig. 4 be Fig. 3 chip packing-body on look schematic diagram.For the convenience on illustrating, Fig. 3 and Fig. 4 are the schematic diagrames of perspective packing colloid 240, and only go out the profile of packing colloid 240 with dotted lines.Chip-packaging structure 200 comprises a lead frame 210, a chip 220, at least one first bonding wire 230, at least one second bonding wire 232, many articles the 3rd bonding wires 234 and a packing colloid 240.
Lead frame 210 comprises a chip carrier 212, many interior pins 214 and a busbar 216.Interior pin 214 is disposed at the periphery of chip carrier 212, and wherein pin 214 comprises the pin 214a and a plurality of second interior pin 214b at least one first in these.Busbar 216 is between chip carrier 212 and interior pin 214, and busbar 216 is to keep one first height difference H 1 between heavy mode that installs and the interior pin 214.
Chip 220 has an active surface 222 respect to one another and a back side 224.Chip 220 is disposed on the chip carrier 212, and the back side 224 is towards chip carrier 212.Chip 220 has at least one first contact 226 and a plurality of second contacts 228, and wherein first contact 226 and second contact 228 all are positioned on the active surface 222.
First bonding wire 230 is connected between first contact 226 and the busbar 216.Second bonding wire 232 is connected between the busbar 216 and the first interior pin 214a.Thus, first contact 226 just can electrically connect via pin in first bonding wire 230, busbar 216 and second bonding wire 232 and first 214.234 of the 3rd bonding wires are to be connected between the second interior pin 214b and these second contacts 228.
Packing colloid 240 is coated on chip carrier 212, interior pin 214, busbar 216, chip 220, first bonding wire 230, second bonding wire 232 and the 3rd bonding wire 234 in it.More preferably, present embodiment can also make and keep one second height difference H 2 between chip carrier 212 and the interior pin 214 via the heavy mode that installs meter, to improve reliability.
Based on above-mentioned structure, present embodiment can be a transit point with busbar 216 just, and a plurality of first contacts 226 with same potential are electrically connected on its corresponding first interior pin 214a.For example, when these first contacts 226 are ground contact, and when these when pin 214a is grounding pin in first, present embodiment just can be electrically connected at these first contacts 226 (ground contact) on these first interior pin 214a (grounding pin) via first bonding wire 230, busbar 216 and second bonding wire 232.It should be noted that, because the current potential of the various piece of busbar 216 is all identical, therefore present embodiment can be adjusted the position that first bonding wire 230, second bonding wire 232 engage with busbar 216, so that present embodiment can be finished electric connection between first contact 226 and the first interior pin 214a with the wire length (i.e. the length of first bonding wire 230 and second bonding wire 232) of lacking.
Certainly first contact 226 also can be power supply contact or signal contact in other embodiments of the invention.What deserves to be mentioned is when first contact 226 is signal contact, to have only single first contact 226 to be electrically connected on the busbar 216 via first bonding wire 230.
In addition, the lead frame 210 of present embodiment can also be complied with the needs in the design and has a plurality of busbars 216 except can having single busbar 216.For example, present embodiment can also be formed at another busbar 216 opposite side of chip carrier 212 except a busbar 216 being formed at the side of chip carrier 212.
When lead frame 210 has a plurality of busbar 216, outside these of present embodiment first contact 226 can also be made up of a plurality of ground contacts, a plurality of power supply contact or a plurality of signal contact, can also be both combinations arbitrarily in above-mentioned three kinds of contacts, or even above-mentioned three kinds of contacts combine.Be noted that when a plurality of first contacts 226 were connected to same busbar 216, the current potential of a time point in office of these first contacts 226 must be identical.
Fig. 5 is the schematic side view of the chip packing-body of another embodiment of the present invention.Fig. 6 be Fig. 5 chip packing-body on look schematic diagram.For the convenience on illustrating, Fig. 5 and Fig. 6 are the schematic diagrames of perspective packing colloid 360, and only go out the profile of packing colloid 360 with dotted lines.Please jointly with reference to Fig. 5 and Fig. 6, chip-packaging structure 300 comprises a chip 310, a lead frame 320, at least one first bonding wire 330, at least one second bonding wire 340, many articles the 3rd bonding wires 350 and a packing colloid 360.
Chip 310 has an active surface 312.Chip 310 also has at least one first contact 314 and a plurality of second contacts 316, and wherein first contact 314 and second contact 316 are to be disposed on the active surface 312.Chip 310 is bonded to the below of lead frame 320.Lead frame 320 comprises many interior pins 322, a busbar 324.End of pin 322 is positioned on the active surface 312 in these, and is positioned at the periphery of first contact 314 and second contact 316, and wherein pin 322 comprises the pin 322a and a plurality of second interior pin 322b in a plurality of first in these.
Busbar 324 and is positioned at the top of active surface 212 in these between pin 322 and first contact 314, second contact 316, and wherein busbar 324 is the modes via lifting (up-set) design, come and interior pin 322 between keep a height difference H 3.
First bonding wire 330 is connected between first contact 314 and the busbar 324.Second bonding wire 340 is connected between the busbar 324 and the first interior pin 322a.The 3rd bonding wire 350 is connected between the second interior pin 222b and second contact 216.Packing colloid 360 is coated on interior pin 322, busbar 324, chip 310, first bonding wire 330, second bonding wire 340 and the 3rd bonding wire 350 in it.
Based on above-mentioned structure, present embodiment can be a transit point with busbar 324 just, and a plurality of first contacts 314 with same potential are electrically connected on its corresponding first interior pin 322a.For example, when these first contacts 314 are ground contact, and when these when pin 322a is grounding pin in first, present embodiment just can be electrically connected at these first contacts 314 (ground contact) on these first interior pin 322a (grounding pin) via first bonding wire 330, busbar 324 and second bonding wire 340.It should be noted that, because the current potential of the various piece of busbar 324 is all identical, therefore present embodiment can be adjusted the position that first bonding wire 330, second bonding wire 340 engage with busbar 324, so that present embodiment can be finished electric connection between first contact 314 and the first interior pin 322a with the wire length (i.e. the length of first bonding wire 330 and second bonding wire 340) of lacking.
Certainly first contact 314 also can be power supply contact or signal contact in other embodiments of the invention.What deserves to be mentioned is when first contact 314 is signal contact, to have only single first contact 314 to be electrically connected on the busbar 324 via first bonding wire 330.
In addition, the lead frame 320 of present embodiment can also be complied with the needs in the design and has a plurality of busbars 324 except can having single busbar 324.For example, present embodiment can also be formed at another busbar 324 opposite side of first contact 314 except a busbar 324 being formed at the side of first contact 314.
When lead frame 320 has a plurality of busbar 324, outside these of present embodiment first contact 314 can also be made up of a plurality of ground contacts, a plurality of power supply contact or a plurality of signal contact, can also be both combinations arbitrarily in above-mentioned three kinds of contacts, or even above-mentioned three kinds of contacts combine.Be noted that when a plurality of first contacts 314 were connected to same busbar 324, the current potential of these first contacts 314 must be identical.
Compared to existing technologies, owing to have difference in height between busbar of the present invention and the interior pin, so the present invention can dwindle the line length of the shared space of lead frame, shortening first bonding wire and second bonding wire.Therefore chip packing-body proposed by the invention has the advantage of miniaturization.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims (5)

1. chip-packaging structure comprises:
One lead frame comprises:
One chip carrier;
Many interior pins are disposed at the periphery of this chip carrier;
At least one busbar between this chip carrier and these many interior pins, and is kept one first difference in height between this busbar and these many interior pins, and this busbar is the heavy meter that installs;
One chip, have an active surface respect to one another and a back side, this chip configuration is on this chip carrier, and this back side is towards this chip carrier, this chip has at least one first contact and a plurality of second contact, and this first contact is positioned on this active surface with these a plurality of second contacts;
At least one first bonding wire is connected between this first contact and this busbar;
At least one second bonding wire connects this busbar and these many interior pins between one of them;
Many articles the 3rd bonding wires connect respectively between other this many interior pins and this a plurality of second contacts; And
One packing colloid coats this chip carrier, these many interior pins, this busbar, this chip, this first bonding wire, this second bonding wire and this a plurality of the 3rd bonding wires.
2. chip-packaging structure as claimed in claim 1 is characterized in that, keeps one second difference in height between these many interior pins and this chip carrier, and this chip carrier is the heavy meter that installs.
3. chip-packaging structure as claimed in claim 1 is characterized in that, this first contact comprises power supply contact, ground contact or signal contact.
4. chip-packaging structure comprises:
One chip has an active surface and at least one first contact and a plurality of second contact that are disposed at this active surface;
One lead frame, this chip are bonded to this lead frame below, and this lead frame comprises:
Many interior pins, an end of these many interior pins is positioned on this active surface, and is positioned at the periphery of this first contact and these a plurality of second contacts;
At least one busbar between these many interior pins and this first contact and this a plurality of second contacts, and is positioned at the top of this active surface, wherein keep a difference in height between this busbar and these many interior pins, and this busbar designs for lifting;
At least one first bonding wire is connected between this first contact and this busbar;
At least one second bonding wire is connected in this busbar and these many interior pins between one of them;
Many articles the 3rd bonding wires are connected between other this many interior pins and this a plurality of second contacts; And
One packing colloid coats these many interior pins, this busbar, this chip, this first bonding wire, this second bonding wire and this a plurality of the 3rd bonding wires.
5. chip-packaging structure as claimed in claim 4 is characterized in that, this first contact comprises power supply contact, ground contact or signal contact.
CNB2006100301150A 2006-08-16 2006-08-16 Chip encapsulation structure Active CN100470782C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006100301150A CN100470782C (en) 2006-08-16 2006-08-16 Chip encapsulation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006100301150A CN100470782C (en) 2006-08-16 2006-08-16 Chip encapsulation structure

Publications (2)

Publication Number Publication Date
CN101127337A CN101127337A (en) 2008-02-20
CN100470782C true CN100470782C (en) 2009-03-18

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