CN100468749C - Bigrid layout structure for thin film transistor - Google Patents
Bigrid layout structure for thin film transistor Download PDFInfo
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- CN100468749C CN100468749C CNB2007100065487A CN200710006548A CN100468749C CN 100468749 C CN100468749 C CN 100468749C CN B2007100065487 A CNB2007100065487 A CN B2007100065487A CN 200710006548 A CN200710006548 A CN 200710006548A CN 100468749 C CN100468749 C CN 100468749C
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- raceway groove
- conductive impurity
- polysilicon layer
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Abstract
The invention relates to one pixel multi-grating film transistor tube to suppress current leakage, which comprises one snake shape or L shape multi-silicon layer composed of one n+ mixture source electrode, one first n- light mixture area, one first grating groove, one second mixture area, one second grating groove, one third n- light mixture, one n+ weight leakage area; the source electrode is connected to one materials line through oen contact window with length direction along materials line to deposit one grating oxidation electrode.
Description
The present invention is on April 9th, 2003 for the applying date, and application number is 03109443.0, and denomination of invention is divided an application for the patent application of " Bigrid layout structure of thin-film transistor ".
Technical field
The present invention relates to a kind of LCD Technology, particularly a kind of double grid type thin-film transistor structure of low temperature polycrystalline silicon LCD.
Background technology
LCD (LCD) is a kind of display of plane, has the low power consumption characteristic, compare with cathode ray tube (GRT) with window dimension, though with regard to take up room or quality with regard to, LCD gains all great advantage.The good gesture thereafter of also therefore numerous manufacturers and add in succession and produce ranks.This also impels its price more popular.Therefore its product is also by undersized consumption electronic products such as palmtop computer, computerized dictionary, wrist-watch, mobile phone, PDA(Personal Digital Assistant), upper floor and more to larger-size notebook computer, communication terminal machine, display panel, individual's desktop computer, TV etc.Active-matrix type Thin Film Transistor-LCD (TFT-LCD) particularly, its angle of visibility, contrast expression, reaction time are the outstanding persons of all LCD display, future a slice is good.
With regard to TFT-LCD, nowadays many for a long time have a selection in addition with the main material of traditional amorphous silicon as the TFT of TFT-LCD in addition, promptly uses polysilicon replacement amorphous silicon and might become main flow.This mainly is conceived to no matter be the mobility (mobility) in electronics or hole, and polysilicon all provides better mobility than amorphous silicon.In addition, to also have an advantage be that the drive circuit (comprising nmos pass transistor or PMOS transistor CMOS CMOS even) that forms the LCD panel can carry out simultaneously with the manufacturing of pixel panel to multi-crystal TFT-LCD.Because above-mentioned factor, polysilicon type TFT-LCD can provide the switching rate better than amorphous silicon type TFT-LCD, and is more attractive.
Certainly polysilicon type TFT-LCD is not immaculate yet, for example carries out switch when switching to closed condition as TFT, often still has very big drain leakage.For overcoming this shortcoming, people such as Inoue propose a kind of thin-film transistor structure that is called bigrid (dual gate) can be in order to suppress leakage current.Please refer to United States Patent (USP) the 5693959th, another kind of method please refer to No. the 5th, 940,151, its United States Patent (USP) that obtains for overcoming the problem of leakage current by people such as Ha with the technology of lightly doped drain (LDD).
The present invention will be absorbed in the thin-film transistor structure of bigrid (dual gate).Please be simultaneously with reference to the vertical view of Figure 1A and the cross sectional representation of cutting corresponding to a-a ' among Figure 1A.Number in the figure 909 is polysilicon layers, in order to the middle light doping section 909d of source electrode heavily doped region 909a, source electrode light doping section 909b, the first raceway groove 909c, bigrid, the second raceway groove 909e, drain electrode light doping section 909f, the drain electrode heavily doped region 900g that constitutes thin-film transistor (TFT).903 of labels are scan lines, comprise two grids on the first raceway groove 909c, the second raceway groove 909e.Label 904 is holding wires, is generally the aluminum metal lead, connects drain electrode heavily doped region 909g by drain electrode contact 910 (also being aluminum materials).912 of labels are the drain metal leads, and (through hole) 913 is connected with transparent conductive electrode 914 by perforation.Also be connected with drain electrode heavily doped region 909g simultaneously by drain electrode contact 911.
Be in direction in the above-mentioned double-grid structure with two grid parallel arrangement along scan line, and unfortunately be usually in the design that comprises colored filter, the pixel of Red, with at present layout also is side by side and along scan-line direction, such result will cause the resolution of picture to be restricted.Because with the total length of light doping section 909d three in the middle of two raceway groove 909c, 909e and the bigrid and, be subjected to the restriction of the little shadow board of TFT LCD up till now, its length summation will limit the resolution of whole image.
Though along scan-line direction bunching of picture element is arranged and influences the problem of resolution, along the direction of data line, because of the three primary colors pixel side by side direction and have more tolerance space not in this direction.Therefore the present invention will propose another thinking pattern, and the position of two raceway grooves is adjusted, and part is adjusted to by the data line direction along the burden on the scan line share, and solve a difficult problem on the above-mentioned conventional process.
Summary of the invention
Technical problem to be solved by this invention provides a kind of Bigrid layout structure of thin-film transistor of low temperature polycrystalline silicon LCD, in order to suppress leakage current, simultaneously, two grids that also can improve traditional double gate type thin film transistor structure are listed in the impairment that scan-line direction improves for resolution.
The Bigrid layout structure of thin-film transistor provided by the present invention is realized by following technical scheme.
A kind of pixel multi-grid electrode film transistor of LCD is characterized in that comprising:
One conductive impurity heavy-doped source polar region, one first conductive impurity doped region, a first grid raceway groove, one second conductive impurity doped region, a second grid raceway groove, one the 3rd conductive impurity doped region, and a conductive impurity heavily doped drain region be arranged in regular turn in the polysilicon layer, this conductive impurity heavy-doped source polar region is connected in a data line by the one source pole contact hole, this polysilicon layer is formed on the substrate and is one L shaped, and the length direction of this first grid raceway groove and this second grid raceway groove at least one be along the data line direction;
One grid oxic horizon covers above-mentioned polysilicon layer; And
One multiple-grid grid is formed on this grid oxic horizon, and at least with this polysilicon layer intersection in this first grid raceway groove and this second grid raceway groove top;
Wherein, this second conductive impurity doped region also comprises a conductive impurity heavily doped region in wherein, to reduce the resistance between this first grid raceway groove and this second grid raceway groove.
Except that above-mentioned essential features, in specific implementation process, also can replenish following technology contents:
Wherein this multiple-grid grid comprises one scan line and an I shape grid extension vertical with this scan line, and respectively with perpendicular section of this L shaped polysilicon layer with the crosspiece intersection in this first grid raceway groove and this second grid raceway groove top, the crosspiece end of this L shaped polysilicon layer is this conductive impurity heavy-doped source polar region, and perpendicular section end is this conductive impurity heavily doped drain region.
In this second conductive impurity light doping section between above-mentioned first grid raceway groove and above-mentioned second grid raceway groove, comprise a conductive impurity heavily doped region in wherein, to reduce the resistance between this two grid groove.The present invention discloses a kind of pixel multi-grid electrode film transistor layout structure in order to the LCD that suppresses leakage current, comprises five embodiment in the present invention altogether.
At least include the gate metal layer that a polysilicon layer and that is snakelike (or being called stairstepping) comprises an one scan line and an I shape extension among first embodiment, this snakelike polysilicon layer and this scan line and this I shape extension respectively have a plotted point; In addition, the adjoiner of grid groove is the n-light doping section, and more comprises a n+ heavily doped region to reduce the resistance between two grid grooves between two grid grooves.In addition, the both ends of I conformal polysilicon layer then are respectively n+ heavy-doped source polar region and n+ heavily doped drain region.N+ heavy-doped source polar region wherein is connected in a data line by the one source pole contact hole.The n+ heavily doped drain region then is connected to storage capacitors by the drain electrode contact hole and another interlayer raceway groove connects the transparency electrode pole plate.
In a second embodiment, polysilicon layer is L-shaped, and gate metal layer comprises an one scan line and a L shaped extension, this L shaped polysilicon layer and this scan line and this L shaped extension respectively have a plotted point with as grid groove, in addition, the adjoiner of grid groove is the n-light doping section, and the both ends of L shaped polysilicon layer then are respectively n+ heavy-doped source polar region and n+ heavily doped drain region.
In the 3rd embodiment, polysilicon layer is L-shaped, and gate metal layer comprises an one scan line and an I shape extension, this L shaped polysilicon layer and this scan line and this I shape extension respectively have a plotted point with as grid groove, in addition, the adjoiner of grid groove is the n-light doping section, and more comprises a n+ heavily doped region to reduce the resistance between two grid grooves between two grid grooves.In addition, the both ends of L shaped polysilicon layer then are respectively n+ heavy-doped source polar region and n+ heavily doped drain region.
In the 4th embodiment, similar in appearance to second embodiment, polysilicon layer is L-shaped, and gate metal layer comprises an one scan line and a L shaped extension, and this L shaped polysilicon layer and this scan line and this L shaped extension respectively have a plotted point with as grid groove.In addition, the adjoiner of grid groove is the n-light doping section, and the both ends of L shaped polysilicon layer then are respectively n+ heavy-doped source polar region and n+ heavily doped drain region.Perpendicular section of but above-mentioned polysilicon layer is approached data line.
In the 5th embodiment, polysilicon layer is L-shaped, and gate metal layer comprises an one scan line and a L shaped extension, the crosspiece of this L shaped polysilicon layer and the L shaped extension of the gate metal layer that comprises an one scan line and a L shaped extension and perpendicular section respectively have a plotted point with as grid groove, in addition, the adjoiner of grid groove is the n-light doping section, and more comprises a n+ heavily doped region to reduce the resistance between two grid grooves between two grid grooves.In addition, the both ends of L shaped polysilicon layer then are respectively n+ heavy-doped source polar region and n+ heavily doped drain region.
The invention has the advantages that:
Because two grid grooves in the bigrid have at least one to be along the data line direction, therefore make transistor layout structure of the present invention can hold more pixels, and can improve resolution along scan-line direction.
Preferred embodiment of the present invention will be aided with description of drawings and do more detailed elaboration in following comment.
Description of drawings
Figure 1A shows the schematic top plan view of traditional double grid thin-film transistor.
Figure 1B shows along the cross sectional representation of the a-a ' line of Figure 1A.
Fig. 2 A shows the transistorized schematic top plan view of double-gate film of the present invention.
Fig. 2 B shows along the cross sectional representation of the b-b ' line of Fig. 2 A.
Fig. 3 shows the schematic top plan view of double-gate film transistor second embodiment of the present invention.
Fig. 4 shows the schematic top plan view of double-gate film transistor the 3rd embodiment of the present invention.
Fig. 5 shows the schematic top plan view of double-gate film transistor the 4th embodiment of the present invention.
Fig. 6 shows the schematic top plan view of double-gate film transistor the 5th embodiment of the present invention.
Embodiment
Because it is following no matter be that the tendency of LCD or LCD TV is except large scaleization, be exactly improving its resolution with further raising picture quality.And the leakage current of the shortcoming of low temperature polycrystalline silicon LCD maximum when being OFF, though and Bigrid layout structure at present can reduce leakage current, but because of two grids are to be listed in along scan-line direction, therefore impairment is arranged to improving resolution.Layout structure provided by the present invention can solve the above problems.Relevant conductive-type impurity in the narration of following execution mode, all be to be example for convenience of description with n type conductive-type impurity, but in order to limit claim of the present invention, any correlation technique person of being familiar with does not know that all n type conductive-type impurity can also be replaced with p type conductive-type impurity comprehensively.Layout of the present invention has a plurality of different embodiment, and division is as follows:
The first embodiment of the present invention please refer to the layout vertical view of a pixel of Fig. 2 A and corresponding cross sectional representation Fig. 2 B thereof.Snakelike (or be called stairstepping, shown in Fig. 2 A) polysilicon section 100 comprises that 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I are formed on the glass substrate.Snakelike polysilicon section 100 has two confluces with scanning metal wire 120 and I shape grid extension 121, and these two confluces constitute the first raceway groove 100C respectively, reach the second raceway groove 100G.Certainly, before forming scan line metal wire 120 and I shape grid 121, can form a grid oxic horizon on substrate comprehensively.The adjacent dual-side of the first raceway groove 100C is that n-meets doped region 100B, 100D.The adjacent dual-side of the same second raceway groove 100G also is n-light doping section 100F, 100H.For reducing the resistance between two grid groove 100C and the 100G, can comprise a n+ heavily doped region 100E usually.Polysilicon section 100A is the source area of a n+ heavy doping type conductive impurities in addition, and with the data line 130 of metal material, for example the aluminum metal line connects by contact hole 132.And polysilicon section 100I is a heavily doped drain region, connects storage capacitors (not shown) and is connected with plain conductor 150 on being formed at first metal intermetallic dielectric layer 180 by contact hole 133.Be connected with transparent conductive electrode 160 on second metal intermetallic dielectric layer 190 by another contact hole 162 again.
Please note polysilicon section 100D, 100E, the 100F of Fig. 2 A, can also not need as illustrated three districts that make at right angles, for example can be the figure arcuation or be two raceway groove 100C and be connected two raceway grooves with the beeline straight line of 100G line.Near if contraction in length to 1 μ m (containing) is following, can be as long as a n-light doping section.
The second embodiment of the present invention please refer to the layout vertical view of the pixel of Fig. 3.L shaped polysilicon section 200 comprises that 200A, 200B, 200C, 200D, 200E, 200F, 200G are formed on the glass substrate.L shaped polysilicon section 200 has two confluces with scan line metal wire 220 and L shaped grid extension 221, and these two confluces constitute the first raceway groove 200C respectively, reach the second raceway groove 200E.Certainly, before forming scan line metal wire 220 and L shaped grid 221, can form a grid oxic horizon 240 on substrate comprehensively.Just like last embodiment, the adjacent dual-side of the first raceway groove 200C, the second raceway groove 200E is n- light doping section 200B, 200D and 200D and 200F.Polysilicon section 200A is the source area of a n+ heavy doping type conductive impurities in addition, is connected with the data line 230 of metal material by contact hole 232.And polysilicon section 200G is a heavily doped drain region, and it is connected described just like first embodiment with plain conductor that is connected storage capacitors (not shown) (not shown) and transparent conductive electrode 260 respectively by two contact holes.
Please note if the two raceway groove 20OG of Fig. 3 are little with the distance of 200E, as long as a n-light doping section 200D, but also can comprise a n+ reclosing and mix and distinguish 200D, in wherein for reducing resistance.
The third embodiment of the present invention please refer to the layout vertical view of the pixel of Fig. 4.L shaped polysilicon section 300 comprises that 300A, 300B, 300C, 300D, 300E, 300F, 300G, 300H, 300I are formed on the glass substrate.L shaped polysilicon section 300 has two confluces with scan line metal wire 320 and I shape grid extension 321, and these two confluces constitute the first raceway groove 300C respectively, reach the second raceway groove 300G.The adjacent dual-side of the first raceway groove 300C, the second raceway groove 300G is n- light doping section 300B, 300D and 300F and 300H, and is n+ heavily doped region 300E between n- light doping section 300D and 300F, can be in order to reduce the resistance between two grid groove 300C and the 300G.Polysilicon section 300A is the source area of a n+ heavy doping type conductive impurities in addition, is connected with the data line 330 of metal material by contact hole 332.And polysilicon section 300I is a heavily doped drain region, and it is connected described just like first embodiment with plain conductor that is connected storage capacitors (not shown) (not shown) and transparent conductive electrode 360 respectively by two contact holes.
The fourth embodiment of the present invention please refer to the layout vertical view of the pixel of Fig. 5.L shaped polysilicon section 400 comprises that 400A, 400B, 400C, 400D, 400E, 400F, 400G are formed on the glass substrate.L shaped polysilicon section 400 has two confluces with scan line metal wire 420 and L shaped mirror image grid 421, and these two confluces constitute the first raceway groove 400C respectively, reach the second raceway groove 400E.The 4th preferred embodiment and second embodiment compare, basically one be L shaped mirror image grid 421, be L shaped grid 221 all the other are all identical, so repeat no more.Similarly, please note if the distance of the two raceway groove 400C of Fig. 5 and 400E is little, as long as a n-light doping section 400D.But also can comprise the assorted district of n+ reclosing 400D ' in wherein for reducing resistance.
The fifth embodiment of the present invention please refer to the layout vertical view of the pixel of Fig. 6.L shaped polysilicon section 500 comprises that 500A, 500B, 500C, 500D, 500E, 500F, 500G, 500H, 500I are formed on the glass substrate.L shaped grid extension 521 in the gate metal layer of L shaped polysilicon section 500 and scan line metal wire 520 and L shaped grid extension 521 has two confluces, and these two confluces constitute the first raceway groove 500C respectively, reach the second raceway groove 500G.The adjacent dual-side of the first raceway groove 500C, the second raceway groove 500G is n- light doping section 500B, 500D and 500F and 500H, and the 500E between n- light doping section 500D and 500F is the n+ heavily doped region.Polysilicon section 500A is a n+ heavy doping type source area in addition, is connected with the data line 530 of metal material by contact hole 532.And polysilicon section 500I is a heavily doped drain region, and it is connected described just like first embodiment with plain conductor that is connected storage capacitors (not shown) (not shown) and transparent conductive electrode 360 respectively by two contact holes.
The present invention with preferred embodiment explanation as above and is familiar with this field skill person, in not breaking away from spiritual scope of the present invention, retouch when doing a little change, its scope of patent protection more ought on the claim scope and etc. same domain decide.
Claims (2)
1, a kind of pixel multi-grid electrode film transistor of LCD is characterized in that, described thin-film transistor comprises:
One conductive impurity heavy-doped source polar region, one first conductive impurity doped region, a first grid raceway groove, one second conductive impurity doped region, a second grid raceway groove, one the 3rd conductive impurity doped region, and a conductive impurity heavily doped drain region be arranged in regular turn in the polysilicon layer, this conductive impurity heavy-doped source polar region is connected in a data line by the one source pole contact hole, this polysilicon layer is formed on the substrate and is one L shaped, and the length direction of this first grid raceway groove and this second grid raceway groove at least one be along the data line direction;
One grid oxic horizon covers above-mentioned polysilicon layer; And
One multiple-grid grid is formed on this grid oxic horizon, and at least with this polysilicon layer intersection in this first grid raceway groove and this second grid raceway groove top;
Wherein, this second conductive impurity doped region also comprises a conductive impurity heavily doped region in wherein, to reduce the resistance between this first grid raceway groove and this second grid raceway groove.
2, the pixel multi-grid electrode film transistor of LCD according to claim 1, wherein this multiple-grid grid comprises one scan line and an I shape grid extension vertical with this scan line, and respectively with perpendicular section of this L shaped polysilicon layer with the crosspiece intersection in this first grid raceway groove and this second grid raceway groove top, the crosspiece end of this L shaped polysilicon layer is this conductive impurity heavy-doped source polar region, and perpendicular section end is this conductive impurity heavily doped drain region.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031094430A CN1328796C (en) | 2003-04-09 | 2003-04-09 | Double-grid arrangement structure of film transistor |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031094430A Division CN1328796C (en) | 2003-04-09 | 2003-04-09 | Double-grid arrangement structure of film transistor |
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| Publication Number | Publication Date |
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| CN101013706A CN101013706A (en) | 2007-08-08 |
| CN100468749C true CN100468749C (en) | 2009-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031094430A Expired - Lifetime CN1328796C (en) | 2003-04-09 | 2003-04-09 | Double-grid arrangement structure of film transistor |
| CNB2007100065487A Expired - Lifetime CN100468749C (en) | 2003-04-09 | 2003-04-09 | Bigrid layout structure for thin film transistor |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031094430A Expired - Lifetime CN1328796C (en) | 2003-04-09 | 2003-04-09 | Double-grid arrangement structure of film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100624314B1 (en) | 2005-06-22 | 2006-09-19 | 삼성에스디아이 주식회사 | Light emission display device and thin film transistor |
| TWI328879B (en) | 2006-11-30 | 2010-08-11 | Au Optronics Corp | Pixel structure and fabricating method thereof, diaplay panel and electro-optical apparatus |
| CN102709240B (en) * | 2012-05-04 | 2014-11-26 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN104122721B (en) * | 2013-06-28 | 2017-02-08 | 深超光电（深圳）有限公司 | Pixel structure |
| CN103915509B (en) * | 2014-03-25 | 2017-07-18 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT), array base palte and display device |
| CN103984174B (en) * | 2014-05-26 | 2017-01-18 | 南京中电熊猫液晶显示科技有限公司 | Pixel structure and manufacturing method and repair method thereof |
| CN105572992A (en) * | 2015-12-31 | 2016-05-11 | 深超光电（深圳）有限公司 | Pixel structure, array substrate and manufacturing method for pixel structure |
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| JP3253808B2 (en) * | 1994-07-07 | 2002-02-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
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2003
- 2003-04-09 CN CNB031094430A patent/CN1328796C/en not_active Expired - Lifetime
- 2003-04-09 CN CNB2007100065487A patent/CN100468749C/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
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| US5818070A 1998.10.06 |
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| Publication number | Publication date |
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| CN1328796C (en) | 2007-07-25 |
| CN1536681A (en) | 2004-10-13 |
| CN101013706A (en) | 2007-08-08 |
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