CN100461397C - 具有引线接合焊盘的半导体器件及其方法 - Google Patents

具有引线接合焊盘的半导体器件及其方法 Download PDF

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Publication number
CN100461397C
CN100461397C CNB038045214A CN03804521A CN100461397C CN 100461397 C CN100461397 C CN 100461397C CN B038045214 A CNB038045214 A CN B038045214A CN 03804521 A CN03804521 A CN 03804521A CN 100461397 C CN100461397 C CN 100461397C
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bond pad
aluminum lead
electric conductor
lead bond
passivation layer
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CN1639865A (zh
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苏珊·H·多尼
詹姆斯·W·米勒
乔弗里·B·哈尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

一种集成电路(50)具有引线接合焊盘(53)。引线接合焊盘(53)在集成电路(50)的有源电路(26)和/或电互连层(24)上方的钝化层(18)上形成。引线接合焊盘(53)连接于多个最末的金属层部分(51，52)。所述多个最末的金属层部分(51，52)在互连层(24)的最末互连层上形成。在一个实施例中，接合焊盘(53)由铝制成，最末金属层焊盘由铜制成。引线接合焊盘(53)允许在接合焊盘(53)正下方的最末金属层(21)中排布导体，因此使半导体芯片的表面积减小。

Description

具有引线接合焊盘的半导体器件及其方法
技术领域
本发明涉及半导体器件，尤其涉及一种具有引线接合焊盘的半导体器件及其方法。
背景技术
在集成电路(IC)的制造过程中，重要的是集成电路芯片应尽可能小，以便降低成本。引线接合(wire bonding)是一种广泛使用的方法，用于将具有电路的半导体芯片连接于元件封装上的管脚。接合焊盘是IC表面上的导电金属区。尽管改进的技术已经可以减小集成电路的尺寸，但引线接合焊盘的尺寸没有尽快地递减。所以，接合焊盘占用了整个电路面积的很大百分比。这也减小了IC上用于在形成接合焊盘的金属层上排布电力总线的可用面积。
发明内容
根据本发明，提供一种集成电路，包含：具有有源电路的衬底；在所述衬底上形成的多个铜互连层；在所述多个互连层上形成的钝化层；以及铝引线接合焊盘，该铝引线接合焊盘形成在所述钝化层上方且通过保形填充所述钝化层中的暴露所述多个互连层其中之一的第一导电体的一个或多个开口而连接于所述第一导电体，其中在所述铝引线接合焊盘正下方的所述多个铜互连层的顶端互连层中形成第二导电体，所述第二导电体仅通过所述钝化层与所述铝引线接合焊盘电隔离且不直接连接于引线接合焊盘。
根据本发明，提供一种用于形成集成电路的方法，包含步骤：提供具有有源电路的衬底；在所述衬底上形成多个铜互连层；在所述多个铜互连层上沉积钝化层；在所述钝化层中形成一个或多个开口，以便暴露所述多个铜互连层的第一导电体；以及在所述钝化层的一个或多个开口上形成铝引线接合焊盘，该铝引线接合焊盘保形地填充所述一个或多个开口，以便使所述铝引线接合焊盘连接于所述第一导电体，其中所述铝引线接合焊盘形成于在所述多个铜互连层的顶端互连层中形成的第二导电体的正上方，所述第二导电体仅通过所述钝化层与所述铝引线接合焊盘电隔离，其中所述导电体不直接连接于引线接合焊盘。
现在，铜通常用于集成电路的互连。然而，因为与铜的引线接合问题，用于铜互连技术的引线接合焊盘通常使用铝层来覆盖暴露的铜引线接合焊盘。这种铝帽的增加允许使用在铝互连技术中使用的引线接合工具和工艺。
图1示出了具有现有技术的引线接合焊盘13的半导体器件10的剖面图。半导体器件10包括硅衬底19、互连区域20、钝化层15和引线接合焊盘叠层13。在硅衬底19上形成有源电路。互连区域20包括铜层21，22，和23，层间通路层在铜层21，22和23以及衬底19的有源电路之间提供电连接。在多层金属铜技术中，引线接合焊盘叠层13的铜部分12由铜互连区域20的最末的、最后的或顶部层21形成。在最末的IC钝化层15上切出较大的开口，宽度和高度为50-100微米(μm)，从而露出铜焊盘12。然后，铝帽14淀积在铜盘12上，绕引线接合区域的周边在钝化层15上逐步升高。
如上所述，按芯片的比例，接合焊盘较大。在通常的芯片设计中，I/O(输入/输出)焊盘单元位于环绕芯片周围的圆环中。接合焊盘通常覆盖该I/O环形区域的一半至四分之一。大的金属电源总线通常也排布在该I/O环内。在许多芯片设计中，电学性能可能受这些总线中的电阻的限制。总线电阻问题的一种解决方案是为工艺流程增加额外的铜金属层，在总线金属叠层中提供另一层，但这导致成本增加。作为选择，I/O环形区域可以增加而提供用于排布电力总线的更大面积，但这也增加成本。
因此，需要一种引线接合焊盘和电力总线及接地总线，可以减轻上述问题的严重性，且不增加成本。
附图说明
图1示出了具有现有技术的引线接合焊盘的半导体器件的剖面图。
图2示出了具有本发明的引线接合焊盘的半导体器件的剖面图。
具体实施方式
总的来说，本发明提供了一种具有接合焊盘的集成电路。所述接合焊盘在集成电路的有源电路和/或电互连层正上方的钝化层上形成。在所述实施例中，接合焊盘由铝形成，电互连层由铜形成。本发明消除了图1所示的引线接合焊盘结构中的绝大多数铜。全标准尺寸的铝焊盘直接淀积在钝化层顶部。在钝化层上切出一或多个小开口，仅视需要提供与下面的芯片电路的电连接。在铝帽的淀积过程中，钝化切口用铝填充，形成直至一或多个下面的最末金属层铜互连的通孔。应指出的是，最末金属层铜互连可以相当小，且仅需视需要放置，而有利于高效互连。在铝引线接合焊盘下方的最末金属层铜的较大面积现在可用于电力总线，或其他互连，且可以与上方的铝接合焊盘电隔离。
在所述实施例中，用于引线接合的铝帽是标准制造流程的一部分。所以，本发明提供了更有效的优点，附加的铜金属层，限于引线接合焊盘正下方的区域，且没有增加成本。因为引线接合焊盘可以较大，所以这可以在I/O环形排布区域和/或电学性能上有明显的影响。
在引线接合焊盘下方的区域可用于导电，接地或传导信号穿过集成电路。而且，在引线接合焊盘下方排布的最末金属层铜导体可以与引线接合焊盘无关或独立。此外，通过使用引线接合焊盘下方的区域，可以减小半导体芯片的表面积。
图2示出了本发明另一实施例的半导体器件50的剖面图。应指出的是该图不是按比例绘出的。半导体器件50具有边缘，或者周边25，钝化层18，互连区24，衬底或有源区26和接合焊盘53。应指出的是，与图1中示出的现有技术的铝包铜焊盘对比，图2中示出的焊盘仅由铝制成。由通过钝化层18上的小切口形成的两个填充铝的通孔提供从接合焊盘53到最末金属层28的最末金属部分51和52的电连接。请注意在铝接合焊盘53上的凹陷，在此铝已经保形地填充了小钝化切口。钝化层18覆盖在接合焊盘53下方的较大面积的引线接合区，且使铜金属层28的部分54与铝接合焊盘53电隔离。部分54是用于在引线接合焊盘53下方为电源、地线和其他信号布线的金属导体的剖面。部分54可以跨过沿周边25形成的多个相邻引线接合焊盘下面的大部分的半导体器件。部分45可以，或可以不连接于引线接合焊盘53。最末金属部分51和52可以是向铝焊盘53及其下面的互连提供电连接所必须的或所需的任何尺寸和形状。而且，在其他实施例中，可以有两个以上，或小于两个的、使所述接合焊盘电连接于互连层28、30和32的最末金属部分51和52。
在优选实施例中，钝化切口的最小高度或宽度是3μm。使用最小尺寸是3×3μm的方形切口，以及直至3×50μm的矩形切口。
在一个实施例中，接合焊盘53相对靠近半导体器件50的周边25定位。通常，沿周边25排列多个类似于接合焊盘53的引线接合焊盘(未示出)，以便提供与半导体器件50的外部连接。而且，可以根据需要在铝焊盘53和最末金属部分51和52之间使用阻挡层(未示出)。所述阻挡层可以由钽形成。但在其他实施例中，所述阻挡层可以是在不同且相邻的材料之间形成扩散阻挡和粘结层的任何材料。扩散和阻挡材料的示例是氮化钽、钛、氮化钛、镍、钨、钛钨合金和氮化硅钽。
接合焊盘53可以由铝形成，最末金属层部分51和52可以由铜形成。然而，本领域的技术人员可认识到接合焊盘53可以是含铝的合金，最末金属层部分51和52可以是包含铜的合金。接合焊盘53形成相对较厚的铝层。铝焊盘53的厚度可以介于约0.5至2.0微米之间。互连区24包括用于在半导体器件20的各种元件之间为电源、地线、信号和其他线路布线的金属层28，30和32。应注意的是每个金属层28，30和32使用绝缘材料互相隔开。如上所述，最末金属层28包括位于引线接合焊盘53正下方的导体，所述导体也用于为电源、地线和其他信号布线。
半导体器件50通过常规的制造技术，在衬底，或有源区域26上形成电路。所述电路可以用于各种集成电路应用，比如，通信、运输、通用计算，或娱乐。在所示的实施例中，金属层28，30，和32形成在导体材料中，例如，铝、铜、或金。在其他实施例中，可以有更多或更少的金属层。
在接合焊盘53正下方的互连层28，30，和32，用于排布跨过集成电路的用于电源、地线和信号的一或多个导电体54，从而使所述半导体器件的总体尺寸可以更小。而且，不直接连接于所述接合焊盘的电源和地线布线层可以围绕所述接合焊盘下的集成电路，从而减小电源总线电阻，且没有增加集成电路的尺寸或增加制造的复杂性。在引线接合位于接合焊盘53上的实际区域可以在钝化切口正上方。作为选择，接合焊盘53可以拉长而超过引线接合所在的区域，以便形成与远离引线接合区的最末层部分51或52的连接。另外，引线接合焊盘53可以位于集成电路中的任何位置，甚至是远离相关I/O电路的位置，从而允许最大的IC设计和封装柔性。铝引线接合层也可以用作互连层，无需叠加的任何钝化层，例如，使所述引线接合焊盘电连接于其他电路部分。此外，因为最末金属层部分51和52不用于探针试验或引线接合，最末金属层部分51和52的尺寸和形状，以及钝化层18上的开口的尺寸和形状仅受为接合焊盘53提供连接所需的面积的限制。此外，因为半导体器件可以做得更小，所以每个晶片上的芯片数量可以增加，从而降低成本。
在前述内容中，已经参照具体实施例描述了本发明。然而，本领域的技术人员将认识到可以作出多种改进和变化，而不脱离如下权利要求中公开的本发明的范围。因此，说明书和附图被认为是示例性的，而不是限制性的，且所有这些改进意味着包括在本发明的范围内。
在上面已经对照具体实施例描述了益处、其他优点和问题的解决方案。然而，可能导致任何益处、优点和解决方案发生或变得更显著的所述益处、优点、问题的解决方案及其他要素不应解释为任一或全部权利要求的关键的、必须的或基本的特征或要素。如在此使用的，术语“包含”、“含有”或其任何变体，意谓着覆盖非排他性的包含物，比如工艺、方法、物品或设备，包含一组要素，但不仅包括这些要素，而是可以包括未明确列出或这些工艺、方法、物品或设备固有的其他要素。

Claims (10)

1.一种集成电路，包含：
具有有源电路的衬底；
在所述衬底上形成的多个铜互连层；
在所述多个铜互连层上形成的钝化层；以及
铝引线接合焊盘，该铝引线接合焊盘形成在所述钝化层上方且通过保形填充所述钝化层中的暴露所述多个铜互连层其中之一的第一导电体的一个或多个开口而连接于所述第一导电体，其中在所述铝引线接合焊盘正下方的所述多个铜互连层的顶端互连层中形成第二导电体，所述第二导电体仅通过所述钝化层与所述铝引线接合焊盘电隔离且不直接连接于铝引线接合焊盘。
2.如权利要求1所述的集成电路，其特征在于，所述第二导电体用于为集成电路上的电路提供电源电压。
3.如权利要求1所述的集成电路，其特征在于，所述铝引线接合焊盘利用穿过所述钝化层直至所述顶端互连层的接触的一个或多个被保形填充的通孔而连接于所述多个铜互连层之一。
4.如权利要求1所述的集成电路，其特征在于，所述多个铜互连层中的顶端互连层包括用于在铝引线接合焊盘正下方提供电源电压的第三导电体，且所述第三导电体不直接连接于所述铝引线接合焊盘。
5.一种用于形成集成电路的方法，包含以下步骤：
提供具有有源电路的衬底；
在所述衬底上形成多个铜互连层；
在所述多个铜互连层上沉积钝化层；
在所述钝化层中形成一个或多个开口，以便暴露所述多个铜互连层的第一导电体；以及
在所述钝化层的一个或多个开口上形成铝引线接合焊盘，该铝引线接合焊盘保形地填充所述一个或多个开口，以便使所述铝引线接合焊盘电连接于所述第一导电体，其中所述铝引线接合焊盘形成于在所述多个铜互连层的顶端互连层中形成的第二导电体的正上方，所述第二导电体仅通过所述钝化层与所述铝引线接合焊盘电隔离，其中所述第二导电体不直接连接于铝引线接合焊盘。
6.如权利要求5所述的方法，其特征在于，形成所述铝引线接合焊盘的步骤包含形成0.5至2.0微米厚的铝引线接合焊盘。
7.如权利要求5所述的方法，其特征在于，所述第二导电体用于为集成电路上的电路提供电源电压。
8.如权利要求5所述的方法，其特征在于，还包含使用一个或多个穿过所述钝化层的通孔使所述铝引线接合焊盘连接于所述多个铜互连层之一的步骤。
9.如权利要求5所述的方法，其特征在于，在顶端互连层中形成第三导电体，用于在铝引线接合焊盘正下方提供电源电压，该第三导电体不直接连接于所述铝引线接合焊盘。
10.如权利要求6所述的方法，其特征在于，还包含使用一个或多个穿过所述钝化层的通孔使所述铝引线接合焊盘连接于所述多个铜互连层之一的步骤。
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