CN100458977C - Apparatus and method for adaptive controlling flash storage interface reading and writing speed - Google Patents
Apparatus and method for adaptive controlling flash storage interface reading and writing speed Download PDFInfo
- Publication number
- CN100458977C CN100458977C CNB2007100989146A CN200710098914A CN100458977C CN 100458977 C CN100458977 C CN 100458977C CN B2007100989146 A CNB2007100989146 A CN B2007100989146A CN 200710098914 A CN200710098914 A CN 200710098914A CN 100458977 C CN100458977 C CN 100458977C
- Authority
- CN
- China
- Prior art keywords
- read
- write
- flash
- speed
- write operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000003044 adaptive effect Effects 0.000 title claims description 23
- 230000014759 maintenance of location Effects 0.000 claims description 65
- 230000001276 controlling effect Effects 0.000 claims description 22
- 238000004904 shortening Methods 0.000 claims description 14
- 238000012360 testing method Methods 0.000 claims description 14
- 230000001105 regulatory effect Effects 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000012795 verification Methods 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 5
- 230000000052 comparative effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Abstract
This invention provides a device and a method for controlling read-write speed of flash interfaces adaptively, which reads and writes data to a flash blank region and judges if wrong read-write appears, if there is not error, it reduces the set-up and kept time to flash read-write waveforms till read-write errors appear so as to speed up read-write speed of flash interfaces.
Description
Technical field
The present invention relates to the technical field of flash memory, be specifically related to the apparatus and method of adaptive controlling flash storage memory interface speeds.
Background technology
At present, along with science and technology development, for storage medium, the raising of memory access speed is the problem that people concern very much.Because storage medium manufacturer is very many, the kind of storage medium and model are also just very many, and concentrating the talk of NAND FLASH flash memory just has the hundreds of kind.Yet the interface protocol of the product of each producer and speed sequential require to be not quite similar.For the storer of compatible different model, need chip controller according to different memory interface protocol, dispose suitable instruction and interface transmission speed.In the prior art, need the user that controller is carried out some configurations, essential informations such as the type of memory that makes chip controller identify to be connect, interface rate usually.
Like this, under the applied environment that lacks configuration tool, use flash memory to become very inconvenient with multiple transmission speed; If use fixing lower interface rate, with make speed faster flash memory can not bring into play the superiority of speed aspect.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of device and method of adaptive controlling flash storage interface reading and writing speed, need not to increase extra dispensing unit, system just can make the interface reading and writing speed of flash memory reach the fastest easily.For achieving the above object, the device of a kind of adaptive controlling flash storage interface reading and writing speed provided by the invention comprises flash cell, read-write control unit, read-write operation detecting unit, read or write speed adjustment module, wherein
Described flash cell has the clear area that can store the data that described read-write control unit writes;
Described read-write control unit, be used for according to default or current read or write speed from described read or write speed adjustment module, write the data of user preset to the clear area of described flash cell, and after write operation is finished, read this data from the clear area of described flash cell, and the data that read are sent to described read-write operation detecting unit with identical read or write speed;
Described read-write operation detecting unit is used to detect read-write operation and mistake whether occurs, and testing result is sent to read-write control unit;
Described read-write control unit, also be used for testing result according to the transmission of read-write operation detecting unit, send the steering order of regulating current read or write speed to described read or write speed adjustment module, with when read-write operation is not made mistakes, control described read or write speed adjustment module and accelerate current read or write speed, make mistakes until read-write operation; And when read-write operation is made mistakes, control described read or write speed adjustment module and reduce current read or write speed, correct until read-write operation, thus the read or write speed after obtaining to regulate to flash memory.
Described read or write speed adjustment module comprise Time Created regulon and Time Created storage unit;
Described Time Created, regulon was used for the control command of the adjusting read or write speed that sends according to described read-write control unit, regulated the read-write waveform Time Created to flash memory;
Described Time Created storage unit, be used for the stored adjustment gained to flash reading and writing waveform value Time Created.
Described read or write speed adjustment module comprises retention time regulon and retention time storage unit;
Described retention time regulon is used for the control command according to the adjusting read or write speed of described read-write control unit transmission, regulates the flash reading and writing waveform retention time;
Described retention time storage unit, be used for the stored adjustment gained to flash reading and writing waveform retention time value.
Whether described read-write operation detecting unit is the read-write comparing unit, be used for comparison and equate with the data that read-write control unit writes flash cell from the data of read-write control unit, and comparative result is sent to read-write control unit;
Or,
Described read-write operation detecting unit is the read-write check unit, is used for the correctness of the data that verification read from the flash cell clear area by read-write control unit, draws check results, and sends to read-write control unit.
Described flash memory is NAND FLASH.
The present invention also provides a kind of method of interface reading and writing speed of adaptive controlling flash storage, may further comprise the steps:
1) writes data with default or current read or write speed to the flash memory clear area;
2) with the read or write speed identical with step 1) from flash memory clear area reading of data;
3) detect read-write operation and whether make a mistake, obtain testing result;
4) regulate current read or write speed according to step 3) gained testing result, if being read-write operation, the gained testing result do not make a mistake, then accelerate current read or write speed, with the read or write speed after accelerating as current read or write speed, and return step 1), otherwise it is correct until read-write operation to reduce current read or write speed, thus the read or write speed after obtaining to regulate to flash memory.
Whether the detection read-write operation makes a mistake and be specially in the described step 3): relatively whether the data that read from the flash memory clear area equate with the data of the user preset that writes to the flash memory clear area, if both are equal, show that then read-write operation does not make a mistake; Otherwise show that read-write operation makes a mistake;
Or,
Default check code is write the flash memory clear area, and carry out verification,, show that then read-write operation does not make a mistake if check code is correct; Otherwise show that read-write operation makes a mistake.
Described quickening is to the read or write speed of flash memory, by shortening Time Created and/or the retention time realization to the flash reading and writing waveform; Described reduction is to the read or write speed of flash memory, by prolonging Time Created and/or the retention time realization to the flash reading and writing waveform.
Described shortening was specially the Time Created and/or the retention time of flash reading and writing waveform: will successively decrease with a fixed value to the Time Created and/or the retention time of flash reading and writing waveform.
The Time Created and/or the retention time of described prolongation flash reading and writing waveform, be specially: current Time Created and/or the retention time to the flash reading and writing waveform added the fixed value that the last time deducts when shortening Time Created or retention time.
In the described step 1), default read or write speed is to read and write wave period more than or equal to 50ns, and adopts described default read or write speed when for the first time read-write operation being carried out in the flash memory clear area.
If judged result be read-write operation make mistakes after flash memory is carried out read-write operation the described first time, and then system reports an error.
By above technical scheme as seen, the apparatus and method of adaptive controlling flash storage interface reading and writing speed provided by the invention, read and write data by clear area to flash memory, and judge whether to occur the wrong phenomenon of read-write, under the situation that read-write operation does not make a mistake, shortening until appearance read-write mistake, thereby reaches the interface reading and writing speed that adds flash memory to the Time Created and the retention time of flash reading and writing waveform.Like this, solved the problem of the flash memory that in the applied environment that lacks configuration tool, is difficult to use easily multiple transmission speed in the prior art.
Further, because read-write operation is to make mistakes when read or write speed surpasses maximal value, be not fully exerted so can guarantee the flash memory fast reading and writing.
Description of drawings
Fig. 1 is an adaptive controlling flash storage interface reading and writing speed apparatus structure synoptic diagram provided by the invention;
Fig. 2 is a kind of specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
Fig. 3 is the another kind of specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
Fig. 4 is another specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
Fig. 5 is the method flow diagram according to adaptive controlling flash storage interface reading and writing speed provided by the invention;
Fig. 6 is a kind of specific embodiment synoptic diagram according to adaptive controlling flash storage interface reading and writing speed provided by the invention of example with NAND FLASH for flash memory.
Embodiment
Apparatus and method according to adaptive controlling flash storage interface reading and writing speed provided by the invention, by clear area write-read check code to flash memory, and the correctness of judgement institute read check sign indicating number, thereby judge whether to occur the wrong phenomenon of read-write, under the correct situation of check code, transfer fast read-write Time Created and retention time, until the read-write mistake occurring, to add the interface reading and writing speed of flash memory.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 1 is an adaptive controlling flash storage interface reading and writing speed device synoptic diagram provided by the invention.
As shown in Figure 1, this device comprises flash cell 101, read-write control unit 102, read-write operation detecting unit 103, read or write speed adjustment module 104.
Wherein, described flash cell 101 is used to store data, and this unit keeps a clear area and is used to store the data that described read-write control unit 102 writes.
Described read-write control unit 102, be used for the data that flash reading and writing speed write user preset to the clear area of described flash cell with default or current, and after write operation is finished, read this data from the clear area of described flash cell, and the data that read are sent to described read-write operation detecting unit 103 with identical speed.。
Described read-write operation detecting unit 103 is used to detect read-write operation and mistake whether occurs, and draws testing result.
Described read-write operation detecting unit 103 can be the read-write comparing unit, relatively whether the data from read-write control unit 102 equate with the data (these data are preestablished by the user) that read-write control unit 102 writes flash cell 101, and comparative result is sent to read-write control unit 102.
Described read-write operation detecting unit 103 also can be a verification unit, and the correctness of the data that verification unit is read from flash cell 101 clear areas by read-write control unit 102 by verification draws check results, and sends to read-write control unit 102.
Described read-write control unit 102, the testing result that also is used for sending according to the read-write operation detecting unit is to described read or write speed adjustment module transmitting control commands, if testing result is then sent the control command of accelerating read or write speed for not operation, otherwise send the control command that reduces read or write speed.
Described read or write speed adjustment module 104 is used for the control command according to described read-write control unit transmission, regulates the read or write speed to flash memory.
When powering on to system, also do not know the interface reading and writing speed situation of current flash memory this moment, therefore in order to improve reliability and compatibility, needs to determine a flash storage interface reading and writing speed the most basic, makes system be in the tick-over state.Such as, in the prior art, be generally 50ns the access cycle of read-write NAND FLASH.Among the present invention, can set in advance the read-write wave period to NAND FLASH, this read-write wave period is more than or equal to 50ns, as being the cycle NAND FLASH to be carried out read-write operation with 20 times of 50ns.
Described read-write control unit 102 writes the data of user preset for the first time to the clear area of described flash cell 101 with the most basic default read or write speed, after write operation is finished, with identical speed from described flash cell 101 clear area reading of data, and the data that read are delivered to described read-write operation detecting unit 103, detect read-write and whether make a mistake.
Make a mistake if detect read-write operation, then illustrating has bad piece or has other problems in the flash memory, and the processing that reports an error is done by system; Otherwise described read-write control unit 102 sends the control command of quickening read or write speed to described read or write speed adjustment module 104, described read or write speed adjustment module 104 receives order, quickening is to the read or write speed of flash memory, and the read or write speed of regulating the back gained will be as the read or write speed of read-write operation next time.
In read-write operation next time, described read-write control unit 102 writes the data of user preset to the clear area of described flash cell 101 with the speed of regulating the back gained, after write operation is finished, described read-write control unit 102 with identical speed from described flash cell 101 clear area reading of data, and the data that read are delivered to described read-write operation detecting unit 103, detect mistake whether occurs reading and writing.
The read-write mistake do not occur if detect, described read-write control unit 102 sends the control command of accelerating read or write speed to described read or write speed adjustment module 104, and described read or write speed adjustment module 104 is accelerated flash reading and writing speed according to the control command that receives; If detecting read-write operation makes a mistake, this moment, flash storage interface reading and writing speed surpassed maximal value, described read-write control unit 102 sends the control command that reduces read or write speed to described read or write speed adjustment module 104, described read or write speed adjustment module 104 will reduce the read or write speed of flash memory according to the control command that receives, and is correct until read-write operation.
Accelerating current read or write speed described in the embodiments of the invention can improve step by step; The current read or write speed of described reduction can reduce step by step, also can be accelerated read or write speed value (being the read or write speed when last time, read-write operation was not made mistakes) before the last time as the read or write speed value after reducing.
Described adjusting read or write speed can adopt regulates read-write Time Created of waveform and reaching of retention time simultaneously, and Time Created or the retention time that also can regulate the read-write waveform separately reach.
Fig. 2 is a specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
In the present embodiment, described read or write speed adjustment module 204 comprises read-write waveform regulon Time Created 204a and read-write waveform storage unit Time Created 204b.
Receive the control command of accelerating read or write speed when described read or write speed adjustment module 204, described read-write waveform regulon Time Created 204a shortens Time Created, and the value after will shortening stores described read-write waveform storage unit Time Created 204b into, as the Time Created of reading and writing waveform next time.
When described read or write speed adjustment module 204 receives the control command that reduces read or write speed, described read-write waveform regulon Time Created 204a prolongs Time Created to last value before shortening Time Created.
Fig. 3 is another specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
In the present embodiment, described read or write speed adjustment module 304 comprises read-write waveform retention time regulon 304a and read-write waveform retention time storage unit 304b, and principle of work is identical with specific embodiment shown in Figure 2.
Fig. 4 is another specific embodiment synoptic diagram of adaptive controlling flash storage interface reading and writing speed device provided by the invention.
In this example, described read or write speed adjustment module 404 comprises read-write waveform regulon Time Created 404a and read-write waveform storage unit Time Created 404b, read-write waveform retention time regulon 404c and read-write waveform storage unit Time Created 404d.
Receive the control command of regulating read or write speed when described read or write speed adjustment module 404, described read-write waveform regulon Time Created 404a and described read-write waveform retention time regulon shorten or prolong the Time Created and the retention time of read-write waveform simultaneously, and the value after will regulating stores among described read-write waveform storage unit Time Created 404b and the described read-write waveform retention time storage unit 404d, as Time Created of reading and writing waveform and retention time next time.
As a kind of specific embodiment, if shorten the method for Time Created and retention time is that the retention time Time Created storage unit of read-write waveform is successively decreased with a fixed value, the method that the then described Time Created that will read and write waveform and retention time extend to last value before shortening Time Created and retention time be exactly make be stored in described Time Created storage unit 404b and described retention time storage unit 404d in value add this fixed value, resulting like this value is when read-write operation is made mistakes, read-write Time Created of waveform and the value of retention time are flash memory pairing read-write waveform Time Created and retention time when reaching maximum read or write speed.
Fig. 5 is the process flow diagram according to adaptive controlling flash storage interface reading and writing speed provided by the invention.Concrete steps are as follows:
Step 500 powers on to system, and system is in lower-speed state;
Step 501 writes data with current read or write speed to the flash memory clear area;
Whether step 503 detects read-write operation and makes a mistake, and obtains testing result;
Whether described detection read-write operation makes a mistake, and can if both are equal, show that then read-write operation does not make a mistake by relatively whether equating to judge to flash memory clear area data that write and the data that read from the flash memory clear area; Otherwise show that read-write operation makes a mistake.
Also can pass through default check code, and check code is write the flash memory clear area, and carry out verification.If check code is correct, show that then read-write operation does not make a mistake; Otherwise show that read-write operation makes a mistake.
If the result of step 503 gained then accelerates current read or write speed for the read-write mistake does not take place, until detecting the read-write mistake takes place; Otherwise reduce current read or write speed until the read-write mistake no longer takes place.
The current read or write speed of described quickening can improve step by step; The current read or write speed of described reduction can reduce step by step, also can be accelerated read or write speed value before the last time as the read or write speed value after reducing.
Described quickening or reduction are to the read or write speed of flash memory, can shorten or prolong the Time Created of flash reading and writing waveform separately or shorten or prolong retention time of read-write waveform separately, also can be Time Created and the retention time that shortens simultaneously or prolong the flash reading and writing waveform.Because in present flash memory market, the interface rate kind that belongs to NAND FLASH is more, the situation that needs to regulate interface rate more frequently occurs, so, be example with NAND FLASH below, the present invention will be described in more detail.
Fig. 6 is the embodiment synoptic diagram according to adaptive controlling flash storage interface reading and writing speed provided by the invention of example with NAND FLASH for flash memory.
In the present embodiment, judge whether wrong method to occur reading and writing relatively to pass through read-write operation, whether the data that read from flash memory equate to be example with the data of user preset; Quickening is example to the method for flash reading and writing speed with Time Created and the retention time that shortens the read-write waveform simultaneously.The concrete steps of adaptive controlling flash storage interface reading and writing speed provided by the invention are as follows:
During owing to power on, and do not know, to need the interface reading and writing speed situation of current NAND FLASH to determine a interface reading and writing speed the most basic, make system be in the tick-over state therefore in order to improve reliability and compatibility in system.In the prior art, be generally 50ns the access cycle of read-write NAND FLASH.In the present embodiment, set in advance read-write wave period to NAND FLASH, this read-write wave period is more than or equal to 50ns, as being the cycle NAND FLASH to be carried out read-write operation, just Time Created and the retention time that can determine to read and write waveform according to default read-write wave period with 20 times of 50ns.
Step 601 for the first time according to Time Created and the retention time to the read-write waveform of NAND FLASH that set in advance, is write the data that access customer sets in advance to NAND FLASH clear area.
Step 602 is according to the Time Created and the retention time of default read-write waveform to NAND FLASH, from NAND FLASH clear area reading of data.
Step 605, system reports an error.
Step 605 shortens Time Created and retention time to NAND FLASH read-write waveform, and storage.
Step 606 is according to Time Created of NAND FLASH read-write waveform and retention time are write the data from user preset to NAND FLASH clear area of storage in the step 605.
Step 607, according to storage in the step 605 to Time Created of NAND FLASH read-write waveform and retention time from NAND FLASH clear area reading of data.
Whether step 608, the data that read in the determining step 607 equate with the data of the user preset that writes in the step 606, if equate that then execution in step 609, and return step 606; Otherwise, execution in step 610.
Step 609 shortens Time Created and retention time to NAND FLASH read-write waveform, and storage.
Step 610 will extend to last preceding Time Created and the retention time of shortening to the Time Created and the retention time of NAND FLASH read-write waveform.
Step 611 finishes the Time Created of NAND FLASH read-write waveform and the adjusting of retention time.
In described step 605 and the step 609, shortening is to the Time Created and the retention time of NAND FLASH read-write waveform, can be by the Time Created and the retention time of current read-write waveform be successively decreased with a fixed value, also can pass through Time Created and retention time doubling are realized, thereby reach the effect of accelerating NAND FLASH read or write speed.
In the present embodiment, a kind of method shortens Time Created and the retention time to NAND FLASH read-write waveform before adopting, so, to extend to Time Created and retention time before last the shortening to Time Created of NAND FLASH read-write waveform and retention time described in the described step 610, be to add that by Time Created and retention time with the read-write waveform of current storage the fixed value that shortening was successively decreased during the time obtains.
By the above embodiments as seen, adopt apparatus and method provided by the invention, solved the problem of the flash memory that in the applied environment that lacks configuration tool, is difficult to use easily multiple transmission speed in the prior art, by regulating the read-write waveform Time Created and the retention time of flash memory, to reach the effect of accelerating its interface literary sketch speed, need not extra configuration tool; Because read-write operation is to make mistakes when read or write speed surpasses maximal value, be not fully exerted further so can guarantee the flash memory fast reading and writing.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Those skilled in the art can change accordingly according to embodiments of the invention, such as the identifying information that can add other in the clear area of flash memory, is used to judge whether occur the read-write mistake; Also not only being limited in the scope of flash memory for storer, can also be other storage mediums, as long as the read or write speed of this storage medium can just can realize by one or several parameter that changes other, can adopt apparatus and method provided by the invention.Therefore within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1, a kind of device of adaptive controlling flash storage interface reading and writing speed is characterized in that: described device comprises flash cell, read-write control unit, read-write operation detecting unit, read or write speed adjustment module, wherein
Described flash cell has the clear area that can store the data that described read-write control unit writes;
Described read-write control unit, be used for according to default or current read or write speed from described read or write speed adjustment module, write the data of user preset to the clear area of described flash cell, and after write operation is finished, read this data from the clear area of described flash cell, and the data that read are sent to described read-write operation detecting unit with identical read or write speed;
Described read-write operation detecting unit is used to detect read-write operation and mistake whether occurs, and testing result is sent to read-write control unit;
Described read-write control unit, also be used for testing result according to the transmission of read-write operation detecting unit, send the steering order of regulating current read or write speed to described read or write speed adjustment module, with when read-write operation is not made mistakes, control described read or write speed adjustment module and accelerate current read or write speed, make mistakes until read-write operation; And when read-write operation is made mistakes, control described read or write speed adjustment module and reduce current read or write speed, correct until read-write operation, thus the read or write speed after obtaining to regulate to flash memory.
2, device as claimed in claim 1 is characterized in that:
Described read or write speed adjustment module comprise Time Created regulon and Time Created storage unit;
Described Time Created, regulon was used for the control command of the adjusting read or write speed that sends according to described read-write control unit, regulated the read-write waveform Time Created to flash memory;
Described Time Created storage unit, be used for the stored adjustment gained to flash reading and writing waveform value Time Created.
3, device as claimed in claim 1 or 2 is characterized in that: described read or write speed adjustment module comprises retention time regulon and retention time storage unit;
Described retention time regulon is used for the control command according to the adjusting read or write speed of described read-write control unit transmission, regulates the flash reading and writing waveform retention time;
Described retention time storage unit, be used for the stored adjustment gained to flash reading and writing waveform retention time value.
4, device as claimed in claim 3, it is characterized in that: described read-write operation detecting unit is the read-write comparing unit, be used for comparison and whether equate with the data that read-write control unit writes flash cell, and comparative result is sent to read-write control unit from the data of read-write control unit;
Or,
Described read-write operation detecting unit is the read-write check unit, is used for the correctness of the data that verification read from the flash cell clear area by read-write control unit, draws check results, and sends to read-write control unit.
5, device as claimed in claim 4 is characterized in that: described flash memory is NAND FLASH.
6, a kind of method of interface reading and writing speed of adaptive controlling flash storage is characterized in that: described method may further comprise the steps:
1) writes data with default or current read or write speed to the flash memory clear area;
2) with the read or write speed identical with step 1) from flash memory clear area reading of data;
3) detect read-write operation and whether make a mistake, obtain testing result;
4) regulate current read or write speed according to step 3) gained testing result, if being read-write operation, the gained testing result do not make a mistake, then accelerate current read or write speed, with the read or write speed after accelerating as current read or write speed, and return step 1), otherwise it is correct until read-write operation to reduce current read or write speed, thus the read or write speed after obtaining to regulate to flash memory.
7, method as claimed in claim 6, it is characterized in that: whether the detection read-write operation makes a mistake and be specially in the described step 3): relatively whether the data that read from the flash memory clear area equate with the data of the user preset that writes to the flash memory clear area, if both equate, show that then read-write operation does not make a mistake; Otherwise show that read-write operation makes a mistake;
Or,
Default check code is write the flash memory clear area, and carry out verification,, show that then read-write operation does not make a mistake if check code is correct; Otherwise show that read-write operation makes a mistake.
8, method as claimed in claim 7 is characterized in that: described quickening is to the read or write speed of flash memory, by shortening Time Created and/or the retention time realization to the flash reading and writing waveform; Described reduction is to the read or write speed of flash memory, by prolonging Time Created and/or the retention time realization to the flash reading and writing waveform.
9, method as claimed in claim 8 is characterized in that: described shortening was specially the Time Created and/or the retention time of flash reading and writing waveform: will successively decrease with a fixed value to the Time Created and/or the retention time of flash reading and writing waveform.
10, method as claimed in claim 8, it is characterized in that: the Time Created and/or the retention time of described prolongation flash reading and writing waveform, be specially: current Time Created and/or the retention time to the flash reading and writing waveform added the fixed value that the last time deducts when shortening Time Created or retention time.
11, method as claimed in claim 6 is characterized in that: in the described step 1), default read or write speed is to read and write wave period more than or equal to 50ns, and adopts described default read or write speed when for the first time read-write operation being carried out in the flash memory clear area.
12, method as claimed in claim 11 is characterized in that: if judged result be read-write operation make mistakes after flash memory is carried out read-write operation the described first time, and then system reports an error.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100989146A CN100458977C (en) | 2007-04-29 | 2007-04-29 | Apparatus and method for adaptive controlling flash storage interface reading and writing speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100989146A CN100458977C (en) | 2007-04-29 | 2007-04-29 | Apparatus and method for adaptive controlling flash storage interface reading and writing speed |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101067968A CN101067968A (en) | 2007-11-07 |
| CN100458977C true CN100458977C (en) | 2009-02-04 |
Family
ID=38880484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100989146A Expired - Fee Related CN100458977C (en) | 2007-04-29 | 2007-04-29 | Apparatus and method for adaptive controlling flash storage interface reading and writing speed |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100458977C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013060215A1 (en) * | 2011-10-27 | 2013-05-02 | 忆正科技（武汉）有限公司 | Flash memory controller and method of data transmission between flash memories |
| CN106683709A (en) * | 2016-12-28 | 2017-05-17 | 西北工业大学 | Method for evaluating NOR and NAND flash memory performance |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101572123B (en) * | 2009-05-31 | 2012-04-04 | 成都市华为赛门铁克科技有限公司 | Control device of non-volatile storage, method and system thereof for dispatching data |
| CN101986329A (en) * | 2010-09-16 | 2011-03-16 | 建荣集成电路科技(珠海)有限公司 | Method for self-adapting communication of data line by card reading device |
| CN104601921A (en) * | 2015-01-15 | 2015-05-06 | 上海小蚁科技有限公司 | System configuration method and device |
| CN104778126B (en) * | 2015-04-20 | 2017-10-24 | 清华大学 | Transaction Information storage optimization method and system in non-volatile main |
| CN109036494A (en) * | 2018-07-20 | 2018-12-18 | 江苏华存电子科技有限公司 | A kind of method of quick detection flash memory flaw |
| CN109903800A (en) * | 2019-03-15 | 2019-06-18 | 中国科学院上海微系统与信息技术研究所 | Phase change memory control device, phase change memory control method, electronic device and storage medium |
| CN110018789B (en) * | 2019-03-26 | 2022-03-25 | 记忆科技(深圳)有限公司 | Method, device and storage medium for dynamically adapting Tr and Tprom time of NAND |
| CN110765041B (en) * | 2019-10-22 | 2023-06-09 | 天津津航计算技术研究所 | Self-adaptive Nand Flash read-write speed adjusting system |
| CN110765042B (en) * | 2019-10-22 | 2023-06-09 | 天津津航计算技术研究所 | Self-adaptive Nand Flash read-write speed adjusting method |
| CN110867203B (en) * | 2019-11-19 | 2021-12-14 | 上海华力微电子有限公司 | Memory read speed regulation circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1983002164A1 (en) * | 1981-12-17 | 1983-06-23 | Ryan, Philip, Meade | Apparatus for high speed fault mapping of large memories |
| US4456995A (en) * | 1981-12-18 | 1984-06-26 | International Business Machines Corporation | Apparatus for high speed fault mapping of large memories |
| CN1035018A (en) * | 1988-01-27 | 1989-08-23 | 约翰弗兰克制造公司 | In device, be used for memory is carried out the method and system of the functional test of high speed pin-point accuracy based on microprocessor |
| US5477492A (en) * | 1993-03-24 | 1995-12-19 | Mitsubishi Denki Kabushiki Kaisha | Memory device to detect and compensate for defective memory cells |
| CN1315732A (en) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | Automatic test method and circuit for RAM |
-
2007
- 2007-04-29 CN CNB2007100989146A patent/CN100458977C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1983002164A1 (en) * | 1981-12-17 | 1983-06-23 | Ryan, Philip, Meade | Apparatus for high speed fault mapping of large memories |
| US4456995A (en) * | 1981-12-18 | 1984-06-26 | International Business Machines Corporation | Apparatus for high speed fault mapping of large memories |
| CN1035018A (en) * | 1988-01-27 | 1989-08-23 | 约翰弗兰克制造公司 | In device, be used for memory is carried out the method and system of the functional test of high speed pin-point accuracy based on microprocessor |
| US5477492A (en) * | 1993-03-24 | 1995-12-19 | Mitsubishi Denki Kabushiki Kaisha | Memory device to detect and compensate for defective memory cells |
| CN1315732A (en) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | Automatic test method and circuit for RAM |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013060215A1 (en) * | 2011-10-27 | 2013-05-02 | 忆正科技（武汉）有限公司 | Flash memory controller and method of data transmission between flash memories |
| CN106683709A (en) * | 2016-12-28 | 2017-05-17 | 西北工业大学 | Method for evaluating NOR and NAND flash memory performance |
| CN106683709B (en) * | 2016-12-28 | 2019-08-09 | 西北工业大学 | NOR and nand flash memory performance measuring and evaluating method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101067968A (en) | 2007-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100458977C (en) | Apparatus and method for adaptive controlling flash storage interface reading and writing speed | |
| US20100325372A1 (en) | Parallel training of dynamic random access memory channel controllers | |
| CN103915119B (en) | Data storage device and flash memory control method | |
| CN109686391B (en) | Nonvolatile memory device, method of operating the same, and nonvolatile memory package | |
| CN106128504B (en) | Storage device and operation method thereof | |
| KR102450930B1 (en) | Memory devices with multiple sets of latencies and methods for operating the same | |
| US8447927B2 (en) | Storage system, control device and storage device | |
| KR20200034189A (en) | Memory system, operating method thereof and non-volatile memory device | |
| CN101515221A (en) | Method, device and system for reading data | |
| CN101923494B (en) | Memory controller verification system, method and scoreboard | |
| CN104484685A (en) | Method and system for issuing smart cards in batched mode | |
| CN102646453A (en) | Method and system for testing error correcting code module in NandFlash controller | |
| CN108302724A (en) | A kind of air-conditioner control system and method | |
| US9489298B2 (en) | Nonvolatile memory apparatus, operating method thereof, and data processing system having the same | |
| US9152348B2 (en) | Data transmitting method, memory controller and data transmitting system | |
| CN106158015A (en) | Resistive formula storage arrangement, read/write circuit unit and operational approach thereof | |
| CN103631737A (en) | Memory data processing system and method | |
| CN110209433B (en) | Method for identifying concentrators of different models | |
| CN111028881B (en) | Open Block testing device, method and system | |
| US7565476B2 (en) | Memory device | |
| TW201702859A (en) | Memory controller including a write performance storage circuit, a write counting circuit and a mapping circuit | |
| TWI833207B (en) | Device and method for selecting clock frequency in master device of bus system | |
| CN102033791B (en) | Method for improving verification efficiency of controller of flash memory, memory device and controller | |
| US8966162B2 (en) | Flash memory controller and method for generating a driving current for flash memories | |
| CN105679320A (en) | Voice control device and voice control method for home appliances |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090204 Termination date: 20120429 |