CN100456496C - 半导体结构和形成该半导体结构的方法 - Google Patents

半导体结构和形成该半导体结构的方法 Download PDF

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CN100456496C
CN100456496C CNB2006100850355A CN200610085035A CN100456496C CN 100456496 C CN100456496 C CN 100456496C CN B2006100850355 A CNB2006100850355 A CN B2006100850355A CN 200610085035 A CN200610085035 A CN 200610085035A CN 100456496 C CN100456496 C CN 100456496C
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盖伊·M.·科恩
保罗·M.·所罗门
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GlobalFoundries Inc
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Abstract

公开了一种具有形成FET沟道的纳米线的垂直FET结构。在导电的硅化物层之上形成纳米线。纳米线通过围绕的栅极而被栅极化。顶部和底部绝缘体插塞用作栅极间隔物并减小栅极-源极和栅极-漏极电容。

Description

半导体结构和形成该半导体结构的方法
技术领域
本发明涉及基于半导体纳米线的电子器件，更具体而言，涉及具有纳米线沟道和硅化物底部接触的垂直场效应晶体管(FET)。本发明还涉及制造含有纳米线沟道和硅化物底部接触的垂直FET的方法。
背景技术
传统的垂直FET是其中的源极-漏极电流在垂直于衬底表面的方向上流动的器件。例如，如果衬底表面制成水平的，则垂直FET通常是垂直的柱子，柱子的顶部和底部部分是漏极和源极。垂直FET的一个主要优点是，不通过光刻来限定沟道长度，而是通过例如外延或层淀积等即使在纳米尺寸也提供良好的厚度控制的的方法来限定。可以在Min Yang等人的“25-nm p-channel vertical MOSFET’s withSiGeC source-drains”，IEEE Electron Dev.Lett.，p.301，(1999)和J.M.Hergenrother等人的“The vertical replacement-gate(VGR)MOSFET：A 50nm vertical MOSFET with lithography-independentgate length”，Int.Electron Dev.Meeting(IEDM)，p.75，1999，中找到垂直FET一些示例。
传统的垂直FET具有几个问题。第一，很难有效地接触柱子底部的源极(或漏极)。这个困难导致到源极(或漏极)的相当高的通路串联电阻。第二，不能通过注入来实现掺杂，而是通过外延期间原地掺杂或从固体源扩散来掺杂。第三，栅极-源极电容很高，因为栅极导体与源极导体交叠。第四，通过柱子的刻蚀或通过从沟槽的外延生长来限定沟道表面；刻蚀通常留下具有反应离子刻蚀(RIE)损伤的粗糙壁，而强制的外延也会表现出缺陷。第五，对于CMOS电路在同一个晶片上制造n-FET和p-FET器件需要在栅极与源极和漏极区域中引入不同的掺杂剂。这是非常困难的，因为与平面FET常规使用的离子注入不兼容。对于上述挑战，现有技术的垂直FET几乎不能用于CMOS技术。
近来的工作已经显示，硅纳米线能够用于制造FET。例如，见Yi Cui等人的“High Performance Silicon Nanowire Field EffectTransistors”，Nano Lett.，3(2)，p.149，(2003)，Andrew B.Greytak等人的“Growth and transport properties of complementarygermanium nanowire field-effect transistors”，Appl.Phys.Lett.，84(21)，p.4176，(2004)和Xiangfeng Duan等人的“High-performancethin-film transistors using semiconductor nanowires andnanoribbons”，Nature，245，p.274，(2003)。到目前为止，报告的纳米线FET主要使用水平配置，其中通过传统的光刻来接触单纳米线，并通过向衬底施加电压来使纳米线背栅极化(见，上述的Yi Cui等人和Andrew B.Greytak等人的论文)。在这些报告中，用于制造FET的接触的纳米线的位置是随机的，并且它们的电流驱动限于单纳米线。
近来报告了使用多个平行纳米线的水平(平面)薄膜晶体管(TFT)，多个平行的纳米线是使用流体流动对准方法组装的(在Langmuir-Blodgett上单轴地压缩)。例如，仍然见Xiangfeng Duan等人的“High-performance thin-film transistors using semiconductornanowires and nanoribbons”，Nature，245，p.274，(2003)。然而，如何精确地定位和定向用于制造大规模的平面纳米线FET的纳米线的问题是当前未解决的问题。
为了获取纳米线的操作，能够建立垂直纳米线FET，其中在纳米线生长的时刻就已经确定了纳米线的位置。在此情况下，FET的沟道包括多个纳米线，以满足指定的电流驱动。在Hou T.Ng等人的“SingleCrystal Nanowire Vertical Surround-Gate Field-Effect Transistor”，Nano Lett.，4(7)，p.1247，(2004)中给出了关于使用单ZnO纳米线沟道的垂直围绕栅极FET的第一报告。
Hou T.Ng等人的论文没有解决与垂直MOSFET相关的如何减小到底部接触的通路电阻以及如何精确控制栅极长度的主要问题。此外，Hou T.Ng等人的论文没有说明如何在MOSFET的制造过程中使用多个纳米线。
考虑到前述问题，需要提供一种包括多个纳米线沟道的垂直FET，其中到底部接触的通路电阻被减小并且栅极长度受到控制。
发明内容
本发明提供一种具有纳米线沟道的垂直FET。本发明的每个垂直FET包括多个纳米线沟道。在晶体导电层(例如硅化物层)上形成用作创造性垂直FET之沟道的纳米线，用于减小到源极的通路串联电阻。通过栅极材料围绕纳米线，并将纳米线制成小的直径(大约在10nm或更小的量级)以获得良好的短沟道特性(例如，本发明基本上减小了因为沟道长度减小导致的MOSFET阈值电压下降的短沟道效应)。以密集阵列形成创造性垂直FET的纳米线，因此减小栅极-源极交叠电容。
在本发明的第一方面中，公开了例如FET的一种半导体结构，包括纳米线沟道，用于控制通过纳米线沟道的电流的围绕栅极，位于每个纳米线中的顶部和底部源极和漏极区域，和导电底部接触层。
具体地，本发明的半导体结构包括位于半导体衬底的一部分上或之内的硅化物接触层；位于所述硅化物接触层上的多个半导体纳米线；围绕所述多个纳米线的栅极电介质；位于所述栅极电介质上的栅极导体；和位于所述纳米线的每个端部的源极和漏极。
更具体地，本发明的FET包括底部外延导电层；位于所述底部外延导电层上的多个半导体纳米线沟道，其中所述多个纳米线沟道垂直于所述底部外延导电层；位于所述纳米线沟道之上的顶部接触层，其中接触层垂直于所述多个半导体纳米线沟道；围绕每个所述半导体纳米线沟道的栅极电介质；围绕所述栅极电介质的栅极导体，其中所述栅极导体通过底部绝缘层与底部外延导电层分开，并且所述栅极导体通过绝缘体插塞与顶部接触层分开；和位于所述多个半导体纳米线沟道的每个端部的源极和漏极。
在本发明的一些实施例中，纳米纳米线沟道之间的间隔与纳米线沟道直径相当。通常，每个纳米线之间的间隔从大约2nm到大约50nm，其基本上等于各个纳米线沟道的直径。
在本发明的第二方面中，公开了通过纳米线沟道制造例如FET的半导体结构的方法。在这些方法的其中一种中，半导体衬底的表面暴露在分配给FET的选择的区域中，并且在暴露的区域中形成硅化物接触层。能够在半导体衬底内其表面部分或半导体衬底的顶部形成硅化物接触。形成的硅化物接触层保护了下面硅的晶体模板；因此硅化物接触层模仿了半导体衬底晶向。催化剂位于硅化物层上，并且垂直于衬底表面生长纳米线。形成的纳米线可以包括与半导体衬底相同或不同的材料。通常从每个纳米线的尖端去除催化剂，并淀积共形的栅极电介质。淀积栅极导体材料，填充纳米线之间的空间。然后通过化学机械抛光(CMP)平坦化该结构。平坦化将纳米线修整为指定的长度并去除了多出的栅极材料。使栅极材料相对于纳米线的顶部表面凹陷。在凹陷区域中形成绝缘体插塞，并形成顶部接触。形成栅极和源极接触通孔从而完成器件制造。
使用硅纳米线和硅处理说明了本发明的方法。也可以通过其它的半导体(例如Ge或III-V族半导体)来实践该方法。使用纳米线的一个优点是，由于其通常较小的直径(几纳米)所以即使出现大的晶格失配也能够在晶体衬底上生长纳米线。例如，能够在硅衬底上生长Ge纳米线。因此，即使衬底是硅也能够通过硅以外的半导体纳米线来制造垂直FET沟道。
附图说明
图1-10和17是给出制造具有纳米线沟道的垂直FET的基本处理步骤的绘图(贯穿的剖面图)。
图11-16是给出用于制造具有纳米线沟道的垂直FET的基本掩模设置的绘图(顶视图)。
图18-31是给出本发明中用于制造具有纳米线沟道的垂直FET的基本处理步骤的第二实施例的绘图(贯穿的剖面图)。
图32-37是给出本发明中用于制造具有纳米线沟道的垂直FET的基本处理步骤的第三实施例的绘图(贯穿的剖面图)。
图38和39是给出本发明另一个实施例的绘图(贯穿的剖面图)，其中纳米线生长在重掺杂外延的半导体层上。
具体实施方式
将通过引用下面的论述详细地说明提供了具有纳米线沟道的垂直FET及其制造方法的本发明。在此论述中，将参照显示本发明实施例的各个附图。由于为了示例的目的而提供了本发明实施例的附图，所以其中所含的结构没有按比例绘制。
再次强调，使用硅纳米线和硅处理来说明本发明的方法。本发明的方法也能够通过其它的半导体(例如Ge或III-V族半导体)来实践。当使用不含硅的半导体时，除了在形成硅化物接触层之前能够在非半导体表面的顶部上形成Si层之外，本发明的处理步骤基本上相同。但是优选地是使用含硅的半导体材料，例如Si、SiGe、Si/SiGe、绝缘体上硅(SOI)、绝缘体上硅锗(SGOI)、SiC或SiGeC。
图1-10和17显示了基本方法。使用硅晶片10作为起始的半导体衬底。通常选择Si衬底使其具有(111)取向，使得纳米线生长将垂直于衬底表面。尽管通常使用(111)晶向，但是本发明也可以使用具有其它结晶取向的衬底。在衬底10上淀积绝缘膜12，例如二氧化硅(SiO2)、氮化硅(Si3N4)或氮氧化硅(SiON)。通过传统的光刻和刻蚀在绝缘膜12中形成开口14，其中一个显示在图1中。通过图11中所示的掩模来限定开口14。开口14的位置限定了将由垂直FET占用的区域。暴露的衬底10被重掺杂(大约1020cm-3的量级)以在衬底10中形成n++区域16。能够使用覆盖离子注入或气相掺杂将掺杂剂引入暴露的区域。n型掺杂剂的示例是磷(P)和砷(As)。当制造p-FET时，通过p型区域替换n型区域16。p型掺杂剂的示例是硼(B)和铟(In)。
如图2所示，覆盖淀积金属层18，例如镍(Ni)、钴(Co)、钛(Ti)、钨(W)或者当与硅反应时能够形成硅化物的其它类似金属。优选地采用Ni或Co，因为这些材料能够形成外延导电层。通常通过溅射、蒸发、化学气相淀积或类似的淀积工艺来执行金属淀积。金属层18与暴露的硅表面10反应，形成硅化物接触20。硅化物形成包括使用传统的自对准硅化(SALICIDE)工艺。通过此工艺，只在暴露的硅区域之上形成硅化物。可以根据用作层18的金属类型来改变自对准硅化工艺期间所使用的精确的退火条件。可以使用单个退火步骤，之后刻蚀任何未反应的金属。或者，能够通过第一退火、刻蚀和第二退火来形成硅化物接触20，其中第一退火的温度通常低于第二退火的温度。在形成不含硅的半导体衬底的情况下，Si层通常在金属层18淀积之前形成在开口中。或者，能够形成金属半导体合金，如果其具有低电阻(大约在50μΩ-cm或更小的量级)。例如，如果使用锗(Ge)衬底，则能够形成金属锗化物合金，例如Ni-锗化物。
再次根据使用的金属类型以及退火条件，能够形成不同相的硅化物接触。例如，在Ni的情况下，形成的金属硅化物是NiSi或NiSi2。通过在大约450℃的温度退火包含金属层18的衬底10而形成NiSi相。通过在高于750℃的温度退火衬底而形成NiSi2相。由于金属层18仅与暴露的硅反应，所以使用选择性刻蚀从非硅表面去除未反应的金属18(图3)。用于去除未反应的金属的刻蚀化学物的示例是在65℃下H2O2∶H2SO4为10∶1进行10分钟。NiSi相比NiSi2具有较低的电阻系数。但是，NiSi2相对于硅是可以外延的，因此其能够保护下部硅衬底的晶体模板。例如，参见R.T.Tung等人的“Formation of UltrathinSingle-Crystal Silicide Films on Si：Surface and InterfacialStabilization of Si-NiSi2 Epitaxial Structures”，Phys.Rev.Lett.50，P.429(1983)和R.T.Tung等人的“Growth of single crystal epitaxialsilicides on silicon by the use of template layers”，Appl.Phys.Lett.42，P.888(1983)。NiSi2相的这种特性能够在与衬底10保持相同的晶体取向的硅化物接触20之上生长硅纳米线。
参照图4，剥离绝缘体膜12并淀积由层22A和22B构成的双层膜22。这些层可以分别是SiO2和Si3N4。在两个步骤中对双层膜22构图：由图12和13所示的下面的示例，首先使用掩模2在顶部膜22B中刻蚀“T”形。刻蚀步骤停止在绝缘体膜22A上。然后使用掩模3限定层22A被刻蚀的区域。暴露的硅化物接触20表面包含在由开口14(掩模1)限定的区域内。
在暴露的硅化物接触20之上形成用于纳米线生长的催化剂点24，例如Au、Ga、Al、Ti和Ni。此处所述的催化剂点24优选的是Au点。能够通过将催化剂膜构图(图形化)为点或通过分散含有所述催化剂的胶体来形成催化剂点24。应当注意，催化剂点24的尺寸(例如宽度)限定了纳米线直径。因此，点尺寸的精确控制对于获得紧密分布的纳米线的直径是重要的。用于引入催化剂的其它方法也是可能的。例如，如果在升高的温度(例如高于350℃)退火，则薄催化剂膜将凝聚成分开的催化剂小滴。但是，催化剂凝聚方法不产生通常如催化剂悬浮法所获得的点尺寸的窄分布。而且，能够利用自组装工艺形成催化剂点。此处使用术语“自组装”来表示材料的自发组织成规则图形。自组装工艺利用嵌段共聚物并且这些技术是本领域公知的。
参照图4和5，垂直于衬底10表面生长纳米线26。通过催化剂点24来帮助纳米线26的生长，并且通常由化学气相淀积(CVD)或等离子体增强化学气相淀积(PECVD)来进行生长。生长温度取决于使用的前体。例如，对于硅烷(SiH4)，典型的生长温度是从大约370℃到大约500℃。对于四氯化硅(SiCl4)，生长温度是从大约800℃到大约950℃。通过将氯添加到SiH4，生长温度能够升高到600℃以上。纳米线26的生长速率取决于生长温度和生长室内的气压。例如，对于通过H2(1∶1)稀释的SiH4，在1托(torr)压力和450℃的生长温度下，典型的CVD生长速率大约是7.6μm/小时。通过汽-液-固(VLS)机制所述，据信各向异性生长的纳米线26是最好的，例如在E.I.Givargizov的“Highly Anistropic Crystals”Kluwer academicpublishers，Norwell MA，1986中进行了说明。当开始生长时，形成催化剂-硅液体合金28。通过从气相(例如SiH4)额外提供的Si，液体小滴变成了Si过饱和，多出的硅淀积在固-液界面。结果，液体小滴28从最初的衬底表面上升到生长纳米线晶体的端部。如果生长温度保持在大约500℃以下(如果使用SiH4)，或者使用氯添加剂，则在其它表面上不会出现硅的淀积。注意，能够由与半导体衬底相同或不同的材料构成纳米线26。在一个实施例中，优选地是由与半导体衬底不同的材料构成纳米线26。在本发明另一实施例中，纳米线是基本上具有相同晶向的单晶Si纳米线。
在此处所述的具体示例中，其中Si纳米线形成在(111)取向的Si衬底上，因为其源自于也具有(111)取向的衬底10，所以硅纳米线取向是(111)。这是使用模仿衬底的方向的硅化物膜20的原因。纳米线26通常生长到超过膜22A和22B总厚度的长度。注意，纳米线26垂直于衬底10的表面生长。
参照图6，共形的栅极电介质30覆盖淀积在衬底上。栅极电介质的一些示例包括但不限于：SiO2、Al2O3和HfO2。例如，通过诸如CVD或原子层淀积(ALD)的技术来执行栅极电介质30的淀积。注意，由于一旦完成了纳米线26的生长则不需要催化剂24，所以能够在栅极电介质30淀积之前通过选择性刻蚀来去除催化剂24。另一方面，保持催化剂24能够提供额外的刻蚀选择性，因此在栅极导体凹陷刻蚀期间保护纳米线26，如稍后所述。
参照图7，共形栅极导体32淀积在栅极电介质30上。栅极导体32填充纳米线26之间的空间。栅极导体32能够是掺杂的多晶硅或者导电金属，例如钨(W)、铝(Al)、铜(Cu)或钽(Ta)。此处也考虑到导电金属的合金以及所述导电金属的硅化物或氮化物。然后通过针对栅极电介质30的选择性刻蚀使栅极导体32凹陷，以提供例如图8所示的结构。如图所示，本发明的此步骤使得凹陷的栅极导体32的顶部在绝缘体层22的表面线之下。在该结构上覆盖淀积其它的绝缘体34，例如低温氧化物(LTO)。然后通过CMP来平坦化该结构，以提供图9所示的结构。使用绝缘体层22B作为CMP阻挡层。CMP步骤将纳米线26修整为全部相同的长度。还形成绝缘体插塞(插块)34，从顶部表面缓冲凹陷的栅极导体32。这使得接触纳米线26的暴露端部而不会与栅极32短路。使用SALICIDE工艺，使每个纳米线26的尖端硅化形成为硅化物的端部38。
图10(通过图16中所示的A-A’，是从上到下的视图)和17(通过图16中所示的B-B’)显示了在形成到源极、漏极和栅极的接触之后两个主剖面中的器件。为了接触源极，形成到硅化物表面20的通路孔40。类似地形成到栅极导体32的通路孔42。分别由图14的掩模5和4限定栅极和源极的通路孔。最后，由掩模6(图15)限定漏极接触44、源极接触46和栅极接触48。
图18至31显示了用于制造具有纳米线沟道的垂直FET的另一种方法。该方法类似于图1至17中所述的方法，具有以下的改变：(i)在生长步骤之后立即去除催化剂。(ii)有三个CMP步骤：第一步骤修整纳米线使其全部具有相同的长度。第二CMP步骤用于去除多出的栅极导体材料，第三CMP步骤用于在栅极导体之上形成LTO插塞。(iii)在淀积栅极材料之前硅化纳米线的暴露的顶部。
考虑到工艺变化，引入这些改变以允许更强的工艺。例如，在凹陷步骤(图7-8)之前的栅极导体的平坦化通常将产生更好的对凹陷深度的控制。在纳米线的顶部形成硅化物为CMP工艺和用于使栅极导体凹陷的刻蚀过程提供了更好的选择性。
图18至22显示的处理步骤与先前关于图1至5所述的步骤相同。参照图22至23，通过刻蚀选择地去除催化剂硅液体合金28，并在该结构上淀积共形的栅极电介质30。在该结构(见图24)上淀积填充材料50(有机的或无机的)，例如光刻胶、聚酰亚胺或低温氧化物(LTO)。选择填充材料50，使其能够相对于栅极电介质30被选择性去除。通过CMP平坦化该晶片，层22B是用于CMP的硬阻挡层。结果将所有的纳米线26修整为与双层22总厚度相同的单个长度(图25)。
选择性地刻蚀出填充材料，并对该晶片施加SALICIDE步骤。结果将每个纳米线尖端上的暴露的硅表面转化成硅化物38(图26)。例如，硅化物38可以是NiSi或NiSi2或CoSi2。
参照图27，覆盖淀积栅极导体32，并施加CMP来去除膜22表面上方的任何多出的栅极材料。在纳米线26的顶部表面相对于硅化物38选择性地使栅极材料32凹陷(图28)。覆盖淀积例如LTO的绝缘体34，并施加CMP来去除膜22表面上方的LTO。结果在凹陷的栅极导体32上形成LTO插塞34(图29)。LTO插塞34避免了形成到纳米线顶部的接触与栅极短路。
图30和31在两个主剖面A-A’和B-B’中显示了最终的结构。为了完成该制造，形成栅极通孔42和源极通孔40并通过栅极接触金属和源极接触金属进行填充。最后，形成漏极接触44、源极接触46和栅极接触48。如图所示，漏极接触金属44在纳米线26的顶端接触到硅化物38。
图32至37显示了用于制造具有减小了栅极-源极交叠电容的纳米线沟道的垂直FET的另一种方法。除了在纳米线26的底端具有绝缘体插塞70(类似于顶部LTO插塞34)以外，该最终结构类似于前两个实施例中所述的结构。注意，绝缘体插塞70由例如SiO2的电介质构成。通过进一步相对栅极导体32偏置所述连接到源极的底部导电硅化物20层，绝缘体插塞有助于降低栅极与源极之间的交叠电容。
图32至34所示的处理步骤与图1至3所述的步骤相同。参照图35，通过由绝缘体22A构成的绝缘膜70围绕催化剂24。催化剂24也与硅化物层20接触。要求催化剂24与层20接触使得纳米线取向模仿衬底10的取向。有几种方法用于制造由绝缘体层22A围绕的催化剂24。在第一种方法中，在膜22A中形成具有预期催化剂的尺寸的开口。这能够通过在绝缘体膜22A之上形成自组装掩模(例如双嵌段共聚物)来实现。双嵌段共聚物的一个示例是聚苯乙烯和聚(甲基丙烯酸甲酯)的共聚物。在通过RIE刻蚀的双嵌段共聚物掩模的小孔中限定膜22A中的开口。稍后通过电镀将金或其它类似的纳米线催化剂材料引入到开口中。催化剂24将不镀在绝缘体膜表面22A之上，因此催化剂24仅添加到膜22A的开口中。
在第二种方法中，在包括开口的膜22A上覆盖淀积催化剂膜。由于催化剂淀积容易冲刷形貌，所以开口中的催化剂厚度通常比膜22A顶部表面上的厚度要厚。然后全面刻蚀催化剂，直到从膜22A的顶部表面上去除所有的催化剂为止。由于开口中的催化剂膜较厚，所以每个开口的底部将保留一层未刻蚀的催化剂。
在第三种方法中，去除图34中所示的电介质膜12，并淀积覆盖膜70。在膜70中形成开口，并在层70上淀积覆盖的催化剂膜。通过CMP步骤来“刮削”膜70顶部表面上的催化剂，但是没有去除填充开口的催化剂。然后淀积并图形化膜22B，以获得图35所示的结构。
在第四种方法中，首先淀积膜22B并使用掩模2(图12)来图形化膜22B以便露出层20。在该结构之上执行膜70的共形淀积，因此膜70也覆盖层20以及膜22B的侧壁。选择膜70使其对于催化剂具有高的表面迁移率。然后在膜70中形成开口(小孔)。每个小孔的尺寸都使其能够容纳不止一个催化剂颗粒。通过含有催化剂颗粒的胶体来淹没晶片的表面。能够使用各种技术用于将催化剂颗粒拖入小孔。在一种具体技术中，催化剂是带负电的，胶体由水溶液构成，膜70被选为SiO2。催化剂颗粒被自然地从带负电的SiO2表面排斥。为了激励通过催化剂颗粒占据小孔的过程，能够向衬底施加正脉冲。然后能够使用本领域公知的技术从衬底表面清洗没有陷在小孔中的多出的催化剂颗粒。
产生图36和37在两个主剖面A-A’和B-B’中所示的最终结构的工艺步骤与先前所述的两个实施例的步骤保持相同。结果将催化剂24嵌入到形成在层70中的开口内，该结构与围绕纳米线26的顶部和底部部分的电介质插塞更加对称。这些插塞34和70能够被视为旋转了90度的传统的平面化FET的栅极间隔物。
具体地，图36和37显示了包括底部外延导电层(例如，硅化物接触20)以及位于该底部外延导电层(例如，硅化物接触20)上的多个半导体纳米线沟道26的FET。按照本发明，每个半导体纳米线沟道26垂直于底部外延导电层。FET还包括顶部接触，即，漏极接触44，其位于多个半导体纳米线沟道26上方，其中顶部接触(即，漏极接触44)垂直于半导体纳米线。FET还包括围绕每个纳米线26的栅极电介质30以及围绕栅极导体30的栅极导体32。按照本发明，栅极导体30通过底部绝缘70与底部外延导电层(即，硅化物接触20)隔开，栅极导体32通过绝缘体插塞34与顶部接触44隔开。
在每个纳米线的端部形成源极和漏极(没有具体标示)。硅化物的掺杂能够将掺杂剂(通过扩散)引入到纳米线端部。此外，通过对绝缘体70和34使用掺杂的氧化物(例如硼硅(酸盐)玻璃或磷硅(酸盐)玻璃)，能够通过固体源扩散来掺杂纳米线的端部(例如，见J.M.Hergenrother等人的同上所述的论文)。如J.M.Hergenrother等人的论文所述，将需要在两个薄氮化硅层之间插入绝缘体70和插塞34，以防止掺杂剂扩散进入栅极材料。也能够在形成硅化物之前(例如图9的时刻)分开地从气相掺杂纳米线的顶端。此外，源极和漏极可以有意地被形成不对称的(例如与源极相比漏极具有较低的掺杂)。由于降低的栅极-漏极电容，所以这可以产生更快的器件。
应当注意，由于纳米线的直径非常小，所以在硅技术中实践的传统的掺杂技术可能不是用于在纳米线中形成源极和漏极的最好的方式。通过适当的处理在半导体中诱导载流子也能够在Si纳米线的端部提供载流子富含区域(类似于可能通过掺杂而获得的)。
图38和39显示了本发明的另一各实施例，其中纳米线26生长在重掺杂的外延半导体层90上。使用本领域已知的技术在外延硅化物层20上淀积层90。可以在S.C.Wu等人的“Epitaxy of silicon on nickelsilicide”，Phys.Rev.B 32，p.6956(1985)中发现在镍的硅化物上硅外延的示例。还能够在区域16之上外延生长硅化物膜20(例如NiSi2)，而并非通过与金属反应来形成，如先前参照SALICIDE方法所述。能够通过重掺杂的硅半导体膜90的外延来继续硅化物膜20的外延。通过一步外延形成膜20和90，在两个膜之间产生清洁的界面。产生图38和39所示的最终结构的工艺步骤与在膜90(图4或21)之上淀积催化剂24或者在淀积在膜90之上的膜70中形成小孔的步骤保持相同。
考虑到先前提及的关于超薄纳米线的掺杂的问题，引入层90的另一个优点是，其能够提供在纳米线本体外部的源极区域。不再需要这种方式掺杂的纳米线的端部。也能够通过在纳米线26的顶部与漏极接触44之间引入重掺杂的半导体层来增加外部漏极区域。
尽管已经关于本发明的优选实施例具体显示和说明了本发明，但是本领域技术人员应当理解，在不脱离本发明的实质与范围的情况下，可以进行形式和细节上的前述和其它的改变。因此本发明不限于所述和示例的确切的形式和细节，而是落于后附权利要求的范围内。

Claims (20)

1.一种半导体结构，包括：
位于半导体衬底的一部分上或之内的硅化物接触层；
位于所述硅化物接触层上的多个纳米线；
围绕所述多个纳米线的栅极电介质；
位于所述栅极电介质上的栅极导体；和
位于所述纳米线的每个端部的源极和漏极。
2.如权利要求1所述的半导体结构，其中所述多个纳米线垂直于所述半导体衬底。
3.如权利要求1所述的半导体结构，进一步包括顶部漏极接触和使所述栅极导体与所述顶部漏极接触分开的LTO插塞。
4.如权利要求1所述的半导体结构，其中所述多个纳米线包括至少一种与所述衬底不同的材料。
5.如权利要求1所述的半导体结构，其中所述硅化物接触层是外延的，并且所述硅化物接触层的晶向与所述衬底的晶向相同。
6.如权利要求1所述的半导体结构，进一步包括在所述硅化物接触之下的位于所述半导体衬底内的掺杂剂区域。
7.如权利要求1所述的半导体结构，进一步包括位于所述栅极导体上方和之下的LTO插塞。
8.如权利要求1所述的半导体结构，其中所述纳米线是具有相同的晶向的单晶硅纳米线。
9.如权利要求1所述的半导体结构，其中所述硅化物接触层包括选自于由Ni、Co、Ti和W所组成的组的至少一种金属。
10.如权利要求1所述的半导体结构，其中每个纳米线包括含有硅化物的尖端。
11.如权利要求1所述的半导体结构，进一步包括形成在所述纳米线与所述硅化物接触层之间的重掺杂的外延半导体层。
12.一种场效应晶体管，包括：
底部外延导电层；
位于所述底部外延导电层上的多个半导体纳米线沟道，其中所述多个半导体纳米线沟道垂直于所述底部外延导电层；
位于所述纳米线沟道上的顶部接触层，其中接触层垂直于所述多个半导体纳米线沟道；
围绕每个所述半导体纳米线沟道的栅极电介质；
围绕所述栅极电介质的栅极导体，其中所述栅极导体通过底部绝缘层与底部外延导电层分开，并且所述栅极导体通过绝缘体插塞与顶部接触层分开；和
位于所述多个半导体纳米线沟道的每个端部的源极和漏极。
13.如权利要求12所述的场效应晶体管，其中纳米线沟道之间的间隔与各个纳米线沟道的直径相同。
14.一种形成半导体结构的方法，包括：
在半导体衬底的指定区域上或之内形成硅化物接触层；
从形成在所述硅化物接触层之上的多个催化剂点形成纳米线；
在所述纳米线上淀积栅极电介质和栅极导体；
平坦化所述纳米线以便将所述纳米线修整为相同的长度；
使栅极导体凹陷并在所述凹陷的栅极导体之上形成绝缘体插塞；以及
形成到每个所述纳米线的上表面的接触、到所述硅化物接触层的接触和到所述栅极导体的接触。
15.如权利要求14所述的方法，进一步包括：在所述硅化物接触层之上形成绝缘层；在所述绝缘层中刻蚀开口；以及在所述开口中形成所述催化剂点。
16.如权利要求14所述的方法，进一步包括通过自对准硅化工艺使每个所述纳米线的尖端硅化。
17.如权利要求14所述的方法，其中通过自组装方法形成所述催化剂。
18.如权利要求14所述的方法，其中通过催化剂驱动外延形成所述纳米线。
19.如权利要求14所述的方法，其中垂直于所述半导体衬底来形成所述纳米线。
20.一种形成半导体结构的方法，包括：
在半导体衬底的指定区域上或之内形成硅化物接触层；
从形成在所述硅化物接触层之上的多个催化剂点形成纳米线；
在所述纳米线之上淀积栅极电介质和填充材料；
平坦化所述纳米线以便将所述纳米线修整为相同的长度；
去除填充材料并在先前包括填充材料的空间中形成凹陷的栅极导体；
在所述凹陷的栅极导体之上形成绝缘体插塞；以及
形成到每个所述纳米线的上表面的接触、到所述硅化物接触层的接触和到所述栅极导体的接触。
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