CN100449784C - Semiconductor device and its making method - Google Patents
Semiconductor device and its making method Download PDFInfo
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- CN100449784C CN100449784C CNB2006100300158A CN200610030015A CN100449784C CN 100449784 C CN100449784 C CN 100449784C CN B2006100300158 A CNB2006100300158 A CN B2006100300158A CN 200610030015 A CN200610030015 A CN 200610030015A CN 100449784 C CN100449784 C CN 100449784C
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- cobalt
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 100
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 42
- 239000010941 cobalt Substances 0.000 claims abstract description 42
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 71
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052759 nickel Inorganic materials 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- ZGDWHDKHJKZZIQ-UHFFFAOYSA-N cobalt nickel Chemical compound [Co].[Ni].[Ni].[Ni] ZGDWHDKHJKZZIQ-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 abstract description 15
- 230000008901 benefit Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 235000013495 cobalt Nutrition 0.000 description 39
- 238000005516 engineering process Methods 0.000 description 24
- 230000008569 process Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000004873 anchoring Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
The invention discloses a metal oxide semi-conductor device, which comprises a semi-conductor underlayer, a grid structure formed on the surface of the underlayer, and the two sides of which have side wall isolators, a source electrode area and a drain electrode area positioned on the two sides of the side wall isolators on the underlayer, a first metal silicide positioned on the source electrode area and the drain electrode area, and a second silicide positioned on the grid structure. The manufacturing method of semi-conductor devices of the invention forms respectively the first metal silicide containing the first and the second metal, and forms the second silicide containing the second metal. The invention combines the advantages of both the cobalt silicide techniques and the nickel silicide techniques, and applies well the nickel silicide techniques to the following technique nodes below 65nm. The invention reduces the risk of forming spriking in the source/drain area, when assuring the formation of metal contact layer of high reliability on the surface of the grid by using nickel silicide.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the metal contact layer and the manufacture method thereof of particularly a kind of mos field effect transistor (MOS).
Background technology
In ultrahigh speed MOS large scale integrated circuit,, adopted self-aligned silicide (salicide) technology for the film resistor and the dead resistance of reduction source/drain electrode and grid.In self-aligned technology, on source, the drain region of the MOSFET that constitutes by the impurity diffusion layer that is formed on the Semiconductor substrate and the grid that constitutes by polysilicon, form metal and semiconductor for example the reaction product of silicon (Si) be silicide (calling metal silicide in the following text).Metal silicide plays important effect in the VLS/ULSI device technology.In the MOS device, often adopt metal silicide to obtain good low resistance contact.Metal silicide can be used to provide the contact-making surface between metal wire and substrate contact region territory, for example source electrode and the drain electrode on polysilicon gate, the silicon substrate.Fig. 1 is the position view of metal silicide layer in transistor.As shown in Figure 1, metal silicide layer 151,152,153 is set respectively on source area 110, drain region 120 and grid 130.Metal silicide can reduce the sheet resistance between Metal Contact and the following square structure, reduces the contact hole of upper layer interconnects structure and the contact resistance of each utmost point of transistor.
To 90 nm technology node, the CMOS technology mainly adopts cobalt silicide (CoSi) as contact layer from 0.13 micron technology node.After advancing before the technology node, it is more and more littler that size of devices becomes, and high silicon consumption becomes a big problem of cobalt at this moment tying, because high silicon consumption has reduced useful active area.Another uses the problem of cobalt is that the thermal annealing temperature is higher, and its 700～800 ℃ of annealing temperatures and live width effect are unacceptable for advanced person's 65 nanometer MOS technology.
After 90 nanometer technology nodes, begin to replace cobalt to form the metal silicide (NiSi) of nickel as contact layer with nickel (Ni).Particularly,, have lower silicon consumption and lower heat budget (thermal budget) and lower contact resistance, so the following process node of 65 nanometers replaces cobalt with nickel because nickel does not have the live width effect at 65nm and following.But NiSi does not have CoSi stable when high temperature, can form the Ni of high resistant when temperature is higher
2Si, so the annealing temperature of nickel must be controlled between 350～450 ℃.NiSi is the low-resistance phase that people need, but NiSi is a phase in the middle of.Metal silicide among Fig. 2 is example with nickel, and as shown in Figure 2, when temperature was higher than 450 ℃, the NiSi of low-resistance can change the Ni of high resistant into
2The Si phase.And the diffusion coefficient of nickel in silicon is bigger, and when silicification reaction, combination reaction spreads in silicon carries out.Especially the process node below 65nm, unsettled NiSi changes the Ni of high-impedance state into
2Behind the Si, Ni
2Si can be by the diffusion downwards of surface, narrow source/drain region, thereby in the source region 110 of substrate, drain region 120, forms the Ni by high-impedance state below the nickel silicide layer 151 and 152 on surface
2Anchoring (spriking) zone 160 and 161 that Si forms causes contact resistance to increase.
A kind of method that forms metal silicide layer on grid and source, drain region surface is disclosed in No. the 6180469th, United States Patent (USP).This method is utilized on grid and source, drain region surface after chemical plating optionally forms the Ni layer, nitrogen is carried out ion to be injected in this Ni layer, formation is divided into barrier layer up and down with the Ni layer, only makes the Ni layer of lower floor form silicide by heat treatment, to reduce contact resistance.But it is bigger beyond doubt that this ion injects the technique controlling difficulty of dividing layer-selective to form silicide, the risk that still exists the silicide of nickel to be changed to high-impedance state by low resistance state in heat treatment process.Therefore, NiSi is integrated into one of huge challenge of being still 65 advanced nano-technology techniques in the whole process flow.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device and manufacture method thereof, can be in conjunction with cobalt silicide technology and nickel silicide technology advantage separately, when guaranteeing that gate surface utilizes nickel silicide to form highly reliable metal contact layer, farthest be reduced in the risk that source/drain region forms anchoring (spriking).
For achieving the above object, a kind of metal oxide semiconductor device provided by the invention comprises:
Semiconductor substrate; At the grid structure that described substrate surface forms, described grid structure two examples have sidewall spacers; And lay respectively at source area and drain region in the substrate of described sidewall spacers both sides; It is characterized in that also comprising:
First metal silicide is positioned on described source area and the drain region; With
Second metal silicide is positioned on the described grid structure.
Described first metal silicide is the alloying metal silicide.
Described first metal silicide comprises first metal and second metal; Described second metal silicide comprises second metal.
Described first metal is a cobalt, and described second metal is a nickel.
Described first metal silicide is the mixture of nickle silicide and cobalt silicide; Described second metal silicide is a nickle silicide.
Described first metal silicide is the alloy silicide of nickel and cobalt.
Described grid structure comprises a gate dielectric layer and a gate electrode.
Comprise light doping section in the substrate of described sidewall spacers below.
Correspondingly, the manufacture method of metal oxide semiconductor device of the present invention comprises:
Form grid, source area and drain region on Semiconductor substrate, described grid both sides have sidewall spacers;
Form deposited barrier layer in described gate surface;
At described source area and drain region deposit first metal;
On described source area and drain region, form the metal silicide layer that comprises first metal;
Remove described deposited barrier layer;
At described grid, source area and drain region surface deposition second metal;
On described source area and drain region, form first metal silicide that comprises first and second metals;
Remaining second metal of described source area of selective etch and surface, drain region;
On described grid, form second metal silicide that comprises second metal.
Described first metal is a cobalt, and described second metal is a nickel.
The material of described deposited barrier layer is silicon nitride, silicon oxynitride, carborundum or its combination.
Described first metal silicide is the alloying metal silicide.
Described first metal silicide is the mixture of nickle silicide and cobalt silicide.
Described first metal silicide is the alloy silicide of nickel and cobalt.
Described second metal silicide is a nickle silicide.
The manufacture method of another kind of metal oxide semiconductor device of the present invention comprises:
Form grid, source area and drain region on Semiconductor substrate, described grid both sides have sidewall spacers;
Form deposited barrier layer in described gate surface;
At described source area and drain region depositing metal cobalt;
Carry out first thermal anneal step;
Remove described deposited barrier layer;
At described grid, source area and drain region surface deposition metallic nickel;
Carry out second thermal anneal step;
The remaining nickel of described source area of selective etch and surface, drain region;
Carry out the 3rd thermal anneal step.
The temperature of described first thermal annealing is 400-550 ℃.
The temperature of described second thermal annealing is 250-350 ℃.
The temperature of described the 3rd thermal annealing is 350-450 ℃.
Described thermal annealing is a rapid thermal annealing.
Compared with prior art, the present invention has the following advantages:
At 90nm and 65nm process node, nickel silicide is widely used as metal contact layer.At 0.13um and 90nm process node, cobalt silicide still is used as contact layer with the advantage of the simple low cost of manufacture of its technology.Method, semi-conductor device manufacturing method of the present invention cobalt silicide technology and nickel silicide technology are put in order and, overcome the deficiency of nickel silicide technology, nickel silicide technology has been applied in 65nm and following technology node well.Method of the present invention in the source/surface, drain region at first forms cobalt silicide as at metal contact layer, the silicification technics of cobalt is very ripe; And then, form nickel silicide, as metal contact layer in area of grid surface and source/drain region surface deposition nickel.Nisiloy metallization processes heat budget is low, and the nickel silicide of formation does not have the live width effect and has lower contact resistance.Like this, advantage in conjunction with two kinds of technologies, form nickel silicide in gate regions, in the source/drain region formation cobalt nickel silicide, the live width effect of promptly having avoided adopting on area of grid surface high silicon loss that cobalt silicide brought and heat budget and may having brought has been avoided again in the source/high-impedance state Ni that the drain region is easy to generate when forming nickel silicide
2Si anchoring (spriking) phenomenon.Method of the present invention can wholely reduce the technological temperature that forms metal contact layer at the 65nm process node, has reduced heat budget, can form electrical good metal silicide contacts layer in source/drain region and gate regions surface.In addition, cobalt is very limited in the silicon loss of narrow source/drain region at a lower temperature, can not impact device performance.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 is the position view of metal silicide layer in transistor;
Fig. 2 is the schematic diagram of anchoring in the prior art (spriking) phenomenon;
Fig. 3 is the semiconductor device structure schematic diagram according to the embodiment of the invention;
Fig. 4 is the flow chart according to the method, semi-conductor device manufacturing method of the embodiment of the invention;
Fig. 5 to Fig. 9 is the profile of explanation method, semi-conductor device manufacturing method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Semiconductor device provided by the invention and manufacture method thereof are specially adapted to characteristic size in 65nm and following semiconductor device and manufacturing thereof.Described semiconductor device is not only MOS transistor, can also be PMOS transistor and nmos pass transistor among the CMOS (complementary mos device).
Fig. 3 is the semiconductor device structure schematic diagram according to the embodiment of the invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.As shown in Figure 3, semiconductor device of the present invention comprises Semiconductor substrate 200; At the grid structure that described substrate surface forms, grid structure is included in and forms dielectric layer 240 and polysilicon gate 250 on the Semiconductor substrate 200.Substrate 200 can comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form substrate 200, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.
Above-mentioned dielectric layer 240 can be silica (SiO2) or silicon oxynitride (SiNO).At the following process node of 65nm, the characteristic size of grid is very little, and dielectric layer 240 is as gate dielectric layer, and its material is preferably high-k (high K) material.Can be used as the material that forms high-K gate dielectric layer and comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming dielectric layer 240, this layer can be formed by other material that reduces grid leakage current.
Has sidewall spacers (spacers) 231 in the both sides of described grid structure.Sidewall spacers 231 utilizes etching technics to form, and its material can be silica, silicon nitride, silicon oxynitride, carborundum or their mixture.Lay respectively at source area 210 and drain region 220 in the described sidewall spacers 231 both sides substrates; Has light doping section 230 with source area 210 and drain region 220 adjacent areas in the substrate 200 below described sidewall spacers 231.The doping content of light doping section 230 is less than the doping content of source area 210 and drain region 220, the short channel effect of light doping section 230 conducting channel below can suppressor grid under the short gate length.
Semiconductor device of the present invention has first metal silicide 260 on source area 210 and drain region 220, have second metal silicide 270 at the top of grid 250.First metal silicide 260 is different with second metal silicide 270, and first metal silicide 260 is for comprising the metal silicide of cobalt and nickel, and this silicide comprises cobalt silicide and nickle silicide, and cobalt silicide forms below nickle silicide and prior to nickle silicide.The alloy silicide that also includes cobalt and nickel in the above-mentioned metal silicide 260.Metal silicide 270 at top portions of gates is a nickle silicide.Metal silicide 260 and 270 provides electrical good metal silicide contacts layer in source/drain region and gate regions surface.
Above-mentioned semiconductor device only is an example, and it also can be applied in other example, for example nmos device and PMOS device.NMOS and PMOS can be source electrode and drain electrode structure, bigrid (double gate) structure, many finger-like (multi-finger) structure or the fin field effect pipes (FinFET) with projection (raised).NMOS and PMOS can utilize P trap (well), N trap or two trap (double-well) structure to make, also can be formed directly on the above-mentioned Semiconductor substrate or within.Also should have area of isolation between NMOS and the PMOS.Area of isolation can use isolation technology to form, and for example shallow trench isolation is from (STI) technology.
Fig. 4 is the flow chart according to the method, semi-conductor device manufacturing method of the embodiment of the invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.As shown in Figure 4, method, semi-conductor device manufacturing method of the present invention is included in and forms grid, source area and drain region (S101) on the Semiconductor substrate, described grid forms by for example CVD method deposit spathic silicons such as (chemical vapor depositions) and etch polysilicon, be doped with suitable foreign particle in source area and the drain region, form source electrode and drain electrode; Form deposited barrier layer (S102) in described gate surface, described deposited barrier layer can utilize the part hard mask layer to serve as, can be after forming sidewall spacer that also the gate surface deposition forms, deposited barrier layer can be silicon nitride, silicon oxynitride or its combination; At described source area and drain region depositing metal cobalt (S103), described deposition process preferably adopts physical sputtering method (sputter); Carry out first thermal anneal step then, be preferably rapid thermal annealing (RTP), temperature just forms cobalt silicide (S104) on described source area and drain region between 400-550 ℃; Remove described deposited barrier layer (S105), the method that removes preferably adopts wet etching; At described grid, source area and drain region surface deposition metallic nickel (S106), deposition process also preferentially adopts the physical sputtering method subsequently; And carry out second thermal anneal step, and being preferably rapid thermal annealing, temperature is between 250-350 ℃, and just high-impedance state nickle silicide (NiSi is formed on (top) on described grid
2) (S107), formed nickle silicide at the also existing part metals nickel of source area and drain region this moment; Described source area of selective etch and drain region surface remaining nickel (S108), the i.e. nickel of silication not then; And carry out the 3rd thermal anneal step, and being preferably rapid thermal annealing, temperature is 350-450 ℃, just form the nickle silicide (NiSi) of low resistance state this moment on described grid, formed the alloy silicide (S109) that comprises cobalt and nickel on described source area and drain region.
Fig. 5 to Fig. 9 is the profile of explanation method, semi-conductor device manufacturing method of the present invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.As shown in Figure 5, and in conjunction with Fig. 4, on Semiconductor substrate 200, form one deck liner (liner) oxide layer as gate dielectric layer 240.The growing method of dielectric layer 240 can be any conventional vacuum coating technology, such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, be preferably atom layer deposition process.In such technology, can form smooth atom interface between substrate 200 and the dielectric layer 240, can form the gate dielectric layer of ideal thickness.In the inventive method, the live width of grid is below 65nm, and dielectric layer 240 preferred thickness exist
Between.It should be noted that in different situations dielectric layer 110 can adopt different materials and different thickness.Afterwards, on dielectric layer 240, utilize method deposit spathic silicon layers such as CVD, form hard mask at polysilicon surface then, define the position of grid by photoetching process, and be mask with hard mask, utilize reactive ion etching (RIE) or plasma etching method to etch grid 250.Subsequently at substrate surface deposit silicon nitride or silicon oxynitride and etching formation sidewall spacer 231.Before forming sidewall spacer 231, need elder generation in the substrate of grid both sides, to utilize ion to inject and form light doping section 230, after forming sidewall spacer 231, inject heavily doped source area 210 of formation and drain region 220 then by ion.Method of the present invention will form one deck deposited barrier layer 271 at grid 250 tops, the material of deposited barrier layer 271 is silicon nitride, silicon oxynitride or its combination.Can when removing the hard mask on above-mentioned grid 250 surfaces, keep a part of hard mask layer as deposited barrier layer 271; Also can be after forming sidewall spacer 231 again in grid 250 surface deposition one deck silicon nitrides or silicon oxynitride as deposited barrier layer 271.
As shown in Figure 6, and in conjunction with Fig. 4, utilize the physical sputtering method, at source area 210 and drain region 220 surface deposition metallic cobalts (Co), those skilled in the art can be according to the deposit of the thickness of routine and time control cobalt.Because grid 250 surfaces have deposited barrier layer 271, so grid 250 surfaces do not have the metallic cobalt deposition.Carry out the thermal annealing first time subsequently, preferred rapid thermal anneal process is to form the silicide 261 of cobalt on source area 210 and drain region 220.The temperature of the once annealing of typical cobalt is between 400～450 ℃.Cobalt forms the nucleation of CoSi phase of low-resistance mutually by the CoSi2 of high resistant in this temperature range very fast, and source/drain region the live width effect can not occur in phase transition process, and cobalt is also very little to the loss of source/drain region silicon, can not exert an influence to device performance.Next remove remaining cobalt and to processing such as substrate surface clean.
As shown in Figure 7, and in conjunction with Fig. 4, the silicide 261 of cobalt, just cobalt silicide on source area 210 and drain region 220, have been formed this moment.In ensuing processing step, remove the deposited barrier layer 271 on grid 250 surfaces, can utilize wet etching, for example use phosphoric acid to remove above-mentioned deposited barrier layer 271.
Then, as shown in Figure 8, and in conjunction with Fig. 4, at described grid 250, source area 210 and drain region 220 surface deposition metallic nickels (Ni).The method of deposit preferably adopts for example sputtering method of physical vapor deposition (PVD).Top portions of gates metals deposited nickel 272 directly contacts with polycrystalline silicon material, and the metallic nickel 262 of source area 210 and drain region 220 surface depositions is to cover on the cobalt silicide 261 of previous formation.Then, carry out the thermal annealing second time, be preferably rapid thermal annealing, annealing temperature is between 250-350 ℃.In annealing process, the nickel 272 on grid 250 surfaces forms the silicide nickle silicide of nickel to grid 250 diffusion inside and with silicon in the polysilicon gate 250 gradually, but the nickle silicide of this moment is the NiSi of high resistant
2Phase.Also in thermal annealing process, silicon cobalt substrate 261 internal penetrations to source area 210 and 220 surfaces, drain region form nickle silicide with remaining pasc reaction in the silicon cobalt substrate 261 at the metallic nickel 262 of source area 210 and drain region 220 surface depositions.Make promptly to comprise cobalt silicide and also comprise nickle silicide in this layer, also may comprise the metal silicide of cobalt-nickel alloy attitude.
Next as shown in Figure 9, and, optionally etch away source area 210 and drain region 220 surperficial remaining unreacted metal nickel, and carry out surface clean in conjunction with Fig. 4.Afterwards, carry out the 3rd thermal anneal step, be preferably rapid thermal annealing, temperature is 350-450 ℃.In this annealing process, the NiSi of the high resistant at grid 250 tops
2The nickle silicide of phase undergoes phase transition through further thermal annealing, forms the NiSi phase nickel silicide layer 270 of low resistance state on grid 250 tops.The further silication of nickel in source area 210 and drain region 220 upper metal silicide layers, the nickle silicide and the cobalt silicide that form further react, thereby form the metal silicide layer 260 that comprises nickle silicide, cobalt silicide and cobalt-nickel alloy attitude at source area 210 and 220 tops, drain region.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1, a kind of metal oxide semiconductor device comprises:
Semiconductor substrate;
At the grid structure that described substrate surface forms, described grid structure both sides have sidewall spacers; And
Lay respectively at source area and drain region in the substrate of described sidewall spacers both sides; It is characterized in that also comprising:
The cobalt nickel silicide layer is positioned on described source area and the drain region; With
By the silicide layer that nickle silicide constitutes, be positioned on the described grid structure.
2, semiconductor device as claimed in claim 1 is characterized in that: described grid structure comprises a gate dielectric layer and a gate electrode.
3, semiconductor device as claimed in claim 1 is characterized in that: comprise light doping section in the substrate of described sidewall spacers below.
4, a kind of manufacture method of metal oxide semiconductor device comprises:
Form grid, source area and drain region on Semiconductor substrate, described grid both sides have sidewall spacers;
Form deposited barrier layer in described gate surface;
At described source area and drain region depositing metal cobalt;
On described source area and drain region, form cobalt silicide;
Remove described deposited barrier layer;
At described grid, source area and drain region surface deposition metallic nickel;
On described source area and drain region, form the cobalt nickel silicide;
The remaining metallic nickel of described source area of selective etch and surface, drain region;
On described grid, form the silicide that constitutes by nickle silicide.
5, method as claimed in claim 9 is characterized in that: the material of described deposited barrier layer is silicon nitride, silicon oxynitride, carborundum or its combination.
6, a kind of manufacture method of metal oxide semiconductor device comprises:
Form grid, source area and drain region on Semiconductor substrate, described grid both sides have sidewall spacers;
Form deposited barrier layer in described gate surface;
At described source area and drain region depositing metal cobalt;
Carry out first thermal anneal step;
Remove described deposited barrier layer;
At described grid, source area and drain region surface deposition metallic nickel;
Carry out second thermal anneal step, form the cobalt nickel silicide at described source area and drain region;
The remaining nickel of described source area of selective etch and surface, drain region;
Carry out the 3rd thermal anneal step, on described grid, form the silicide that constitutes by nickle silicide.
7, method as claimed in claim 6 is characterized in that: the temperature of described first thermal annealing is 400-550 ℃.
8, method as claimed in claim 6 is characterized in that: the temperature of described second thermal annealing is 250-350 ℃.
9, method as claimed in claim 6 is characterized in that: the temperature of described the 3rd thermal annealing is 350-450 ℃.
10, as claim 7,8 or 9 described methods, it is characterized in that: described thermal annealing is a rapid thermal annealing.
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| CN102983163B (en) * | 2011-09-07 | 2016-04-20 | 中国科学院微电子研究所 | Low source-drain contact resistance MOSFETs and manufacture method thereof |
| CN103000528B (en) * | 2011-09-16 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | There is semiconductor structure and the formation method in Ni suicide contacts district |
| KR101830782B1 (en) * | 2011-09-22 | 2018-04-05 | 삼성전자주식회사 | Electrode structure including graphene and feield effect transistor having the same |
| CN103065965B (en) * | 2011-10-20 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
| CN103137449B (en) * | 2011-12-01 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of grid, the manufacture method of transistor |
| CN102522327A (en) * | 2011-12-22 | 2012-06-27 | 上海华虹Nec电子有限公司 | Method for manufacturing self-aligned low-resistance gate RF LDMOS (radio-frequency laterally diffused metal oxide semiconductor) |
| CN103915326B (en) * | 2013-01-08 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method and semiconductor devices of self-aligned metal silicate |
| CN103456615B (en) * | 2013-09-02 | 2016-04-27 | 上海华力微电子有限公司 | Improve the method for metal silicide mask layer defect |
| US9240454B1 (en) * | 2014-10-22 | 2016-01-19 | Stmicroelectronics, Inc. | Integrated circuit including a liner silicide with low contact resistance |
| CN104867941B (en) | 2015-04-24 | 2018-05-11 | 京东方科技集团股份有限公司 | A kind of method for making array base palte and its array base palte and display device |
| CN112820778A (en) * | 2021-03-29 | 2021-05-18 | 厦门芯一代集成电路有限公司 | Novel high-voltage VDMOS device and preparation method thereof |
| CN113629009B (en) * | 2021-08-09 | 2023-10-24 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor cobalt silicide film layer, semiconductor device and memory |
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