CN100449364C - Method of supplying power to scan line driving circuit, and power supply circuit - Google Patents
Method of supplying power to scan line driving circuit, and power supply circuit Download PDFInfo
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- CN100449364C CN100449364C CNB2005101088487A CN200510108848A CN100449364C CN 100449364 C CN100449364 C CN 100449364C CN B2005101088487 A CNB2005101088487 A CN B2005101088487A CN 200510108848 A CN200510108848 A CN 200510108848A CN 100449364 C CN100449364 C CN 100449364C
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Abstract
A power supply circuit comprising a charge pump circuit supplies a supply voltage to a gate driver. A timing controller supplies a predetermined timing signal to a NAND circuit, a shutdown terminal of the charge pump circuit, and a gate shading circuit including a capacitor, a resistor, a NOT circuit, and a transistor. When this timing signal is high, the charge pump circuit makes a normal operation and the gate shading circuit is deactivated. When this timing signal is low, the charge pump circuit stops operating and the gate shading circuit is activated to drain an electric charge from the output of the charge pump circuit.
Description
Technical field
The present invention relates to method of supplying power, power circuit, display device and carrying device to the scan line drive circuit supply power of liquid crystal board of sweep trace and the rectangular configuration of data line etc.
Background technology
In recent years, the TFT of active array type (Thin Film Transistor) liquid crystal board etc. is popularized, and this liquid crystal board maximizes year by year.Along with liquid crystal board maximizes, the spurious impedance of sweep trace increases, and at the two ends of liquid crystal board, for example produces constant time lag in the scanning-line signal of pulse type.This constant time lag becomes the reason of liquid crystal board flicker.
[patent documentation 1] spy opens the 2000-221474 communique
But patent documentation 1 is configured for generating circuit and above-mentioned buffer circuit to vertical scanning driver supply power respectively as disclosed among its Fig. 1.Therefore, need to increase current sinking in order to carry out such control individually to this buffer circuit supply power.
Summary of the invention
The present invention is the invention in view of this situation, and its purpose is, method of supplying power, power circuit, display device and the carrying device that can suppress current sinking, make the flicker reduction of display board are provided.
In order to solve above-mentioned problem, the method of supplying power of one of the solution of the present invention, the scan line drive circuit supply line voltage that generation is used to drive the signal of the on-off element on the sweep trace that is connected to display board, corresponding to the conduction period of on-off element, make the waveform passivation (rounded) of supply voltage.According to this scheme, can suppress current sinking, and the flicker of display board is reduced.
Another program of the present invention is a power circuit.This power circuit is used to drive the scan line drive circuit supply line voltage of the signal of the on-off element on the sweep trace that is connected to display board to generation, it comprises: the voltage generation circuit that generates predetermined power voltage; And, be the circuit of waveform passivation electric charge of emission regulation from the output of described voltage generation circuit of making described supply voltage corresponding to conduction period of on-off element.' voltage generation circuit ' also can be charge pump circuit.Power circuit also can integrate on a Semiconductor substrate.According to this scheme, can suppress current sinking, and the flicker of display board is reduced.
During the discharging electric charge, voltage generation circuit also can stop the generation of supply voltage.According to this scheme, during the discharging electric charge, can suppress the current sinking of voltage generation circuit.The action of the action timing of voltage generation circuit and the circuit of discharging electric charge regularly also can be controlled by the timing signal that same timing controller generates.According to this scheme, during the discharging electric charge, can suppress the current sinking of voltage generation circuit, can also simplify circuit structure.
Can also comprise delay circuit, this circuit postpones the timing signal of the timing controller generation that scan line drive circuit is controlled.The action of voltage generation circuit regularly regularly also can be controlled by the timing signal after the delay circuit delays with the action of the circuit that discharges described electric charge.According to this scheme, be not subject to the timing signal of supplying with from timing controller, just can carry out shaping to output waveform.
A scheme more of the present invention is a display device.This device comprises: the scan line drive circuit that generates the signal that is used to drive the on-off element on the sweep trace that is connected to described display board; And the power circuit of such scheme.
According to this scheme, can realize suppressing current sinking, and make the display device of the flicker reduction of display board.
Another program of the present invention is a carrying device.This device comprises: display board; Generation is used to drive the scan line drive circuit of the signal of the on-off element on the sweep trace that is connected to described display board; And the power circuit of such scheme.From the direct supply that loaded to the power circuit supply power.' direct supply of loading ' also can be battery.
According to this scheme, can realize suppressing current sinking, and make the carrying device of the flicker reduction of display board.
Being noted that the combination in any of said structure parts or rearranging, all is effective as embodiments of the present invention.
In addition, all essential feature are not explained in general introduction of the present invention, so that the present invention also can be the sub-portfolio of these statement features.
Description of drawings
Explain embodiment below by reference with the accompanying drawing of the indefiniteness shown in the exemplary approach, identical parts are given identical label in these accompanying drawings, wherein:
Fig. 1 is the skeleton diagram of display device that has adopted the power circuit of embodiment.
Fig. 2 is the figure of structure of the power circuit of statement embodiment 1.
Fig. 3 (a), Fig. 3 (b) are the figure of the output waveform of the waveform of the timing signal supplied with of the timing controller of statement embodiment 1 and power circuit.
Fig. 4 (a), Fig. 4 (b) are the figure of the output waveform of expression gate drivers.
Fig. 5 is the figure of structure of the power circuit of expression embodiment 2.
Fig. 6 (a), Fig. 6 (b), Fig. 6 (c) are the figure of the output waveform of the waveform of both end voltage of waveform, the 3rd electric capacity of the timing signal supplied with of the timing controller of expression embodiment 2 and power circuit.
Fig. 7 is the figure of structure of the carrying device of expression embodiment 3.
Embodiment
Below, explain the present invention according to preferred implementation.This statement is not used in and limits scope of the present invention, but illustration the present invention.
At first, before the details of the power circuit 100 that embodiments of the present invention are described, the part related to the present invention of the display device 500 that has adopted this power circuit is described.Fig. 1 is the skeleton diagram of display device 500 that has adopted the power circuit 100 of embodiment.The details back of power circuit 100 and timing controller 200 is discussed.
With regard to display board 400, can use liquid crystal board or organic EL plate etc.A plurality of pixels are set in display board 400, and the pixel groups in the display board 400 is by the sweep trace 410 and data line 420 controls of rectangular configuration.Among Fig. 1, represented an image element circuit that pixel is controlled in the pixel groups in the display board 400.
This image element circuit comprises: two n channel transistors--the 1st transistor the 430, the 2nd transistor 434; The optical element 436 of organic EL etc.; The 1st electric capacity 432; Sweep trace 410; Power supply Vdd; And the data line 420 of input brightness data.Much less, optical element 436 also can be a liquid crystal cells.
The action of this image element circuit is as follows: for writing of the brightness data of optical element 436, be high level at sweep trace 410, during 430 conductings of the 1st transistor, the brightness data that is input to data line 420 is set in the 2nd transistor 434 and the 1st electric capacity 432.In luminous timing, the 1st transistor 430 ends for low level because of sweep trace 410, keeps the grid voltage of the 2nd transistor 434, comes luminous with the brightness data of setting.Have again, in Fig. 1, driven with active matrix has been described, but also can be the display board that passive matrix drives.
Like this, each pixel is subjected to light emitting control by the conduction and cut-off control of the grid of the 1st transistor 430.The control signal of pulse type of conduction and cut-off control that gate drivers 300 will be used for the grid of the 1st transistor 430 is applied to sweep trace 410.That is, has function as the scan line drive circuit of driven sweep line.
(embodiment 1)
Fig. 2 is the figure of structure of the power circuit 100 of statement embodiment 1.Power circuit 100 comprises charge pump circuit 110.Charge pump circuit 110 is that illustrated supply voltage boosts in the future, thereby exports the circuit of the voltage of certain level.In the present embodiment, for example export constant voltage about 30V.Charge pump circuit 110 portion within it comprises: not shown a plurality of electric capacity; And the switch that the charging of these electric capacity is carried out conduction and cut-off.Usually, charge pump circuit is controlled by the timing that discharges and recharges to each electric capacity, thereby input voltage can be boosted.The conduction and cut-off of this switch is regularly controlled by timing signal described later.
The 2nd electric capacity 122, resistance 124, and the 3rd transistor 128 be configured for from the output of charge pump circuit 110 circuit (below, be called grid cover circuit (gateshading circuit) 120) with predetermined timing discharging electric charge.The output of 122 pairs of charge pump circuits 110 of the 2nd electric capacity is charged.The logic of 126 pairs of timing signals described later of NOT circuit is reversed.The 3rd transistor 128 is the n channel transistor, conducting when it is output as high level at NOT circuit 126, and when low level, end.Have, the 3rd transistor 128 is so long as have the element of on-off action again, can be element arbitrarily.When resistance 124 is used for 128 conductings of the 3rd transistor, the charge discharging of charging in the 2nd electric capacity 122 is arrived ground.
Fig. 3 is the figure of the output waveform of the waveform of the timing signal supplied with of the timing controller 200 of expression embodiment 1 and power circuit 100.Timing controller 200 generates the output waveform shown in Fig. 3 (a), and is entered into the open circuit terminal and the grid cover circuit 120 of NAND circuit 102, charge pump circuit 110.As a result, wave form varies is the appearance of Fig. 3 (b), from power circuit 100 output voltages.
For example, suppose between 1 second, to show 60 frames that sweep trace is 760 a display board 400, then can be about 20 μ s with the distribution time set of a sweep trace 410.In this case, be used in the output waveform as power circuit 100 to generate passivation during, be set between the low period about 5 μ s.During these example, because of the standard of display board 400 etc. is a value suitable, that set change.
When above-mentioned timing signal was high level, NAND circuit 102 outputs were with the signal of the logic inversion gained of above-mentioned clock signal clk.In this case, charge pump circuit 110 utilizes the clock signal clk after this counter-rotating, and above-mentioned supply voltage is boosted.On the other hand, when above-mentioned timing signal was low level, regardless of above-mentioned clock signal clk, NAND circuit 102 was all exported high level all the time.In this case, charge pump circuit 110 can not boost because of being supplied to regularly.
Form the structure that the output voltage that can utilize self is controlled the switch of last grade inner electric capacity in structure with charge pump circuit 110, by having adopted the integrating circuit of operational amplifier, thereby under the situation of the output voltage that utilizes this integrating circuit in the switch control, the terminal that opens circuit can be connected to the power supply of this operational amplifier.In this structure, when above-mentioned timing signal is high level,, it is moved as usually to this operational amplifier supply power.On the other hand, when above-mentioned timing signal was low level, to this operational amplifier supply power, above-mentioned switch did not end, and the electric capacity of last level can not charge.Thus, charge pump circuit 110 stops action, not to 122 chargings of the 2nd electric capacity.
When grid cover circuit 120 was high level at above-mentioned timing signal, its 3rd transistor 128 ended, and inoperative.On the other hand, when above-mentioned timing signal was low level, its 3rd transistor 128 conductings can be discharged electric charge from the output of charge pump circuit 110.
The output waveform of power circuit 100 is adjusted according to specification of gate drivers 300 and display board 400 etc.This adjustment can be carried out according to the quantity of electric charge of discharging, by one of them of the size of the resistance value of the capacitance of the 2nd electric capacity 122, resistance 124 and the 3rd transistor 128 or their combination are adjusted, can set the quantity of electric charge that is discharged.
Conclude above explanation, with regard to the output of power circuit 100, when above-mentioned timing signal is high level, the output of charge pump circuit 110 intactly presents, when above-mentioned timing signal was low level, the output of charge pump circuit 110 was discharged, and presented the waveform of passivation.For example, for the timing signal of Fig. 3 (a), the output of power circuit 100 becomes the such output waveform of Fig. 3 (b).The high level of Fig. 3 (b) and low level potential difference (PD) Δ V can at random produce according to the resistance value of the capacitance of the 2nd electric capacity 122 and resistance 124.
The output of such power circuit 100 becomes the supply voltage of gate drivers shown in Figure 1 300.Fig. 4 is the figure of the output waveform of statement gate drivers 300.Gate drivers 300 generates the control signal that is used to drive the 1st transistor 430 according to this supply voltage and above-mentioned timing signal.The waveform of the control signal of Fig. 4 (a) statement present embodiment.Because supply voltage is passivated, so also being passivated to low level negative edge of its control signal from high level.
With respect to this, Fig. 4 (b) is according to the common supply voltage of passivation not and the control signal that above-mentioned timing signal generates.The waveform on Fig. 4 (b) left side is expressed near the signal of the point the gate drivers, and the waveform statement on the right is apart from the signal of gate drivers point far away.At the display board 400 of Fig. 1, come the switched scan line with the timing of negative edge.Therefore, shown in Fig. 4 (b), be passivated apart from the negative edge of gate drivers point far away, and the negative edge of near point is not when being passivated, then the distance because of the distance gate drivers produces deviation on the driving timing of the 1st transistor 430.About this point, shown in Fig. 4 (a), by generating corresponding control signal according to the supply voltage of passivation in advance, the timing that can make negative edge evenly and with the range-independence of distance gate drivers.
As described above, according to embodiment 1, make passivation between the high period of the control signal that applies on the sweep trace by the output of power circuit being carried out passivation, thereby can reduce the timing offset of the pixel selection on the same sweep trace, and can reduce the flicker of display board.
In addition, this supply voltage is carried out passivation during, stop action, thereby can suppress current sinking the constant voltage generative circuit of the charge pump circuit that constitutes power circuit etc.In the example of above-mentioned Fig. 3,, can be suppressed to the current sinking of 3/4 under the situation of not stopping by for one-period of 20 μ s and the action of charge pump circuit is stopped 5 μ s.
(embodiment 2)
Fig. 5 is the figure of structure of the power circuit 100 of statement embodiment 2.Embodiment 2 is the structures of having added delay circuit 130 in the power circuit 100 of embodiment 1.Give same numeral to the structure identical with embodiment 1, and different structure and the actions of explanation and embodiment 1.
Latch cicuit 132, the timing signal of supplying with from gate drivers 300 is imported into the set terminal, and the output of "AND" circuit 146 is imported into reseting terminal.At first, when above-mentioned timing signal is high level, the output high level.So the 2nd NOT circuit 142 is output as low level, on a terminal of "AND" circuit 146, be transfused to low level.Thus, "AND" circuit 146 is output as low level, is transfused to low level on the terminal that opens circuit of NAND circuit 102, charge pump circuit 110, the 3rd transistorized grid and the latch cicuit 132.Therefore, charge pump circuit 110 is kept common action, and grid cover circuit 120 does not discharge electric charge yet.
Then, latch cicuit 132 output low level when above-mentioned timing signal changes low level into.So the 2nd NOT circuit 142 is output as high level, on a terminal of "AND" circuit 146, be transfused to high level.Therefore, decide output according to input to another terminal.
The low level output of latch cicuit 132 ends the base stage of the 4th transistor 136.So the output of constant current source 134 does not make 136 conductings of the 4th transistor, output is presented on its collector, on voltage charging to the 3 electric capacity 138.The both end voltage Vc of the 3rd electric capacity 138 is imported into the counter-rotating input terminal of comparer 140.
On the non-counter-rotating input terminal of comparer 140, the reference voltage V r of input regulation.Can set timing period Δ t described later according to the current value I of this reference voltage value, constant current source 134 and the capacitance of the 3rd electric capacity 138.That is Δ t=VrC/I.
Comparer 140 is the output high level when the both end voltage Vc of the 3rd electric capacity 138 has surpassed the reference voltage V r of regulation, and when being lower than reference voltage output low level.The 4th transistor 136 become end after, through above-mentioned timing period Δ t, comparer 140 output low levels.At this moment, the 3rd NOT circuit is output as high level, all input terminals of "AND" circuit 146 are high level, so "AND" circuit 146 is to the terminal that opens circuit, the 3rd transistorized grid and the latch cicuit 132 output high level of NAND circuit 102, charge pump circuit 110.
Thus, charge pump circuit 110 stops action, and grid cover circuit 120 discharges electric charge from the output of charge pump circuit 110.The latch cicuit 132 of present embodiment keeps the input of set terminal when reseting terminal is high level.In this case, even above-mentioned timing signal changes high level into, also keep low level.
After the 4th transistor 136 ended, through above-mentioned timing period Δ t, comparer 140 changed high level into.So, the 3rd NOT circuit is output as low level, an input terminal of "AND" circuit 146 is a low level, so "AND" circuit 146 is to the terminal that opens circuit, the 3rd transistorized grid and latch cicuit 132 output low levels of NAND circuit 102, charge pump circuit 110.Therefore, charge pump circuit 110 reverts to common action, and grid cover circuit 120 does not discharge electric charge yet.In addition, when latch cicuit 132 is low level at reseting terminal, the value of set terminal is resetted.Therefore, if on this stage set terminal, be transfused to high level, then export high level.
Fig. 6 is the figure of the output waveform of the waveform of both end voltage Vc of waveform, the 3rd electric capacity 138 of the timing signal supplied with of the timing controller 200 of expression embodiment 2 and power circuit 100.Fig. 6 (a) and Fig. 3 (a) are same, the pulse signal that expression is generated by timing controller 200.Fig. 6 (b) is that the both end voltage of the 3rd electric capacity 138 is integrated, and rises to the reference voltage V r of comparer 140 simultaneously.During this reference voltage V r above-mentioned timing period Δ t.The output waveform of the power circuit 100 of Fig. 6 (c) expression embodiment 2.Compare as can be known with the output waveform of the embodiment 1 shown in Fig. 3 (b), be not subject to the pulse width of above-mentioned timing signal, can set make the waveform passivation during.That is, can generate passivation, so, can generate waveform arbitrarily by adjusting reference voltage value, the current value I of constant current source 134 and the parameters such as capacitance C of the 3rd electric capacity 138 of said reference voltage Vr corresponding to above-mentioned timing period Δ t.
As described above, according to embodiment 2, be not subject to the timing of supplying with from timing controller, can make the output waveform passivation of power circuit.Therefore, under the situation that this timing signal uses in other circuit such as gate drivers, can adjust above-mentioned output waveform and this circuit is not exerted an influence, can make design easily.
(embodiment 3)
Fig. 7 is the block scheme of structure of the carrying device 600 of expression embodiment 3.This carrying device 600 has loaded the carrying device of display part corresponding to portable telephone, PHS (Personal Handyphone System), PDA (Personal DigitalAssistance), digital camera, music playback etc.Carrying device 600 comprises: the display board 400 that shows the image of regulation; Control the gate drivers 300 of the sweep trace of this display board; The power circuit 100 of explanation in the embodiment 1,2 of display board supply power; Direct supply 610 to these power circuit 100 supply powers.Direct supply 610 is for example corresponding to lithium ion battery or TunePower etc.
As described above, according to embodiment 3,, can realize suppressing current sinking, and reduce the carrying device of the flicker of display board by loading the power circuit 100 of embodiment 1,2.Therefore, can take into account carrying device driving time prolongation and improve the picture quality that shows on the display part.
More than, according to embodiment the present invention has been described.It should be appreciated by those skilled in the art that these embodiments are illustrations, in these each structure members and the combination of each treatment process, can form various variation, and these variation also within the scope of the invention.
In embodiment, the example that adopts charge pump circuit in order to generate stable power voltage has been described.In this, also can use switching regulaor or common regulator.In this case, need be to the high slightly supply voltage of regulator input.
In addition, in embodiment, discharge electric charge, but also can discharge with constant current source by resistance.
In addition, in embodiment, the example that makes the negative edge passivation has been described, but also can have made the rising edge passivation of the signal that applies on the sweep trace.In addition, also can make both edge passivation.The waveform of such supply voltage can easily be realized by general wave shaping technology.
Preferred implementation of the present invention has used specific term to explain, but this statement only is used for the illustrative purpose, is noted that can to improve and change under the situation that does not break away from the spirit or scope of the present invention.
Claims (8)
1. method of supplying power is used to drive the scan line drive circuit supply line voltage of the signal of the on-off element on the sweep trace that is connected to display board to generation, it is characterized in that:
Corresponding to the conduction period of described on-off element, make the waveform passivation of described supply voltage.
2. power circuit is used to drive the scan line drive circuit supply line voltage of the signal of the on-off element on the sweep trace that is connected to display board to generation, it is characterized in that described power circuit comprises:
Generate the voltage generation circuit of predetermined power voltage; And
The electric charge of emission regulation from the output of described voltage generation circuit is with the circuit of the waveform passivation that makes described supply voltage corresponding to the conduction period of described on-off element.
3. power circuit as claimed in claim 2 is characterized in that, described voltage generation circuit corresponding to the described electric charge of discharging during and stop the generation of described supply voltage.
4. as claim 2 or 3 described power circuits, it is characterized in that the action of the action timing of described voltage generation circuit and the circuit of the described electric charge of discharging is regularly controlled by the timing signal that same timing controller generates.
5. as claim 2 or 3 described power circuits, it is characterized in that, also comprise the delay circuit of the timing signal delay that is used to make the timing controller generation of controlling described scan line drive circuit,
The action of the action timing of described voltage generation circuit and the circuit of the described electric charge of discharging is regularly controlled by the timing signal after the described delay circuit delays.
6. as claim 2 or 3 described power circuits, it is characterized in that described power circuit is integrated on a Semiconductor substrate.
7. display device is characterized in that comprising:
Display board;
Generation is used to drive the scan line drive circuit of the signal of the on-off element on the sweep trace that is connected to described display board; And
Claim 2 or 3 described power circuits.
8. carrying device is characterized in that comprising:
Display board;
Generation is used to drive the scan line drive circuit of the signal of the on-off element on the sweep trace that is connected to described display board; And
Claim 2 or 3 described power circuits,
From the direct supply that loaded to described power circuit supply power.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP289959/04 | 2004-10-01 | ||
| JP2004289959 | 2004-10-01 | ||
| JP181238/05 | 2005-06-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1760720A CN1760720A (en) | 2006-04-19 |
| CN100449364C true CN100449364C (en) | 2009-01-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101088487A Expired - Fee Related CN100449364C (en) | 2004-10-01 | 2005-09-30 | Method of supplying power to scan line driving circuit, and power supply circuit |
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| CN (1) | CN100449364C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5006655B2 (en) * | 2007-01-15 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | Power supply circuit for display device and display device |
| KR20080111233A (en) * | 2007-06-18 | 2008-12-23 | 삼성전자주식회사 | Driving apparatus for liquid crystal display and liquid crystal display including the same |
| KR101329963B1 (en) | 2008-12-29 | 2013-11-13 | 엘지디스플레이 주식회사 | Organic lighting emitting diode display deivce |
| KR102374748B1 (en) * | 2015-06-30 | 2022-03-17 | 엘지디스플레이 주식회사 | Power supply and display device using the same |
| KR102598383B1 (en) * | 2018-12-10 | 2023-11-06 | 엘지디스플레이 주식회사 | Display device and signal inversion device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121426A (en) * | 1985-11-22 | 1987-06-02 | Hitachi Ltd | Liquid crystal display |
| JPH11265169A (en) * | 1998-03-17 | 1999-09-28 | Toshiba Corp | Liquid crystal display, array substrate and driving method for array substrate |
| US6049319A (en) * | 1994-09-29 | 2000-04-11 | Sharp Kabushiki Kaisha | Liquid crystal display |
| JP2000221474A (en) * | 1999-01-29 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Method for driving liquid crystal display device |
| CN1282950A (en) * | 1999-07-30 | 2001-02-07 | 夏普株式会社 | Liquid crystal display device |
| JP2002023714A (en) * | 2001-05-29 | 2002-01-25 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
| US20030052851A1 (en) * | 2001-09-14 | 2003-03-20 | Takeshi Yano | Display driving apparatus and liquid crystal display apparatus using same |
-
2005
- 2005-09-30 CN CNB2005101088487A patent/CN100449364C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62121426A (en) * | 1985-11-22 | 1987-06-02 | Hitachi Ltd | Liquid crystal display |
| US6049319A (en) * | 1994-09-29 | 2000-04-11 | Sharp Kabushiki Kaisha | Liquid crystal display |
| JPH11265169A (en) * | 1998-03-17 | 1999-09-28 | Toshiba Corp | Liquid crystal display, array substrate and driving method for array substrate |
| JP2000221474A (en) * | 1999-01-29 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Method for driving liquid crystal display device |
| CN1282950A (en) * | 1999-07-30 | 2001-02-07 | 夏普株式会社 | Liquid crystal display device |
| JP2002023714A (en) * | 2001-05-29 | 2002-01-25 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
| US20030052851A1 (en) * | 2001-09-14 | 2003-03-20 | Takeshi Yano | Display driving apparatus and liquid crystal display apparatus using same |
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| CN1760720A (en) | 2006-04-19 |
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