CN100442486C - 具有热电元件来冷却管芯的微电子组件及其制造方法 - Google Patents

具有热电元件来冷却管芯的微电子组件及其制造方法 Download PDF

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CN100442486C
CN100442486C CNB2004800365541A CN200480036554A CN100442486C CN 100442486 C CN100442486 C CN 100442486C CN B2004800365541 A CNB2004800365541 A CN B2004800365541A CN 200480036554 A CN200480036554 A CN 200480036554A CN 100442486 C CN100442486 C CN 100442486C
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thermoelectric
micromodule
tube core
thermoelectric element
carrying substrate
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CN1890803A (zh
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施里拉姆·拉马纳森
萨拉·金
理查德·斯科特·利斯特
格雷戈里·克莱斯勒
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

本发明提供一种微电子组件，所述微电子组件具有形成在管芯上的热电元件，使得在电流流经所述热电元件时将热从所述管芯泵送走。在一个实施方案中，热电元件被集成在管芯有源侧上的传导互连元件之间。在另一个实施方案中，热电元件在管芯的背侧上并且被电连接到所述管芯前侧上的承载衬底。在再一个实施方案中，热电元件被形成在次衬底上并被转移到所述管芯。

Description

具有热电元件来冷却管芯的微电子组件及其制造方法
发明背景
1)发明领域
本发明一般涉及具有微电子管芯的微电子组件(assembly)，并且更具体地，涉及用来冷却这种组件的微电子管芯的系统。
2)相关技术的讨论
当半导体器件(例如，处理器和处理元件)在较高的数据率和较高的频率下持续地运行时，它们一般消耗较大的电流，并且产生较多的热。除了别的以外，为了可靠性的原因，希望将这些器件的运行维持在某个温度范围内。常规的热传递机制已经将这样的器件的运行限制到较低的功率水平、较低的数据率和/或较低的操作频率。由于尺寸和位置的制约以及热的限制，常规的热传递机制已经限制了热传递的能力。
附图说明
本发明通过参考附图的实施例的方式来进行描述，其中：
图1是根据本发明实施方案，部分地被处理来加工微电子组件的晶片衬底部分的剖面侧视图；
图2是在已部分处理的晶片衬底的介电层中蚀刻开口并且在所述开口中形成一个热电元件之后，类似于图1的视图；
图3是在另一个热电元件以及已部分处理的晶片的集成电路上的其他部件被形成以后，类似于图1的视图，其中，所述另一个热电元件具有与图2中形成的热电元件相反的掺杂传导类型；
图4是根据本发明实施方案，在晶片被最终处理，分割(singulate)成单个的管芯，并且一个管芯被倒装在承载衬底上并安装到所述承载衬底，以完成微电子组件的加工之后，类似于图3的视图；
图5是表示根据本发明另一个实施方案的微电子组件的侧视图，所述微电子组件在已分割管芯的有源侧的相对一侧上具有热电部件，并且被线接合到所述管芯有源侧上的封装衬底；
图6是表示根据本发明再一个实施方案的微电子组件的侧视图，所述实施方案与图5的实施方案的不同在于，短插栓(short plug)将管芯一侧上的热电元件与传导互连元件电连接，所述传导互连元件形成在所述管芯相对的、有源的一侧上；
图7是用来加工根据本发明再一个实施方案的微电子组件的两个晶片衬底的侧视图，一个晶片衬底载有有源集成电路，而另一个载有热电元件；
图8是在热电元件被相对于集成电路上的接触垫(contact pad)定位并且被附接到所述集成电路上的接触垫之后，类似于图7的视图；以及
图9是在图8的组件被分割成单个的件，并且集成电路和散热器被安装到这些所述件中的一个之后，类似于图8的视图。
具体实施方式
提供了一种微电子组件，所述微电子组件具有在管芯上形成的热电元件，以便在电流流过所述热电元件时将热从所述管芯泵送走。在一个实施方案中，热电元件被集成在管芯有源侧上的传导互连元件之间。在另一个实施方案中，热电元件在管芯的背侧(backside)上，并且被电连接到所述管芯前侧上的承载衬底。在再一个实施方案中，热电元件被形成在次衬底上并被转移到所述管芯。
附图中的图1示出了根据本发明的实施方案，部分地被处理来加工微电子组件的晶片10的部分。晶片10包括晶片衬底12、集成电路14和介电材料16。
晶片衬底10典型地由硅或者另一半导体材料制成。集成电路14包括形成在晶片衬底12中和在晶片衬底12上的集成电路元件18。集成电路元件18包括晶体管、电容器、二极管等。集成电路14还包括多个交替的介电层和金属层。金属层包括电源层(power plane)20和接地层(round plane)22。集成电路14还包括接触垫24，所述的接触垫24包含电源接触体24P、接地接触体24G和信号接触体24I。
此外，集成电路14的介电层中的插栓、通路和金属线形成电联接(electric link)26，只有几个电联接26被示出。
所述的电联接26包括将电源接触垫24P与电源层20互连的电源电联接26P1，以及将电源层20与集成电路元件18互连的电源电联接26P2。这样，通过电源接触垫24P、电源电联接26P1、电源层20和电源电联接26P2，可以给集成电路元件18中的一个或更多个提供功率。
电联接26包括将接地接触垫24G与接地层22互连的接地电联接26G1，以及将接地层22与集成电路元件18互连的接地电联接26G2。这样，通过接地接触垫24G、接地电联接26G1、接地层22和接地电联接26G2，可以给集成电路元件18中的一个或更多个提供接地。
信号电联接26I将信号接触垫24I与集成电路元件18中的一个或更多个互连，并且与电源层20和接地层22都脱离。通过更多个的信号电联接，例如信号电联接26I，可以给集成电路元件18提供信号，以及由集成电路元件18提供信号。
在集成电路14上面的层中形成介电材料16。介电材料16最初覆盖了接触垫24。随后，在介电材料16中蚀刻第一开口28，所述第一开口暴露了电源接触垫24P的区域。
如图2中所示，热电元件30随后在图1的开口28中形成。热电元件30的层可以被无电镀(electrolessly plate)或者溅射(sputter)，并且包括扩散阻挡层32、p掺杂半导体材料34(例如p掺杂的Bi2Te3，Bi2Te3和Sb2Te3的合金，或者Si和Ge的合金)和扩散阻挡层36，这些层在彼此顶部顺序形成。
如图3所示，在电源接触垫24P上，形成与热电元件30相邻的另一个热电元件40。热电元件30形成之后，热电元件40形成在在介电材料16中形成的开口之中。为了形成用于热电元件40的开口，在介电材料16的上面形成光致抗蚀剂层，并且在要形成热电元件40之处的上面的光致抗蚀剂层中掩模一开口。使用光致抗蚀剂层作为掩模，然后，要形成热电元件40之处的开口在介电材料16中被蚀刻。热电元件40包括扩散阻挡层42、n掺杂半导体材料44(例如n掺杂的Sb2Te3，Bi2Te3和Sb2Te3的合金，或者Si和Ge的合金)和扩散阻挡层46，这些层在彼此顶部顺序形成。因此，除半导体材料34是p掺杂的，而半导体材料44是n掺杂的之外，热电元件40与热电元件30是相同的。
传导间隔(spacer)部件48和50随后分别在接地和信号接触垫24G和24I上形成。可以通过在介电材料16以及热电元件30和40上形成光致抗蚀剂层，掩模所述光致抗蚀剂层，并且然后使用被掩模的光致抗蚀剂层中的开口来在介电材料16中蚀刻要形成传导间隔部件48和50处的开口，来蚀刻要在其中形成传导间隔部件48和50的开口。传导间隔部件48和50典型地由金属制成。
传导互连元件54随后形成，每一个在热电元件30或40，或者传导间隔部件48或50中相应的一个上。传导互连元件54高出(stand proud of)介电材料16，从而具有处于介电材料16的上层之上的共同平面中的上表面56。
图1到3中只示出晶片10的部分。然而，应该理解，所述晶片包括多个集成电路14，这些集成电路14形成在以x和y方向延伸通过所述的晶片的行和列中，每个集成电路14具有热电元件30和40、传导间隔部件48和50以及传导互连元件54的相同布图。
晶片10随后被切割或者分割成单个的管芯，每个管芯载有相应的集成电路和相关连接。每个管芯将包括在图3中所示的那部分晶片10所代表的部件。
图4示出了一个这样的管芯10A，所述管芯10A被倒装并且定位在以封装衬底60为形式的承载衬底上。在封装衬底60的上表面上形成封装引出端子62。传导互连元件54中的每一个与相应的封装引出端子62接触。
然后，将整个微电子组件64，包括管芯10A和封装衬底60，插在炉中，以回流传导互连元件54。传导互连元件54变软并熔化，随后使其冷却并再次固化。然后，每一个传导互连元件54被附着到相应的封装引出端子62，从而将管芯10A安装到封装衬底60，并且使管芯10A和封装衬底60电互连。
使用中，通过封装衬底60经由封装引出端子62A中的一个，可以将功率提供给热电元件30。电流通过p掺杂半导体材料34流向管芯。正如将在热电学领域中被理解的那样，流经p掺杂半导体材料的电流导致热在与所述电流流动方向相反的方向上被泵送。这样，在离开集成电路14的方向上，热通过热电元件30向封装衬底60泵送。流经热电元件30的电流被分成两支(bifurcated)。所述电流中的一部分提供功率给集成电路元件18中的一些，而所述电流中的一些流经电流接触垫24P，然后通过热电元件40到封装引出端子62B。流经n掺杂半导体材料44的电流导致热在所述电流流动的方向上被泵送。流经n掺杂半导体材料44的电流向远离集成电路14的方法流动，由此将热从集成电路14泵送走。
在另一个实施方案中，提供功率给热电元件的电源接触垫可以与提供功率给电路的电源接触垫分开。这一点将允许单独控制热电单元。当必须维持提供给电路的电压并且不让所述电压受到提供给热电模块的功率影响时，这样的构造可能是有用的。
由此可以看到，p掺杂半导体材料34和n掺杂半导体材料44都将热从集成电路14泵送走。可以因此向集成电路14提供局部化的冷却。更多的结构，例如包括热电元件30和40的结构，可以在贯穿(across)集成电路14的所希望的位置处形成，在那里可能需要额外的冷却。还应该注意的是，提供电流给热电元件30和40的同一阵列的封装引出端子62还提供功率、接地和信号给集成电路14。应该进一步注意的是，冷却是在需要它的地方被提供。当集成电路x-y方向上的某个区域需要功率时，所述功率通过同一区域中的热电元件来提供。特定面积内功率需求的增加将与那个特定面积内中生成的热的增多相对应。所述特定面积内功率上的提高同样也将与流经那个特定面积内的热电元件的电流的增大相对应。这样，当在特定面积内有增加的热被生成时，流经所述特定面积内的热电元件的电流将增大。
图5示出了另一个微电子组件70，包括以封装衬底72为形式的承载衬底，安装到封装衬底72的管芯74，管芯74上的热电元件76，集成热散器(heat spreader)78，以及散热器(heat sink)80。通过传导互连元件82，管芯74被安装并且电连接到封装衬底72。
热电元件76以与图3的热电元件30和40同样的方式来形成。热电元件76中的一些具有p掺杂半导体材料，而一些具有n掺杂半导体材料。热电元件76被这样排列，使得当电流流过热电元件76时，从管芯76的上表面向集成热散器78泵送热。
集成热散器78与热电元件76直接接触，并且散热器80位于集成热散器78上。正如被一般地理解的那样，散热器80包括基座和从所述基座延伸的多个翅，热可以从所述翅对流到周围的环境中。
提供引线接合线(wirebonding wire)84，通过所述引线接合线84，电流可以被提供给热电元件76或者从热电元件76传导出去。每根引线接合线84具有被连接到管芯74上表面上的垫的一个端，所述垫被连接到热电元件76中的第一个。所述相应的引线接合线84的相对端被接合到封装衬底72上的封装引线端子。电流通过所述第一热电元件76从封装引线端子流经相应的引线接合线84和相应的接触体。然后，电流能够流过偶数个热电元件76，并且通过引线接合线84中的另一根返回到封装衬底72。
图6示出了根据本发明再一个实施方案的微电子组件86。微电子组件86与图5的微电子组件70相同，并且同样的附图标记表示同样的部件。主要的差别是，微电子组件86包括比图5的管芯74薄得多的管芯88。短插栓90被形成为通过管芯88。热电元件76中的一些与插栓90中对应的那一个以及传导互连元件82中对应的那一个对齐。电流可以通过相应的传导互连元件82和相应的插栓90提供给相应的热电元件76。然后，所述电流可以流经偶数个热电元件76，并且通过彼此对齐的插栓90中的另一个和传导互连元件82中的另一个返回。
图7到图8示出了微电子组件的加工，其中热电元件被加工在单独的衬底上，然后被转移到晶片级的集成电路。然后，组合晶片被分割成单个的件。
特别地，参见图7，提供晶片94，所述晶片94具有晶片衬底96、形成在晶片衬底96上的集成电路98，以及形成在集成电路98上的接触垫100。图7还示出了具有热电元件104的转移衬底102，所述热电元件104以类似于图3的热电元件30和40的方式形成在转移衬底102上。图7还示出了间隔件106形式的互连结构。热电元件104和间隔件106具有形成在其上的传导互连元件108。
如图7所示，使每一个传导互连元件108与接触垫100中对应的那一个接触。然后，通过热回流过程，传导互连元件108被附着到接触垫100。提供包括晶片衬底96和102的组合晶片110。
现在参考图9。图8的组合晶片110被分割成单个的件112。晶片96因此被分割成件(piece)96A和96B，而晶片102被分割成件102A和102B。所述件102是相同的，并且每一个包括相应的集成电路98。在件102A和102B的上表面(upper level)提供金属化。所述件可以被安装在支撑衬底上并且被引线接合到所述支撑衬底。可替换地，件102A和102B可以变薄，并且件102A和102B中的通的通路(through-via)可以将金属化电连接到所述支撑衬底。
然后，集成热散器114可以被安装到件96A的晶片衬底部分的背侧上，即，与集成电路98相对，并且散热器116可以相对于(against)集成热散器114被定位并安装。
尽管已经描述并且在附图中示出了某些示例性的实施方案，但应该可以理解，这样的实施方案对于本发明仅仅是说明性而不是限制性的，并且本发明不受限于示出和描述的具体构造和排列，因为本领域普通技术人员可以进行修改。

Claims (36)

1.一种微电子组件，包括：
管芯衬底；
形成在所述管芯衬底上的集成电路，所述管芯衬底和集成电路共同形成管芯；以及
多个热电元件，所述多个热电元件形成在所述管芯的一侧上，所述集成电路在所述管芯衬底和所述热电元件之间，使得在电流流经所述热电元件时将热从所述管芯泵送走。
2.如权利要求1所述的微电子组件，其中所述集成电路包括连接到所述热电部件的电源层，从而电源通过所述热电部件提供给所述电源层。
3.如权利要求2所述的微电子组件，还包括形成在每个热电部件上的功率传导互连元件。
4.如权利要求3所述的微电子组件，还包括多个具有接触表面的接地和信号传导互连元件，所述接触表面在所述功率传导互连元件的接触表面的层中。
5.如权利要求4所述的微电子组件，还包括承载衬底和多个在所述承载衬底上的承载衬底连接盘，每个传导互连元件相对于相应的承载衬底连接盘来定位。
6.如权利要求1所述的微电子组件，还包括围绕所述热电元件的介电材料。
7.如权利要求1所述的微电子组件，其中所述热电部件是成对的，每一对包括相应的p掺杂的热电部件和相应的n掺杂的热电部件，所述微电子组件还包括多个形成在所述管芯上的联接元件，每个联接元件将相应的对的两个互连元件互连。
8.如权利要求1所述的微电子组件，其中所述热电元件被形成在所述管芯的一侧上，其中所述集成电路在所述管芯衬底和所述热电元件之间，所述微电子组件还包括围绕所述热电元件的介电材料，并且其中所述集成电路包括连接到所述热电部件的电源层，从而功率通过所述热电部件提供给所述电源层。
9.如权利要求7所述的微电子组件，还包括承载衬底和多个在所述承载衬底上的承载衬底连接盘，每一个传导互连元件相对于相应的承载衬底连接盘来定位。
10.如权利要求1所述的微电子组件，还包括围绕所述热电元件的介电材料。
11.如权利要求1所述的微电子组件，其中所述热电部件是成对的，每一对包括相应的p掺杂的热电部件和相应的n掺杂的热电部件，所述微电子组件还包括多个形成在所述管芯上的联接元件，每个联接元件将相应的对的两个互连元件互连。
12.如权利要求1所述的微电子组件，还包括承载衬底，所述管芯被安装到所述承载衬底，并且所述热电元件被电连接到所述承载衬底，以从所述承载衬底接收功率。
13.如权利要求12所述的微电子组件，还包括多个在所述承载衬底上的承载衬底连接盘，多个连接到所述热电元件的热电连接盘，以及多根引线接合线，每根引线接合线具有被附着到相应的承载衬底连接盘的一个部分以及被附着到相应的热电连接盘的另一个部分。
14.如权利要求13所述的微电子组件，其中所述热电连接盘被形成在所述管芯衬底上。
15.如权利要求14所述的微电子组件，还包括多个附着到在所述管芯的一侧上的传导互连元件，其中所述集成电路在所述传导互连元件和所述管芯衬底之间，每个传导互连元件与所述承载衬底连接盘中相应的一个相接触。
16.如权利要求1所述的微电子组件，还包括多个附着到在所述管芯的一侧上的传导互连元件，其中所述集成电路在所述传导互连元件和所述管芯衬底之间，每个传导互连元件与所述承载衬底连接盘中相应的一个相接触。
17.如权利要求16所述的微电子组件，还包括多个在所述管芯中的热电通路，第一多个所述传导互连元件将所述集成电路与第一多个所述承载衬底连接盘连接，并且第二多个所述传导互连元件中通过所述热电通路被连接到所述热电元件。
18.如权利要求17所述的微电子组件，其中所述热电元件中的至少一个与所述热电通路中的一个和所述传导互连元件中的一个对齐。
19.如权利要求1所述的微电子组件，还包括多个在所述管芯上的管芯连接盘，多个第一扩散阻挡层，每一个所述的第一扩散阻挡层在相应的管芯连接盘上，每一个热电元件被形成在相应的扩散阻挡层上。
20.如权利要求19所述的微电子组件，还包括至少一个在所述热电元件中的至少一个上的第二扩散阻挡层，其中所述相应的热电元件在所述第一扩散阻挡层中相应的一个和所述第二扩散阻挡层之间。
21.如权利要求19所述的微电子组件，其中所述热电元件被形成在所述管芯的一侧上，其中所述集成电路在所述管芯衬底和所述热电元件之间。
22.如权利要求20所述的微电子组件，还包括承载衬底，所述管芯被安装到所述承载衬底，并且所述热电元件被电连接到所述承载衬底，以从所述承载衬底接收功率。
23.如权利要求1所述的微电子组件，还包括热耦合到所述热电元件的热传导板，其中所述热电元件在所述管芯和所述热传导板之间。
24.如权利要求23所述的微电子组件，还包括多个从所述热传导板延伸的翅，从所述热传导板传导的热通过所述翅对流到周围的空气中。
25.一种制造微电子组件的方法，包括：
在第一支撑衬底上形成至少一个微电子电路；
在所述第一支撑衬底上形成多个热电元件，所述至少一个微电子电路在所述第一支撑衬底和所述多个热电元件之间，当所述微电子电路运行并且电流流经所述热电元件时，所述热电元件将热从所述微电子电路泵送走。
26.如权利要求25所述的方法，其中所述热电元件在所述微电子电路形成之后形成。
27.如权利要求25所述的方法，还包括在每一个热电部件上形成功率传导互连元件。
28.如权利要求27所述的方法，还包括形成多个具有接触表面的接地和信号传导互连元件，所述接触表面在所述功率传导互连元件的接触表面的层中。
29.如权利要求28所述的方法，还包括相对于相应的承载衬底连接盘定位所述的传导互连元件。
30.如权利要求25所述的方法，还包括形成介电材料，在所述介电材料中形成第一多个开口，在所述第一多个开口中形成第一传导类型的热电元件，随后在所述介电材料中形成第二多个开口，在所述第二多个开口中形成与所述第一传导类型相反的第二传导类型的热电元件，以及电互连所述热电元件对，每一个对具有一个所述第一传导类型的热电元件和一个所述第二传导类型的热电元件。
31.如权利要求25所述的方法，还包括在第二支撑衬底上形成所述热电元件，并且随后将所述热电元件连接到所述第一支撑衬底。
32.如权利要求31所述的方法，其中所述第一和第二衬底形成组合晶片，所述组合晶片通过至少切开所述支撑衬底中的一个来分割成管芯。
33.如权利要求32所述的方法，其中所述第一和第二支撑衬底被切开，以分割所述组合晶片。
34.一种制造微电子组件的方法，包括：
在第一支撑衬底上形成至少一个微电子电路；
在第二支撑衬底上形成热电元件；以及
随后将所述热电元件连接到所述第一支撑衬底，以使得所述至少一个微电子电路在所述第一支撑衬底和所述热电元件之间。
35.如权利要求34所述的方法，其中所述第一和第二衬底形成组合晶片，所述组合晶片通过至少切开所述支撑衬底中的一个来分割成管芯。
36.如权利要求35所述的方法，其中所述第一和第二支撑衬底被切开，以分割所述组合晶片。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005158917A (ja) * 2003-11-25 2005-06-16 Sharp Corp 電子ヒートポンプ装置、レーザ部品、光ピックアップおよび電子機器
US7589417B2 (en) * 2004-02-12 2009-09-15 Intel Corporation Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
KR100629679B1 (ko) * 2004-07-01 2006-09-29 삼성전자주식회사 열전 냉각 소자를 갖는 반도체 칩 패키지
JP4485865B2 (ja) * 2004-07-13 2010-06-23 Ｏｋｉセミコンダクタ株式会社 半導体装置、及びその製造方法
US7654311B2 (en) * 2004-10-20 2010-02-02 University Of Maryland Thermal management of systems having localized regions of elevated heat flux
US7290596B2 (en) * 2004-10-20 2007-11-06 University Of Maryland Thermal management of systems having localized regions of elevated heat flux
US20060243315A1 (en) * 2005-04-29 2006-11-02 Chrysler Gregory M Gap-filling in electronic assemblies including a TEC structure
EP1840980A1 (en) * 2006-03-31 2007-10-03 STMicroelectronics S.r.l. Structure comprising Peltier cells integrated on a semiconductor substrate and corresponding manufacturing process
US7825324B2 (en) 2006-12-29 2010-11-02 Alcatel-Lucent Usa Inc. Spreading thermoelectric coolers
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US7855397B2 (en) * 2007-09-14 2010-12-21 Nextreme Thermal Solutions, Inc. Electronic assemblies providing active side heat pumping
US20090071525A1 (en) * 2007-09-17 2009-03-19 Lucent Technologies, Inc. Cooling Hot-Spots by Lateral Active Heat Transport
DE102008049726B4 (de) * 2008-09-30 2012-02-09 Advanced Micro Devices, Inc. Gestapelte Chipkonfiguration mit stromgespeistem Wärmeübertragungssystem und Verfahren zum Steuern der Temperatur in einem Halbleiterbauelement
TWI405361B (zh) * 2008-12-31 2013-08-11 Ind Tech Res Inst 熱電元件及其製程、晶片堆疊結構及晶片封裝結構
JP5481104B2 (ja) * 2009-06-11 2014-04-23 ルネサスエレクトロニクス株式会社 半導体装置
TWI407545B (zh) * 2009-08-19 2013-09-01 Ind Tech Res Inst 整合熱電元件與晶片的封裝體
JP2011138879A (ja) * 2009-12-28 2011-07-14 Nec Toshiba Space Systems Ltd デバイス設置構造
US9601677B2 (en) * 2010-03-15 2017-03-21 Laird Durham, Inc. Thermoelectric (TE) devices/structures including thermoelectric elements with exposed major surfaces
US9276080B2 (en) * 2012-03-09 2016-03-01 Mcube, Inc. Methods and structures of integrated MEMS-CMOS devices
US8995134B2 (en) * 2011-05-27 2015-03-31 Lear Corporation Electrically-cooled power module
FR2977976A1 (fr) * 2011-07-13 2013-01-18 St Microelectronics Rousset Procede de generation d'energie electrique au sein d'une structure integree tridimensionnelle, et dispositif de liaison correspondant
ITRM20110472A1 (it) 2011-09-09 2013-03-10 Consorzio Delta Ti Res Componenti microelettronici, in particolare circuiti cmos, comprendenti elementi termoelettrici di raffreddamento ad effetto seebeck/peltier, integrati nella loro struttura.
US8604867B2 (en) * 2011-11-28 2013-12-10 Qualcomm Incorporated Energy harvesting in integrated circuit packages
US9190595B2 (en) * 2012-07-20 2015-11-17 Qualcomm Incorporated Apparatus and method for harvesting energy in an electronic device
JP2016527727A (ja) * 2013-07-30 2016-09-08 ハーマン ベッカー オートモーティブ システムズ ゲーエムベーハー 電子モジュール
TWI514528B (zh) * 2013-10-04 2015-12-21 Lextar Electronics Corp 半導體晶片結構
KR102187108B1 (ko) * 2013-12-12 2020-12-04 삼성전자주식회사 반도체 칩 및 이를 포함하는 전자 시스템
US10468330B2 (en) * 2013-12-12 2019-11-05 Samsung Electronics Co., Ltd. Semiconductor chip and electronic system including the same
MA40285A (fr) * 2014-06-02 2017-04-05 Hat Teknoloji A S Configuration de cellule tridimensionnelle intégrée, réseau de refroidissement intégré et circuit intégré précaractérisé
US9746889B2 (en) 2015-05-11 2017-08-29 Qualcomm Incorporated Package-on-package (PoP) device comprising bi-directional thermal electric cooler
US11177317B2 (en) * 2016-04-04 2021-11-16 Synopsys, Inc. Power harvesting for integrated circuits
WO2019066155A1 (ko) * 2017-09-29 2019-04-04 한국과학기술원 2d 열감 제공 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230497B1 (en) * 1999-12-06 2001-05-15 Motorola, Inc. Semiconductor circuit temperature monitoring and controlling apparatus and method
US20030122245A1 (en) * 2000-11-30 2003-07-03 International Business Machines Corporation Electronic module with integrated programmable thermoelectric cooling assembly and method of fabrication
US6614109B2 (en) * 2000-02-04 2003-09-02 International Business Machines Corporation Method and apparatus for thermal management of integrated circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224253A (ja) * 1984-04-20 1985-11-08 Fujitsu Ltd 半導体装置およびその製造方法
DE3935610A1 (de) * 1989-10-26 1991-05-02 Messerschmitt Boelkow Blohm Monolithisch integrierbares peltier-kuehlelement
JPH11135692A (ja) * 1997-10-31 1999-05-21 Sony Corp 集積回路
JPH11214598A (ja) * 1998-01-23 1999-08-06 Takeshi Aoki 大規模集積回路（ｌｓｉ）チップの冷却方法
US6388185B1 (en) * 1998-08-07 2002-05-14 California Institute Of Technology Microfabricated thermoelectric power-generation devices
US6700053B2 (en) * 2000-07-03 2004-03-02 Komatsu Ltd. Thermoelectric module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230497B1 (en) * 1999-12-06 2001-05-15 Motorola, Inc. Semiconductor circuit temperature monitoring and controlling apparatus and method
US6614109B2 (en) * 2000-02-04 2003-09-02 International Business Machines Corporation Method and apparatus for thermal management of integrated circuits
US20030122245A1 (en) * 2000-11-30 2003-07-03 International Business Machines Corporation Electronic module with integrated programmable thermoelectric cooling assembly and method of fabrication

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