CN100435126C - JTAG simulation signal intensifier circuit based on high-speed processor - Google Patents

Abstract

The invention makes quantitative analysis for the high speed low energy consumption processor JTAG interface and IEEE1149. 1 standard, innovatively proposing a reinforced JTAG interface. It makes intensified modification for the JTAG of the TMS320C6713 based on the said principle. The modified JTAG can support flat cable over 120 cm, reaching the advanced national level. This design solves the difficult simulation of hardware with long distance of high speed low power processor, enlarging the application of DSP, FPGA and ARM. It can be used for remote distance tuning of the DSP system, with certain reference value of the relative embedded FPGA system design.

Description

JTAG simulation signal intensifier circuit based on high speed processor

Technical field

The invention belongs to the electronics design field, specifically be based on the JTAG simulation signal intensifier circuit of high speed processor.

Background technology

Jtag interface is a kind of boundary scan agreement of IEEE1149.1 regulation, is used for the external interface bus state of IC device is scanned.

In recent years, along with the development of microprocessor technology, the intermediary that increasing processor and logical device adopt jtag interface to communicate by letter with PC as its kernel, and develop emulator thus, the in-circuit emulation of realization processor or programmable logic device (PLD).Such as FPGA, DSP, ARM, application specific processors such as MIPS all have been equipped with the jtag interface that is exclusively used in emulator.And for DSP, FPGA, devices such as CPLD, the emulator of jtag interface are the instruments of its unique support in-circuit emulation and programming program.Be with jtag interface at dsp system, all be indispensable standard interface in the embedded system.

Yet, because advanced microprocessor generally all adopts low power dissipation design, the control ability of jtag interface thereby be subjected to restriction significantly.IEEE1149.1 standard itself has also illustrated the restriction that JTAG debugging cable has distance.Most microprocessors, such as ARM, DSP etc., CPU to the control of JTAG all in 10 inches scope.To some DSP devices that is used for the high strength computing, such as the TMS320C6000 series DSP, the developer offers some clarification on, and the distance between jtag interface and the CPU must be in 6 inches scopes.

But, all require the scope beyond 6 inches that processor is carried out simulation hardware debugging and programming program under a lot of occasions, thereby this short distance characteristic of jtag interface seriously fettered the use occasion and the function of processor, also is a thorny for it problem of countless DSP and embedded system development person.

JTAG mouth for long distance uses, and the JTAG emulator of supporting long distance, and domestic still do not have similar exploitation case and a Related product.

Summary of the invention

The objective of the invention is to, promptly at above problem, analyze the signal characteristic of high speed processor jtag interface, with and the reason that can not debug at a distance, propose a kind of JTAG simulation signal intensifier circuit, solve JTAG this puzzlement high-speed dsp slip-stick artist of cable problem for many years that can not extend based on high speed processor.

Main contents of the present invention are:

JTAG simulation signal intensifier circuit based on high speed processor, include the jtag interface of high speed processor, the JTAG plug of emulator, the TMS, TDI pin that it is characterized in that the JTAG plug of described emulator forward respectively inserts behind the bus driver and the JTAG pin that inserts high speed processor again, and the TMS of the JTAG plug of emulator, TDI pin connect a pull-up resistor respectively; Insert the TDO pin of the JTAG plug of emulator behind the TDO pin forward access bus driver of the jtag interface of described high speed processor again; Add the clock signal forward and insert the TCK-RET pin that inserts the JTAG plug of emulator behind the bus driver again, the PD pin of the JTAG plug of emulator connects source voltage.

Principle of work of the present invention:

According to the transmission feature of high speed signal, the flat cable impedance R of carrying signal _lCan calculate by following formula:

$R_l=\frac{87}{\sqrt{{\mathrm{\ξ}}_r+1.41}}\ln \left(\frac{5.98h}{0.8\mathrm{\ω}+t}\right)\·l$

The propagation delay t of transmission line _r:

$t_r=85\sqrt{0.475{\mathrm{\ξ}}_r+0.67}\·l$

Wherein, definition is h to ground level, and live width is ω, and line is thick to be t, and effectively relative dielectric constant is ξ _r, line length is 1.

According to equivalent model set forth above, flat cable must have the certain energy loss.Through experimental verification, if this energy loss accounts for 8% of CPU power consumption, the JTAG signal is with unavailable.

In addition, according to the requirement of JTAG signal to sequential, signal must satisfy sequential integrality equation:

T ₁≥t _valid+t _flight+t _setup+C _LKskew+C _LKjitter

t _valid+t _flight≥t _hold+C _LKskew+C _LKjitter

The explanation of above-mentioned each parameter and definition:

The synchronous clock (PC and high speed processor are by the clock frequency of JTAG swap data in other words) of definition JTAG agreement is T ₁Definition signal Time Created (being that data were remained valid the required time before the clock rising edge arrived) of device (such as driver) of process be t _SetupDefinition signal retention time (being that data were remained valid the required time after the clock rising edge arrived) of device (such as driver) of process be t _HoldThe flight time (be the time delay of signal transmission) of definition signal on printed panel is t _FlightBe t the effective time of definition signal _ValidDefinition clock skew deviation is CLK _SkewDefinition clock jitter deviation is CLK _Jitter

If the length of cable of each signal differs, perhaps some signal has passed through driving, may cause above two equations not satisfy, and breaks the sequential rule of jtag interface signal, causes the unavailable of the long cable interface signal of JTAG equally.

For above-described power problems, signal wire can be added driving, and will draw on the part signal, strengthened the driving force of processor.Clock with in the next synchronous jtag interface of external clock plays the effect of correction to it.

Simultaneously, because the signal through overdriving must satisfy the sequential integrality of qualification, so following qualification should be arranged to the selection of driver:

t _setup≤T ₁-t _valid-t _fkight-C _LKskew-C _Ljitter

t _hold≤CLK _skew+CLK _jitter-t _valid-t _flight

The effect of invention

Test in dsp system above, can solve the problem that the JTAG cable can not extend fully.

Plain edition JTAG and the enhancement mode JTAG effect comparison table of table 1DSP

The jtag interface pattern	DSP end electric current during cable 10cm	DSP end electric current during cable 20cm	DSP end electric current during cable 40cm	DSP end electric current during cable 60cm	DSP end electric current during cable 80cm	DSP end electric current during cable 100cm	Workable nose cable length
								Plain edition	0.28A	0.26A	0.18A	0.16A	0.08A	0.06A	20cm
The present invention	0.28A	0.28A	0.28A	0.28A	0.28A	0.27A	120cm

As shown in Table, the plain edition jtag interface is when cable elongates, and source end electric current sharply descends, and under the 40cm cable, it is original 64% that source end electric current has only, and makes the JTAG cisco unity malfunction.And for enhancement mode JTAG, when cable 100cm, source end electric current is only by drop-down 0.01A.Through test, the enhancement mode cable is still available when 120cm.

Description of drawings

Fig. 1 is a circuit diagram of the present invention.

Fig. 2 is the enhancement mode jtag interface circuit diagram of TMS320C6713 chip of the present invention.

Embodiment

The high-speed floating point dsp chip TMS320C6713 that releases with TI company is an example.TMS320C6713 dominant frequency 300MHZ, core voltage is 1.2V, power consumption 1.1W is typical high-speed low-power-consumption processor.Its jtag interface is tested, found that the speed of itself and PC swap data is different because of the emulator pattern, the emulator of general performance is operated in more than the 80MHZ.

Through investigation, all on the market based on TMS320C6713 jtag interface and the distance of processor all at 10 centimetres with interior (i.e. all high speed processors of using at present, distance between its emulator and the circuit board is all in 10 centimetres, do not have to find that the example of breaking through this distance, the application scenario that has seriously fettered high speed processor are arranged.This strengthens module problem to be solved just for this).With flat cable jtag interface is extended to 20 centimetres, send out system power and dragged down, and can't normally enter simulation status, promptly Target Board can't be communicated by letter with PC.

The jtag interface of TMS320C6713 has 13 signal wires, it can be changed into the enhancement mode jtag interface.For strengthening the output driving force of DSP, with EMU0, EMU1, TMS moves 3.3V (according to the Transistor-Transistor Logic level characteristic, the signal tolerance limit that receives with emulator, and the nominal value of resistance, pull-up resistor R5 wherein, R6, R7, R8 get 4.7K ohm) on the TDI; With the clock in the next synchronous JTAG agreement of the external clock that sets; Simultaneously, to TMS, TDI, TDO and TCK_RET signal connect respectively along side signal transmission to bus driver; And long cable is terminated, avoid the reflection of signal.Physical circuit is referring to Fig. 2.

Wherein, because cable has reflection when lengthening, so need termination.The source end driving force of considering high speed processor is too small, so adopt the top series termination.According to the calculating in the formula (5), the impedance of transmission line is approximately 30 ohm, gets final product so get R1=R2=R3=33 ohm.

Claims (1)

1, based on the JTAG simulation signal intensifier circuit of high speed processor, include the JATG interface of high speed processor, the JATG plug of emulator, after it is characterized in that TMS, the TDI pin of the JTAG plug of described emulator forward inserting first bus driver and second bus driver respectively, insert the TMS and the TDI pin of the jtag interface of high speed processor more respectively, the TMS of the JTAG plug of emulator, TDI pin connect a pull-up resistor respectively; The TDO pin forward of the jtag interface of described high speed processor inserts the TDO pin that inserts the JTAG plug of emulator behind the 3rd bus driver again; Add the clock signal forward and insert the TCK-RET pin that inserts the JTAG plug of emulator behind the 4th bus driver again, the PD pin of the JTAG plug of emulator connects source voltage.

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