CN100405786C - Sharing cache dynamic threshold early drop device for supporting multi queue - Google Patents

Abstract

The present invention provides a sharing cache dynamic threshold early drop device for supporting multiple queues, which belongs to the technical field of IP and is realized on a piece of field programmable gate array (FPGA). The sharing cache dynamic threshold early drop device is characterized in that the sharing cache dynamic threshold early drop device comprises circuits shown in figure 1 of an IP grouping division circuit (1-1), a dynamic threshold early drop circuit (1-2), a cell counting circuit (1-3), an idle block management circuit (1-4), a DDR controller (1-5), a queue scheduling circuit (1-6) and a piece-out DDR memory (1-7). The sharing cache dynamic threshold early drop device dynamically adjusts parameters of a random early detection (RED) algorithm according to the average queue length of each currently active queue and the average queue length of the whole sharing cache region and provides a sharing cache dynamic threshold early drop method for supporting multiple queues. The sharing cache dynamic threshold early drop device has the advantages of less packet loss ratio, high cache utilization rate and high fairness. The sharing cache dynamic threshold early drop method for supporting multiple queues keeps the advantages of an RED mechanism and a dynamic threshold (DT) mechanism and uses step type drop curve approximation, and the method is favorable for the realization in the FPGA.

Description

Support the shared buffer memory dynamic threshold early drop device of many formations

Technical field

The invention belongs to the IP technical field.

Background technology

The current Internet intermediary device, as router etc., the control by to the length of buffer queue of its inside influences the congestion situation with Control Network.Being seen in traditional buffer queue administrative mechanism of equipment at present is tail drop (TailDrop) mechanism: each formation is provided with a length threshold, if queue length does not arrive the setting thresholding, receives all groupings and enter formation; Otherwise abandon the grouping of arrival.This mechanism realizes simple, but has three serious defectives:

(1) the full queue state of Chi Xuing (Full Queues);

(2) Business Stream is to the deadlock (Lock Out) of buffer memory;

(3) global synchronization of traffic carrying capacity (Global Synchronization);

Present universally recognized method is the enhancement function that adds intermediate node: active queue management (AQM:Active QueueManagement).Be that intermediate node need abandon the part grouping in advance before network enters congestion situation,, avoid congested generation so that Transmission Control Protocol responds the transmission rate of the source end that slows down.Adopted AQM mechanism is earlier detection (RED:Random Early Detection) method at random in prior network device.But major defect that should mechanism is:

(1) the setting difficulty of parameter, and its performance sensitive is in the variation of parameter and network condition;

(2) need parameter and calculating be set to each single formation, be unfavorable for the situation of number of queues or network flow expansion for interface quantity;

(3) in the RED algorithm a lot of multiplyings are arranged, need ample resources, be difficult to use the hardware realization of High Speed.

Summary of the invention

The objective of the invention is to propose a kind of shared buffer memory dynamic threshold early drop device that can carry out the many formations of support of high speed processing from the angle of hardware.Compare with the random early detection (red) mechanism that generally adopts at present, the present invention comprises the characteristics and the content of following components:

(1) dynamically adjusts the quene threshold value method of dividing into groups to abandon.Original RED algorithm need be set the parameter of the thresholding of a pair of maximum, minimum queue length, when quene state be in this to the scope of thresholding in the time, arrive grouping according to certain probability dropping.Because parameter is predefined, be difficult to satisfy changeable network condition, thereby performance can change along with the variation of setup parameter and network condition.The present invention overcomes the dependence of RED algorithm for parameter setting and network condition, dynamically adjust a pair of thresholding that divides into groups to abandon, promptly dynamically adjust the threshold value that abandons control according to the average queue length of each current active formation and the average queue length of whole shared cache area.This machine-processed basic thought is: the trend increase when the network congestion situation when promptly reduce in the remaining cache space, enters the control stage that grouping abandons in advance; And the trend of working as the network congestion situation weakens, and when promptly the remaining cache space increases, postpones entering the control stage that grouping abandons.

(2) adopt staged to abandon curve method and in hardware, realize abandoning of grouping.After dynamically determining the scope that grouping abandons, need carry out part to the grouping that enters the arrival stream that abandons in the control range and abandon.For the stream that abandons thresholding the closer to maximum, will abandon many more arrival groupings, relatively,, will abandon few more arrival grouping for the stream that abandons thresholding the closer to minimum.And when this network flow abandons thresholding above maximum, abandon fully and arrive grouping.For being positioned at the formation that abandons the scope network flow, we adopt staged as shown in Figure 3 to abandon the ratio that curve calculates the grouping that abandon, thereby the computing of having avoided floating-point makes it possible to the mode realization of High Speed with hardware consulting table.

(3) the many queue management mechanisms on shared buffer memory.Along with the increase of the number of present internet network flow with to the raising of the quality of service requirement of diverse network stream, also requirement can be supported the independent queuing and the management of a large amount of network flows in the network intermediary device.Traditional method is the length that configures number of queues and each formation in advance.This method buffer memory utilance is low, and is unfavorable for the expansion of number of queues.The present invention carries out the buffer memory of different grouping on shared buffer memory.When network flow arrives or withdraws from intermediary device, dynamically generate or cancel formation.When the grouping of having set up the network flow of formation arrives, adopt the method described in (1), (2), judge whether to admit this grouping.Be that then allocation space is connected in its described formation from the buffer memory of free time; , then directly do not abandon.

Support the shared buffer memory dynamic threshold early drop device of many formations, it is characterized in that this device is realized with fpga chip, contained in this fpga chip; IP packet fragmentation circuit, free block management circuit, the outer double data rate memory controller of sheet, stream element count circuit, queue scheduling circuit and dynamic threshold early drop circuit, wherein:

The output of IP packet fragmentation circuit links to each other with the dynamic threshold early drop circuit, the input and output of free block management circuit link to each other with the dynamic threshold early drop circuit, the input and output of the outer double data rate memory controller of sheet link to each other with the dynamic threshold early drop circuit, the input and output of stream element count circuit link to each other with the dynamic threshold early drop circuit, and the input and output of queue scheduling circuit link to each other with the dynamic threshold early drop circuit.

IP packet fragmentation circuit, this circuit is cut apart the elongated IP grouping that arrives by the stream element length of setting, obtain the stream unit of fixed length, represents that with cell described IP packet fragmentation circuit contains:

The 1st push-up storage is provided with IP grouping input;

Counter, the count signal input of this counter are read the FIFO terminal count output with described the 1st push-up storage and are linked to each other;

Splitter, this splitter have two inputs: an input links to each other with the IP data output end of described the 1st push-up storage, and another input of this splitter links to each other with the terminal count output of described counter;

IP header packet information register, the IP header packet information input of this register links to each other with the IP header packet information output of described splitter;

Stream unit header register is provided with stream unit input, and this input links to each other with the corresponding output end of described IP header packet information register;

Be provided with predetermined stream element length in the selector, the stream unit header information input terminal of described selector, IP data input pin link to each other with the IP data output of described stream unit header register, splitter respectively successively;

Stream cell data register, the stream cell data input of this register links to each other with the corresponding output end of described selector;

The 2nd push-up storage, the stream cell data input of this memory links to each other with the corresponding output end of described stream cell data register, and the stream unit that obtains is cut apart in this push-up storage output;

Stream element count circuit, contain: forward-backward counter and magnetic RAM, described forward-backward counter is provided with: the index signal input is admitted in the stream unit, the stream unit of the outer double data rate memory of receiving sheet; Stream cell scheduling index signal input receives the scheduling signals that flows the unit; Previous stream number of unit input; Described magnetic RAM is represented with MRAM, is provided with: the stream number input of stream unit; Current stream number of unit input, this input links to each other with the current stream number of unit output of described forward-backward counter; This MRAM also has: before flowed the unit number output, this output links to each other with the previous stream number of unit input of described forward-backward counter; This forward-backward counter adds the formation hour counter and adds 1 being admitted when a stream unit, is left the formation hour counter and subtracts 1 when a stream unit accesses, and also is provided with the value W of formation weight in this forward-backward counter _q, be calculated as follows t average queue length L constantly ⁱ _Avg(t) output:

L ⁱ _avg(t)＝(1-W _q)L ⁱ _avg(t _old)+W _qQ ⁱ(t)

Wherein, L ⁱ _Avg(t _Old) be the t previous stream unit number of formation i constantly;

Q ⁱ(t) be the stream number of unit that t formation constantly i arrives, this forward-backward counter is provided with a Q (t) output simultaneously, and Q (t) is meant t all queue length summations constantly, Q (t)=∑ _iQ ⁱ(t);

The free block management circuit, this circuit is a free block forward-backward counter, be provided with the capacity of the outer double data rate memory of sheet in this counter, this forward-backward counter also is provided with the stream unit and admits index signal input and stream cell scheduling index signal input, when the adding formation is admitted in a stream unit, when perhaps a stream unit is accessed formation, this forward-backward counter subtracts 1 or add 1 to the idle capacity of the outer double data rate memory of sheet set respectively successively, exports the idle capacity of this sheet double data rate memory in view of the above;

The controller of the outer double data rate memory of sheet, this controller is connecting a described outer double data rate memory, and the access visit of this memory is controlled;

Queue scheduling circuit, this circuit are provided with the queue scheduling signal output part that the stream unit in the described outer double data rate memory is read in scheduling;

The dynamic threshold early drop circuit, this circuit is provided with: L ⁱ _Avg(t) register, abandon the lower threshold L of the queue length of control _Min(t) first arithmetic device of computing, abandon the upper limit threshold L of the queue length of control _Max(t) second arithmetic device of computing, comparator and abandon the 3rd arithmetic unit of control, wherein,

First arithmetic device is built-in with L _Min(t) redundancy is represented with α, also is equipped with the capacity of described outer double data rate memory, represents with B, and unit is the stream element length, and this arithmetic unit receives Q (t) signal and is calculated as follows L by Q (t) signal input part _Min(t):

L _min(t)＝α(B-Q(t))；

Second arithmetic device is built-in with L _Max(t) redundancy is represented with β, and β＞α also is equipped with the capacity of described outer double data rate memory, represents with B, and unit is the stream element length, and this arithmetic unit is by Q (t) signal input part reception Q (t) signal and be calculated as follows L _Max(t):

L _max(t)＝β(B-Q(t))

Q (t) output of the forward-backward counter in above-mentioned each Q (t) signal input part and the described stream element count circuit links to each other;

Comparator is built-in with maximum drop probability p _Max, and this comparator is provided with: L ⁱ _AvgThe current stream number of unit output of the forward-backward counter in (t) signal input part, this input and described stream element count circuit links to each other, and this comparator also is provided with L _Min(t) signal and L _Max(t) signal totally two inputs, this comparator is receiving L ⁱ _Avg(t), L _Min(t), L _Max(t) behind the signal, carry out according to the following steps successively:

Step 1: if $L_{\mathrm{avg}}^i\left(t\right)\≤L_{\min }\left(t\right),$ Then receive the grouping that all arrives, and all stream unit of output arrival, the value of abandoning is 0;

Step 2: if $L_{\min }\left(t\right)<L_{\mathrm{avg}}^i\left(t\right)<L_{\max }\left(t\right)$ The time, then calculate drop probability p _a, and arrive grouping with this probability dropping:

$p_b=p_{\max }\frac{({L^i}_{\mathrm{avg}}\left(t\right)-L_{\min }\left(t\right))}{(L_{\max }\left(t\right)-L_{\min }\left(t\right))}$

p _a=p _b/ (1-cp _b), establish c=-1;

Step 3: if $L_{\mathrm{avg}}^i\left(t\right)\&GreaterEqual;L_{\max }\left(t\right),$ Then abandon whole groupings, c=0;

The 3rd arithmetic unit, this arithmetic unit abandons sign by the stream unit of described comparator output, and promptly the value of described c is calculated as follows drop probability p _a:

C=-1, then p _a=p _b/ (1+p _b), the grouping that arrives is divided in the discarded part;

C=0, then p _a=p _b, abandon the grouping of all arrival.

This by test proof, has the advantage that adaptability is strong, the buffer memory utilance is high and support multithread formation dynamic management mechanism.

Description of drawings

Fig. 1: basic configuration module and external interface relation

Fig. 2: the RED algorithm abandons curve

Fig. 3: the staged of drop mechanism of the present invention abandons curve

Fig. 4: hardware realization flow figure

Fig. 5: IP packet fragmentation circuit (1-1)

Fig. 6: dynamic threshold early drop circuit (1-2)

Fig. 7: cell counting circuit (1-3)

Fig. 8: free block management circuit (1-4)

Fig. 9: DDR controller (1-5)

Figure 10: queue scheduling circuit (1-6)

Figure 11: second section abandons curve waveform (a)

Figure 12: second section abandons curve waveform (b)

Figure 13: the 3rd section abandons curve waveform (a)

Figure 14: the 3rd section abandons curve waveform (b)

Figure 15: the 4th section abandons curve waveform (a)

Figure 16: the 4th section abandons curve waveform (b)

Embodiment

The Internet engineering duty group (IETF) has proposed the AQM technology and has recommended RED mechanism.When the router of realizing the RED algorithm is found congested omen, some groupings in the random drop buffer queue in advance, rather than abandon all new groupings after buffering area takes by the time.The minimum threshold min that surpasses an appointment when the average queue length of the buffer memory of network intermediary device _ThThe time, just think congested omen to have occurred that at this moment router is by certain Probability p _aAbandon grouping, this Probability p _aBe the function of average queue length avg (t):

$p_b=p_{\max }\frac{(\mathrm{avg}\left(t\right)-{\min }_{\mathrm{th}})}{({\max }_{\mathrm{th}}-{\min }_{\mathrm{th}})}$

p _a＝p _b/(1-cp _b)

P wherein _MaxBe the maximum drop probability of setting, the value of c is a constant.

The max threshold max that surpasses an appointment when average queue length _ThThe time, router thinks that heavy congestion has appearred in network, all groupings all will abandon.The RED algorithm abandons curve as shown in Figure 2.

There is following problem when from the introduction of above-mentioned RED algorithm as can be known, hardware is realized the RED algorithm:

(1) selection of parameter: min _Th, max _Th, max _pAnd w _qIsoparametric selection has a significant impact the RED algorithm, but these parameters set in advance, can not reflect the situation of current network in real time;

(2) in the RED algorithm a lot of multiplyings are arranged, also need to generate random number in addition, certain difficulty is arranged with the hardware realization of High Speed;

(3) method of RED algorithm employing first in first out is dispatched a grouping that receives all connections in the formation multiplexing, but does not monitor the state of each stream, does not therefore support the many formations of multithread.

The present invention is on a slice FPGA, write realization with hardware description language Verilog HDL, its basic structure and external interface relation are as shown in Figure 1, each circuit working flow process is: when an IP grouping arrives this device, by IP packet fragmentation circuit (1-1) cutting is the data cell of the fixed length of 60 bytes, be called cell, send it to dynamic threshold early drop circuit (1-2) then.Dynamic threshold early drop circuit (1-2) module implements to admit and abandon control according to the strategy of dynamic threshold early drop method to cell, the cell that is admitted adds by DDR controller (1-5) and writes in the corresponding network flow buffer queue of the outer DDR memory (1-7) of sheet, the dispatching command of waiting list dispatch circuit (1-6).Queue scheduling circuit (1-6) is dispatched the cell in the DDR memory outside the sheet, selects the formation of certain stream from numerous formations, and the grouping in the scheduling DDR memory is left.Cell counting circuit (1-3) is counted the cell among the DDR according to the stream number of cell, and each stream is all safeguarded a counter, enters the formation hour counter and adds one when a cell admits, and leaves the formation hour counter and subtracts one when a cell is scheduled.Free block management circuit (1-4) is responsible for the idle capacity among the outer DDR of statistics sheet, when a cell is entered formation by admittance, distribute a free block, and its number subtracts one; When a cell is scheduled when leaving formation, reclaim a free block, and its number adds one.Two parameters of current idle capacity in the outer DDR memory of the sheet that dynamic threshold early drop circuit (1-2) provides according to cell counting circuit (1-3) among the current cell number of this stream and the outer DDR of sheet that free block management circuit (1-4) provides are implemented admittance and are abandoned control cell.

We stipulate, with Q ⁱ(t) length of expression t moment i waiting list; With Q (t)=∑ _iQ ⁱ(t) the expression t moment all queue length summations, the i.e. size of occupied part in the buffer memory; The size of representing whole shared cache area with B; Use L _Min(t), L _Max(t) represent t to divide into groups to abandon the lower limit and the upper limit threshold of the queue length of control constantly.

When each grouping arrives formation i, calculate the average queue length L of t formation constantly i ⁱ _Avg(t) (W _qBe the formation weight of setting):

L i avg(t)＝(1-W q)L i avg(t old)+W qQ i(t)

(1)

Recomputate the upper and lower bound threshold value L that t divides into groups to abandon the queue length of control constantly _Min(t), L _Max(t) (β＞α):

L min(t)＝α(B-Q(t))

(2)

L _max(t)＝β(B-Q(t)) (3)

According to the L that calculates _Min(t), L _Max(t), carry out following judgement:

(1) if $L_{\mathrm{avg}}^i\left(t\right)\&le;L_{\min }\left(t\right),$ Do not do any control, receive the grouping that all arrives;

(2) if $L_{\min }\left(t\right)<L_{\mathrm{avg}}^i\left(t\right)<L_{\max }\left(t\right)$ The time, then calculate drop probability p _a, and with this probability dropping arrival grouping.(p _MaxBe the maximum drop probability of setting)

(3) if $L_{\mathrm{avg}}^i\left(t\right)\&GreaterEqual;L_{\max }\left(t\right),$ Then abandon whole groupings, c=0.

Below provide the false code of realization:

Initialization: L ⁱ _Avg(t)=0, c=-1;

Moment t, a certain grouping arrives input rank i:

Calculate L with formula (1) ⁱ _Avg(t);

Calculate L with formula (2), (3) _Min(t) and L _Max(t);

if $L_{\min }\left(t\right)<L_{\mathrm{avg}}^i\left(t\right)<L_{\max }\left(t\right)$

Calculate drop probability p with formula (4), (5) _a

With Probability p _aAbandon and reach grouping;

c＝0；

else if $L_{\mathrm{avg}}^i\left(t\right)\&GreaterEqual;L_{\max }\left(t\right)$

Abandon and arrive grouping;

c＝0；

else

c＝-1；

Consider that size is in the buffer area of B, the current A of a having only formation is in active state.Because the length of each formation is controlled in L _Max(t) about, the heap(ed) capacity that this moment, buffer area was occupied is at Q (t)=AL so _Max(t) about, the substitution formula can obtain in (3) $L_{\max }\left(t\right)=\frac{\mathrm{\&beta;<figure-callout\; id="1"\; label="B"\; filenames="C20051012636100161.png,C20051012636100162.png"\; state="\{\{state\}\}">B</figure-callout>}}{1+\mathrm{\&beta;A}},$ So the utilance of buffer area is $\mathrm{\&rho;}=\frac{\mathrm{\&beta;A}}{1+\mathrm{\&beta;A}}.$ As can be seen, the same with the RED algorithm from following formula, the present invention also always reserves the sub-fraction spatial cache, can handle sudden better.

When utilizing the hardware realization of High Speed, there are two difficulties: the one, grouping abandons control thresholding L _Min(t) and L _Max(t) calculating; The 2nd, the calculating of drop probability.The present invention just can utilize hardware to come realization of High Speed by algorithm is done following setting:

(1) whenever there being grouping to arrive, provide the average queue length of this stream by cell counting circuit (1-3), be designated as C;

(2) the big or small B of whole shared cache area is the size of DDR outside the sheet that is adopted;

(3) the big or small Q (t) of occupied part is provided by free block management circuit (1-4) in the buffer memory, and idle cache size is R among the note DDR;

(4) parameter alpha=0.5, β=1.0, the free buffer that then provides by free block management circuit (1-4) size R, L _Min(t)=and 0.5R, L _Max(t)=and R, wherein just can obtain grouping and abandon control thresholding L by simply moving to right one _Min(t).

Because abandoning is that a complete grouping is implemented, therefore, when first cell of grouping arrives, average queue length C and two threshold value L _Min(t), L _Max(t) compare, decision is the cell that abandons this grouping, and still the cell that will divide into groups writes the outer DDR memory of sheet.

In addition, if the strict drop probability that calculates, and according to the grouping that this probability random drop arrives, need complicated pseudo random number generative circuit, and a large amount of multiplyings is arranged, can take a large amount of FPGA resources, be unfavorable for using the hardware realization of High Speed.We can adopt as shown in Figure 3 piecewise function to approach and abandon curve, calculated the relation between sectional door limit value, residual capacity and the drop probability then in advance, during realization, only need by DDR residual capacity R that obtains from the free block administration module and the current queue length C that obtains this stream from the classified counting circuit, can table look-up by table 1 obtains packet dropping probability, periodically abandons the grouping of arrival then according to this drop probability.Such as, when the current queue length 0≤C that obtains from the classified counting circuit＜0.5R, the grouping of all arrival does not abandon, and all passes through DDR controller (1-5) and writes the outer DDR memory of sheet; When 0.5R≤C＜0.75R, this stream is every to be reached 8 groupings and just abandons a grouping.The piecewise function that adopts approaches and abandons curve method and periodically abandon rule, can be on FPGA realization of High Speed, the circuit working flow process is as shown in Figure 4.

The queue length C of table 1 residual capacity R, stream and the relation of packet dropping probability

Fragment number	The current queue length C	Drop probability	Abandon rule
					1	0≤C＜0.5R	0％	Do not abandon grouping
2	0.5R≤C＜0.75R	12.5％	Per 8 groupings abandon one
				3	0.75R≤C＜R	33.3％	Per 3 groupings abandon one
4	C≥R	100％	Abandon whole groupings

Shared buffer memory dynamic threshold early drop device based on the many formations of support of FPGA adopts hardware description language Verilog to realize on a slice FPGA, and experiment and test on the router cable fastener of being developed.Test macro is by the parallel port of PC, JTAG mouth by FPGA, FPGA on this ply-yarn drill downloads the HDL code, send specific I P grouping with tester to Target Board again, after the resume module on FPGA, by tester and eda tool the output result is added up and record, analyze this designed device correctness.

The tester of using in the test is the AX/4000 of Spirent company.AX/4000 is a kind of modular multiport test macro, can test multiple transmission technologys such as ATM, IP, frame relay and Ethernet simultaneously with the speed up to 10Gbps.The AX/4000 tester adopts modularized design, and main modular is made up of system control module, generator module, analyzer module and abundant interface module.Generator module provides IP source address and destination address, the multiple pattern of giving out a contract for a project; The stream information that analyzer module extracts automatically shows information such as each packet loss that flows, packet loss statistics in real time, and shows in modes such as tables of data, linear graph, histograms.The experiment of this patent produces specific stream with AX/4000, and the result is carried out statistics and analysis.

The eda tool of using in the development﹠ testing is mainly the Quartus software of altera corp, and Quartus software is finished writing, realize and downloading of Verilog code, and analyzes and the record timing waveform with Signal Tap wherein.

Shared buffer memory dynamic threshold early drop device based on the many formations of support of FPGA adopts the staged curve to approach the curve that abandons of RED, and periodically abandons the part grouping.The DDR residual capacity R that obtains by free block management circuit (1-4), provide the queue length C of stream and the relation of packet dropping probability can be represented by table 1 by cell counting circuit (1-3).Each section that will test the piecewise function curve based on the experiment of the shared buffer memory dynamic threshold early drop device of the many formations of support of FPGA.In the shared buffer memory dynamic threshold early drop device based on the many formations of support of FPGA, if queue scheduling circuit (1-6) does not advance scheduling, this device will experience each section that segmentation abandons curve, can in the Signal of Quartus Tap, set gradually the relative trigger value, just can write down and analysis waveform.

The test of first section curve: if queue scheduling circuit (1-6) normal consistency, this device is operated in first section that abandons curve, admits the grouping that arrives fully.In test, the tester AX/4000 pattern of giving out a contract for a project is Manually TriggeredBursts, and 100%BW gives out a contract for a project, and total number of giving out a contract for a project is 300000, sends 300000 groupings during each manual triggers, receives grouping after handling with tester AX/4000 again.As can be drawn from Table 2, this device is operated in when abandoning bent first section can correctly transmit grouping, can not abandon grouping.

Table 2 abandons the curve test result for first section

Sequence number	Fluxion	The bag number that sends	Bag is long	The bag number of receiving	Conclusion
							1	1	300,000	40	300,000	Correctly
2	1	300,000	1500	300,000	Correctly
						3	100	300,000	40	300,000	Correctly
4	100	300,000	1500	300,000	Correctly
						5	1000	300,000	40	300,000	Correctly
6	1000	300,000	1500	300,000	Correctly

The test of interlude: if queue scheduling circuit (1-6) is not dispatched, this device will experience each section that segmentation abandons curve, and the relative trigger value is set in Signal Tap successively, writes down its waveform.In test, it is 48 byte packet that tester AX/4000 selects length, and the pattern of giving out a contract for a project is periodic packets, 100%BW.In test, in the Signal of Quartus Tap, add following signal:

1.C4_slotcycle: the timeticks numeration of this device, count value is 0 ~ 15;

2.F_first_cell: the sign of first cell of grouping;

3.CON_discard_interval: every section counting upper limit that abandons curve, such as when 0.75R≤C＜R piecewise interval, per 3 groupings abandon one, then CON_discard_interval=3;

4.C4_discard: at every section cycle rate counter that abandons curve, be used to judge whether that this abandons this grouping, such as when 0.75R≤C＜R piecewise interval, per 3 groupings abandon one, C4_discard is 1 ~ 3 cycle count, when C4_discard=CON_discard_interval=3, abandon this grouping;

5.F_range_judge: judge that at every section cycle count that abandons curve when C4_discard=CON_discard_interval, arrive counting and go up in limited time, then F_range_judge=1 represents that this grouping will abandon;

6.F_IP_discard:IP grouping abandons sign, is 1 o'clock, abandons this grouping, the deration of signal is the width of IP grouping;

7.C19_Cellnum: the cell number of buffer memory in DDR of current stream, i.e. queue length C;

8.C19_Remain:DDR current remaining space, i.e. residual capacity R;

9.F_range_show:RED-DT the place abandons the indication of curved section;

In the Signal of Quartus Tap F_range_show being set is trigger condition, is followed successively by:

00: the first section, do not abandon grouping;

01: the second section, per 8 groupings abandon one;

10: the three sections, per 3 groupings abandon one;

11: the four sections, abandon whole groupings;

Adopt above-mentioned method of testing, obtain following result:

(1) trigger value that F_range_shown is set is 01, is operated in segmentation based on the shared buffer memory dynamic threshold early drop device of the many formations of support of FPGA and abandons second section of curve, and per 8 groupings abandon a grouping, test waveform such as Figure 11, shown in Figure 12.From Figure 11, Figure 12 as can be seen, when F_range_shown=01, C=172031, R=344063,0.5R≤C＜0.75R, this device is operated in segmentation and abandons second section of curve, per 8 groupings abandon a grouping, and when C4_discard=8, F_IP_discard and F_range_judge are 1, abandon this grouping, test is correct.

(2) trigger value that F_range_shown is set is 10, is operated in segmentation based on the shared buffer memory dynamic threshold early drop device of the many formations of support of FPGA and abandons the 3rd section of curve, and per 3 groupings abandon a grouping, test waveform such as Figure 13, shown in Figure 14.From Figure 13, Figure 14 as can be seen, when F_range_shown=10, C=22183, R=294911,0.75R≤C＜R, this device is operated in segmentation and abandons the 3rd section of curve, per 3 groupings abandon a grouping, and when C4_discard=3, F_IP_discard and F_range_judge are 1, abandon this grouping, test is correct.

(3) trigger value that F_range_shown is set is 11, is operated in segmentation based on the shared buffer memory dynamic threshold early drop device of the many formations of support of FPGA and abandons the 4th section of curve, abandons whole groupings, test waveform such as Figure 15, shown in Figure 16.From Figure 15, Figure 16 as can be seen, when F_range_shown=11, C=258047, R=258047, C 〉=R, this device are operated in segmentation and abandon the 4th section of curve, abandon whole grouping F_IP_discard and F_range_judge and be always 1, abandon this grouping, test is correct.

Claims (1)

1. support the shared buffer memory dynamic threshold early drop device of many formations, it is characterized in that, this device is realized with fpga chip, contain in this fpga chip: IP packet fragmentation circuit, free block management circuit, the outer double data rate memory controller of sheet, stream element count circuit, queue scheduling circuit and dynamic threshold early drop circuit, wherein:

The output of IP packet fragmentation circuit links to each other with the input of dynamic threshold early drop circuit, free block management circuit and dynamic threshold early drop circuit interconnection, outer double data rate memory controller of sheet and dynamic threshold early drop circuit interconnection, stream element count circuit and dynamic threshold early drop circuit interconnection, queue scheduling circuit dynamic threshold early drop circuit interconnection;

IP packet fragmentation circuit, this circuit is cut apart the elongated IP grouping that arrives by the stream element length of setting, obtain the stream unit of fixed length, represents that with cell described IP packet fragmentation circuit contains:

The 1st push-up storage is provided with IP grouping input;

Counter, the count signal input of this counter are read the FIFO terminal count output with described the 1st push-up storage and are linked to each other;

Splitter, this splitter have two inputs: an input links to each other with the IP data output end of described the 1st push-up storage, and another input of this splitter links to each other with the terminal count output of described counter;

IP header packet information register, the IP header packet information input of this register links to each other with the IP header packet information output of described splitter;

Stream unit header register is provided with stream unit input, and this input links to each other with the corresponding output end of described IP header packet information register;

Be provided with predetermined stream element length in the selector, the stream unit header information input terminal of described selector, IP data input pin link to each other with the IP data output of described stream unit header register, splitter respectively successively;

Stream cell data register, the stream cell data input of this register links to each other with the corresponding output end of described selector;

The 2nd push-up storage, the stream cell data input of this memory links to each other with the corresponding output end of described stream cell data register, and the stream unit that obtains is cut apart in this push-up storage output;

Stream element count circuit, contain: forward-backward counter and magnetic RAM, described forward-backward counter is provided with: the index signal input is admitted in the stream unit, the stream unit of the outer double data rate memory of receiving sheet; Stream cell scheduling index signal input receives the scheduling signals that flows the unit; Previous stream number of unit input; Described magnetic RAM is represented with MRAM, is provided with: the stream number input of stream unit; Current stream number of unit input, this input links to each other with the current stream number of unit output of described forward-backward counter; This MRAM also has: before flowed the unit number output, this output links to each other with the previous stream number of unit input of described forward-backward counter; This forward-backward counter adds the formation hour counter and adds 1 being admitted when a stream unit, is left the formation hour counter and subtracts 1 when a stream unit accesses, and also is provided with the value W of formation weight in this forward-backward counter _q, be calculated as follows t average queue length L constantly ⁱ _Avg(t) output:

L ⁱ _ang(t)＝(1-W _q)L ⁱ _avg(t _old)+W _qQ ⁱ(t)

Wherein, L ⁱ _Avg(t _Old) be the t previous stream unit number of formation i constantly;

Q ⁱ(t) be the stream number of unit that t formation constantly i arrives, this forward-backward counter is provided with a Q (t) output simultaneously, and Q (t) is meant t all queue length summations constantly, Q (t)=∑ _iQ ⁱ(t);

The free block management circuit, this circuit is a free block forward-backward counter, be provided with the capacity of the outer double data rate memory of sheet in this counter, this forward-backward counter also is provided with the stream unit and admits index signal input and stream cell scheduling index signal input, when the adding formation is admitted in a stream unit, when perhaps a stream unit is accessed formation, this forward-backward counter subtracts 1 or add 1 to the idle capacity of the outer double data rate memory of sheet set respectively successively, exports the idle capacity of this sheet double data rate memory in view of the above;

The controller of the outer double data rate memory of sheet, this controller is connecting a described outer double data rate memory, and the access visit of this memory is controlled;

Queue scheduling circuit, this circuit are provided with the queue scheduling signal output part that the stream unit in the described outer double data rate memory is read in scheduling;

The dynamic threshold early drop circuit, this circuit is provided with: L ⁱ _Avg(t) register, abandon the lower threshold L of the queue length of control _Min(t) first arithmetic device of computing, abandon the upper limit threshold L of the queue length of control _Max(t) second arithmetic device of computing, comparator and abandon the 3rd arithmetic unit of control, wherein,

First arithmetic device is built-in with L _Min(t) redundancy is represented with α, also is equipped with the capacity of described outer double data rate memory, represents with B, and unit is the stream element length, and this arithmetic unit receives Q (t) signal and is calculated as follows L by Q (t) signal input part _Min(t):

L _min(t)＝α(B-Q(t))；

Second arithmetic device is built-in with L _Max(t) redundancy is represented with β, and β＞α also is equipped with the capacity of described outer double data rate memory, represents with B, and unit is the stream element length, and this arithmetic unit is by Q (t) signal input part reception Q (t) signal and be calculated as follows L _Max(t):

L _max(t)＝β(B-Q(t))

Q (t) output of the forward-backward counter in above-mentioned each Q (t) signal input part and the described stream element count circuit links to each other;

Comparator is built-in with maximum drop probability p _Max, and this comparator is provided with: L ⁱ _AvgThe current stream number of unit output of the forward-backward counter in (t) signal input part, this input and described stream element count circuit links to each other, and this comparator also is provided with L _Min(t) signal and L _Max(t) signal totally two inputs, this comparator is receiving L ⁱ _Avg(t), L _Min(t), L _Max(t) behind the signal, carry out according to the following steps successively:

Step 1: if $L_{\mathrm{avg}}^i\left(t\right)\&le;L_{\min }\left(t\right),$ Then receive the grouping that all arrives, and all stream unit of output arrival, the value of abandoning is 0;

Step 2: if $L_{\min }\left(t\right)<L_{\mathrm{avg}}^i\left(t\right)<L_{\max }\left(t\right)$ The time, then calculate drop probability p _a, and arrive grouping with this probability dropping:

$p_b=p_{\max }\frac{({L^i}_{\mathrm{avg}}\left(t\right)-L_{\min }\left(t\right))}{(L_{\max }\left(t\right)-L_{\min }\left(t\right))}$

p _a=p _b/ (1-cp _b), establish c=-1;

Step 3: if $L_{\mathrm{avg}}^i\left(t\right)\&GreaterEqual;L_{\max }\left(t\right),$ Then abandon whole groupings, c=0;

The 3rd arithmetic unit, this arithmetic unit abandons sign by the stream unit of described comparator output, and promptly the value of described c is calculated as follows drop probability p _a:

C=-1, then p _a=p _b/ (1+p _b), the grouping that arrives is divided in the discarded part;

C=0, then p _a=p _b, abandon the grouping of all arrival.

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