CN100403530C - Semiconductor packing process - Google Patents
Semiconductor packing process Download PDFInfo
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- CN100403530C CN100403530C CNB2005100679193A CN200510067919A CN100403530C CN 100403530 C CN100403530 C CN 100403530C CN B2005100679193 A CNB2005100679193 A CN B2005100679193A CN 200510067919 A CN200510067919 A CN 200510067919A CN 100403530 C CN100403530 C CN 100403530C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
The present invention relates to a semiconductor packing process which comprises the process of offering a conducting baseboard, wherein the conducting baseboard has a first surface and a second surface which are opposite to each other. Part of the conducting baseboard is recessed from the first surface to form a conducting pattern; the conducting pattern comprises a plurality of conducting wires; an electronic component is arranged on the conducting pattern; the electronic component is electrically connected with the conducting wires; a mask layer which is in patterns is formed on a second surface of the conducting baseboard; the part which is covered is positioned the conducting baseboard arranged on the opposite side of the conducting wires. The conducting baseboard which is not covered by the mask layer is removed to hollow the part; the conducting wires which are reserved at the opposite side are respectively form a connection pad; the connection pads are respectively smaller than the corresponding conducting wires; an encapsulation colloid is formed for covering the electrical connection between the electronic component and the conducting wires.
Description
Technical field
The present invention relates to a kind of semiconductor packing process, but particularly relate to a kind of semiconductor packing process of reduced point area.
Background technology
With lead frame as the packaging body of substrate four limit flat non-connection pins (quad flat no lead for example; QFN) packaging body, its technology with surface adhering is usually excessive because of the contact area on the lead frame when being assembled on the printed circuit, and the amount control of tin cream is difficult for, and take place tin cream to overflow between above-mentioned contact and the defective of bridge joint takes place.The then necessary heavy industry (rework) of the slight person of situation; The situation severe patient then makes product scrap, and causes the serious loss of output and productive rate.Yet, be subject to the processing procedure of lead frame itself, even it is the size of above-mentioned contact is contracted to the limit of its processing procedure,, still quite limited to the improvement of the problems referred to above.
This shows that above-mentioned conventional semiconductor packages processing procedure obviously still has inconvenience and defective, and demands urgently further being improved in method and use.In order to solve the problem that semiconductor packing process exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and conventional method does not have appropriate method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new semiconductor packing process, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned conventional semiconductor packages processing procedure exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new semiconductor packing process, can improve general conventional semiconductor packages processing procedure, make it have more practicality.Through constantly research, design, and after studying repeatedly and improving, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective that the conventional semiconductor packages processing procedure exists, and a kind of new semiconductor packing process is provided, technical problem to be solved is to make it can reduce the contact area of packaging body in fact according to process requirement.Thereby when being assembled to the packaging body of semiconductor packing process manufacturing of the present invention on the printed circuit, just can reducing the incidence of bridge joint between contact, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor packing process according to the present invention proposes comprises: an electrically-conductive backing plate is provided, has opposite first surface and second surface; From the subregion of the above-mentioned electrically-conductive backing plate of above-mentioned first surface etchback, and form a conductive pattern, above-mentioned conductive pattern comprises a plurality of leads; Provide an electronic component on above-mentioned conductive pattern, and between above-mentioned electronic component and above-mentioned lead, form electric connection; Form a packing colloid and cover electric connection between this electronic component and those leads; At the second surface of above-mentioned electrically-conductive backing plate, form a patterned cover curtain layer, the cover part is positioned at the above-mentioned electrically-conductive backing plate of above-mentioned lead opposition side; Remove the above-mentioned electrically-conductive backing plate that is not covered,, and make the above-mentioned electrically-conductive backing plate of staying above-mentioned lead opposition side respectively become a connection gasket, respectively less than the above-mentioned lead of correspondence with the above-mentioned subregion of hollow out by above-mentioned cover curtain layer; Form a packaging body and comprise this packing colloid, this electronic component, this conductive pattern, and those connection gaskets and and form a welding resisting layer between those connection gaskets.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
Aforesaid semiconductor packing process, it more is included in and forms before or after this packing colloid, removes this cover curtain layer.
Aforesaid semiconductor packing process wherein more comprised a step of cutting before or after removing this cover curtain layer, separate this packaging body.
Aforesaid semiconductor packing process, wherein said packing colloid more is formed between those connection gaskets, and substantially with those connection gasket coplines or protrude from those connection gaskets.
Aforesaid semiconductor packing process, wherein said welding resisting layer are substantially with those connection gasket coplines or protrude from those connection gaskets.
Aforesaid semiconductor packing process, wherein said packing colloid are to be formed to remove not before or after this electrically-conductive backing plate that is covered by this cover curtain layer.
Aforesaid semiconductor packing process, wherein said conductive pattern comprises that more a cooling pad is between those leads, this electronic component more with between this cooling pad forms thermal conductivity and is connected, and this patterned cover curtain layer more cover part is positioned at this second surface of this cooling pad opposition side.
Aforesaid semiconductor packing process, it comprises that more formation one welding resisting layer is between those connection gaskets and this cooling pad.
Aforesaid semiconductor packing process, wherein said welding resisting layer are substantially with those connection gasket coplines or protrude from those connection gaskets.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor packing process according to the present invention proposes comprises: an electrically-conductive backing plate is provided, has opposite first surface and second surface; From the subregion of the above-mentioned electrically-conductive backing plate of above-mentioned first surface etchback, and form a conductive pattern, above-mentioned conductive pattern comprise a plurality of leads, and a cooling pad between above-mentioned lead; Provide an electronic component on above-mentioned conductive pattern, and between above-mentioned electronic component and above-mentioned lead, form electrically connect, the formation thermal conductivity is connected between above-mentioned electronic component and the above-mentioned cooling pad; Form a packing colloid and cover electric connection between this electronic component and those leads, this cooling pad; At the second surface of above-mentioned electrically-conductive backing plate, form a patterned cover curtain layer, the cover part is positioned at the above-mentioned electrically-conductive backing plate of above-mentioned lead and above-mentioned cooling pad opposition side; Remove not the above-mentioned electrically-conductive backing plate that is covered by above-mentioned patterned cover curtain layer, make the above-mentioned electrically-conductive backing plate of staying above-mentioned lead and above-mentioned cooling pad opposition side respectively become a connection gasket, respectively less than the above-mentioned lead and the above-mentioned cooling pad of correspondence; Form a packaging body and comprise above-mentioned packing colloid, above-mentioned electronic component, above-mentioned conductive pattern, and above-mentioned connection gasket and form a welding resisting layer between those connection gaskets.
The object of the invention to solve the technical problems also adopts following technical measures further to realize.
Aforesaid semiconductor packing process, it more is included in and forms before or after this packing colloid, removes this cover curtain layer.
Aforesaid semiconductor packing process wherein more comprised a step of cutting before or after removing this cover curtain layer, separate this packaging body.
Aforesaid semiconductor packing process, wherein said packing colloid more is formed between those connection gaskets, and substantially with those connection gasket coplines or protrude from those connection gaskets.
Aforesaid semiconductor packing process, wherein said welding resisting layer are substantially with those connection gasket coplines or protrude from those connection gaskets.
Aforesaid semiconductor packing process, wherein said first substrate is identical or different with the material of this second substrate.
Aforesaid semiconductor packing process, wherein said packing colloid are to be formed to remove not before or after this electrically-conductive backing plate that is covered by this cover curtain layer.
Aforesaid semiconductor packing process, it comprises that more formation one welding resisting layer is between those connection gaskets and this cooling pad.
Aforesaid semiconductor packing process, wherein said welding resisting layer are substantially with those connection gasket coplines or protrude from those connection gaskets.
Feature of the present invention is on the circuit of lead frame, form a connection gasket as the contact on the packaging body, and visual process requirement is controlled the size of above-mentioned connection gasket.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, the semiconductor packing process that the present invention is special can reduce the contact area of packaging body in fact according to process requirement.Thereby when being assembled to the packaging body of semiconductor packing process manufacturing of the present invention on the printed circuit, just can reduce the incidence of bridge joint between contact.It has above-mentioned many advantages and practical value, and in class methods, do not see have similar design to publish or use and really genus innovation, no matter it is all having bigger improvement on method or on the function, have large improvement technically, and produced handy and practical effect, and have the multinomial effect of enhancement than the conventional semiconductor packages processing procedure, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A～1H is depicted as a series of profile, is the flow process that shows the semiconductor packing process of first embodiment of the invention.
Fig. 2 A～2D is depicted as a series of profile, is the flow process that shows the semiconductor packing process of second embodiment of the invention.
Figure 3 shows that a profile, is an example that shows the formed packaging body of semiconductor packing process of preferred embodiment of the present invention.
Fig. 4 A～4B is depicted as a series of profile, is another example that shows the semiconductor packing process of first embodiment of the invention.
10: electronic component 12: conductive projection
20: electronic component 22: conductive projection
24: conductive projection 100: electrically-conductive backing plate
100a: first surface 100b: second surface
101: conductive pattern 101 ': conductive pattern
101a: lead 101b: lead
101c: cooling pad 102: connection gasket
106: the second substrates of 105: the first substrates
120: packing colloid 130: patterned cover curtain layer
140,140 ': welding resisting layer 150: packing colloid
160: packing colloid
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of semiconductor packing process, method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Figure 1A～1H is depicted as a series of profile, is the flow process that shows the semiconductor packing process of first embodiment of the invention.
At first, see also shown in Figure 1A, an electrically-conductive backing plate 100 is provided, be preferably copper or aluminium.Electrically-conductive backing plate 100 has opposite first surface 100a and second surface 100b.
Next, see also shown in Figure 1B, from the subregion of first surface 100a etchback electrically-conductive backing plate 100, but hollow out electrically-conductive backing plate 100 not, and form conductive pattern 101.Conductive pattern 101 has a plurality of leads, is representative with lead 101a, 101b in the present embodiment.The thickness of etchback electrically-conductive backing plate 100 wherein can by the etched time of control, be controlled the amount of etchback electrically-conductive backing plate 100 thickness by methods such as for example lithographies, and hollow out electrically-conductive backing plate 100 not.
In addition, see also shown in Fig. 4 A～4B, in another embodiment, still can shown in Fig. 4 A, provide first substrate 105 and second substrate 106, both are pressed together formation have opposite first surface 100a and the electrically-conductive backing plate 100 of second surface 100b.Next, shown in Fig. 4 B,, and form aforesaid conductive pattern 101 for another example from the subregion of first surface 100a etching first substrate 105.First substrate 105 and second substrate 106 are preferably copper or aluminium, and both materials can be identical or different.
Next, see also shown in Fig. 1 C, the step shown in Figure 1B or Fig. 4 B that continues provides an electronic component 10 on conductive pattern 101, and forms electric connection between electronic component 10 and lead 101a, 101b.Electronic component 10 can be semiconductor wafer, passive device, the semiconductor wafer that has encapsulated, the passive device that has encapsulated or above-mentioned combination.And in the present embodiment, when electronic component 10 is semiconductor wafer, be to use the chip bonding technology, electronic component 10 is in the downward mode of active surface, by conductive projection 12, form the electric connection between itself and lead 101a, the 101b, yet be familiar with for example wire bonds of joining technique that this skill person can also select other for use.When electronic component 10 during for passive device, the semiconductor wafer that has encapsulated, the passive device that has encapsulated or above-mentioned combination, then be to use the surface adhering technology, by conductive projection 12, form the electric connection between electronic component 10 and lead 101a, the 101b.
Next see also shown in Fig. 1 D, form the electric connection (being the conductive projection 12 of present embodiment) between a packing colloid 120 coated electric components 10 and lead 101a, the 101b.The formation of packing colloid 120 can be used for example technology of ejection formation, some glue or primer filling (underfill).Fig. 1 D is depicted as the result who uses ejection formation or dispensing technology, the electric connection between overlay electronic element 10 and lead 101a, 101b, can also be as shown in the figure, and complete coated electric components 10; Can also expose portions of electronics element 10, in order to heat radiation.In addition, can also use the technology of primer filling, packing colloid 120 is formed under the electronic component 10, and cover electric connection between itself and lead 101a, the 101b.
Next see also shown in Fig. 1 E, at the second surface 100b of electrically-conductive backing plate 100, form a patterned cover curtain layer 130, the cover part is positioned at the electrically-conductive backing plate 100 of lead 101a, 101b opposition side.And in another embodiment, be to form patterned cover curtain layer 130, the cover part is positioned at second substrate 106 (seeing also shown in Fig. 4 B) of lead 101a, 101b opposition side.Patterned cover curtain layer 130 can be resistance agent, dry film or a welding resisting layer, can be after (or second substrate 106) form cover curtain layer 130 comprehensively on the second surface 100b of electrically-conductive backing plate 100, and it is graphical with it for example to re-use exposure imaging or lithography method.
Next see also shown in Fig. 1 F, remove the electrically-conductive backing plate 100 that not graphical cover curtain layer 130 covers, make the electrically-conductive backing plate 100 (or second substrate 106) of staying lead 101a, 101b opposition side respectively become a connection gasket 102, respectively less than lead 101a, the 101b of correspondence.Removing of above-mentioned partially conductive substrate 100 (or second substrate 106) can be that etch mask is finished with patterned cover curtain layer 130 by for example wet etch method or dry ecthing method.The size of connection gasket 102 is to be its process requirement by being familiar with this skill person, reaches by the figure of adjusting patterned cover curtain layer 130.
By, ensuing additional step, can further reduce the incidence of bridge joint between above-mentioned contact.
Next, shown in Fig. 1 G, can remove patterned cover curtain layer 130 earlier, then between each connection gasket 102, form a welding resisting layer 140, at this moment welding resisting layer 140 cardinal principle and each connection gasket 102 copline.And see also shown in Fig. 1 H, if form earlier a welding resisting layer 140 ' between each connection gasket 102, when then removing patterned cover curtain layer 130, welding resisting layer 140 ' then protrudes from each connection gasket 102.Above-mentioned two examples can decide according to its demand by being familiar with this skill person.In addition, can also form another packing colloid (not shown) and replace welding resisting layer 140 or 140 '.
In addition, in order to save the processing procedure cost and to increase output, be familiar with this skill person when the step shown in Figure 1B, can be on electrically-conductive backing plate 100, once form plural conductive figure 101, and after the arbitrary step shown in Figure 1B～1G, add one again and separate for example step of cutting, with each conductive pattern is unit, isolates independent packaging units or packaging body.
Fig. 2 A～2D is a series of profile, is the flow process that shows the semiconductor packing process of second embodiment of the invention.
See also shown in Fig. 2 A, be connected in the step shown in Fig. 1 C, at the second surface 100b of electrically-conductive backing plate 100, form a patterned cover curtain layer 130, the cover part is positioned at the electrically-conductive backing plate 100 of lead 101a, 101b opposition side.And in another embodiment, be to form patterned cover curtain layer 130, the cover part is positioned at second substrate 106 (seeing also shown in Fig. 4 B) of lead 101a, 101b opposition side.Identical with described in first embodiment then about patterned cover curtain layer 130, just repeated description not.
Next, see also shown in Fig. 2 B, remove the electrically-conductive backing plate 100 (or second substrate 106) that not graphical cover curtain layer 130 covers, make the electrically-conductive backing plate 100 of staying lead 101a, 101b opposition side respectively become a connection gasket 102, respectively less than lead 101a, the 101b of correspondence.It is narrated in more detail, also is equivalent to the content shown in Fig. 1 F.
In addition; being familiar with this skill person also can be before the step shown in Fig. 1 C; form another cover curtain layer (not shown) and cover conductive pattern 101 electrically-conductive backing plate 100 in addition; can be in the step shown in Fig. 2 B; when removing the electrically-conductive backing plate 100 of not graphical cover curtain layer 130 coverings; provide extra protection to electronic component 10 and conductive projection 12, reduce the probability that electronic component 10 and conductive projection 12 are damaged in said process.
Next, shown in Fig. 2 C, can remove patterned cover curtain layer 130 earlier, form the electric connection (being the conductive projection 12 of present embodiment) between a packing colloid 150 coated electric components 10 and lead 101a, the 101b again.The formation of packing colloid 150 can be used for example technology of ejection formation, some glue or primer filling (underfill).Fig. 2 C is depicted as the result who uses ejection formation or dispensing technology, the electric connection between overlay electronic element 10 and lead 101a, 101b, can also be as shown in the figure, and complete coated electric components 10; Can also expose portions of electronics element 10, in order to heat radiation.In addition, can also use the technology of primer filling, packing colloid 150 is formed under the electronic component 10, and cover electric connection between itself and lead 101a, the 101b.Packing colloid 150 can also more be formed between each connection gasket 102, this moment packing colloid 120 be substantially with each connection gasket 102 copline.
See also shown in Fig. 2 D, be connected in Fig. 2 B, if form a packing colloid 160 earlier between each connection gasket 102, the electric connection between coated electric components 10 and lead 101a, the 101b (being the conductive projection 12 of present embodiment) then removes patterned cover curtain layer 130.Associated description about packing colloid 160 is then roughly the same with the packing colloid 160 of Fig. 2 C.If yet when more being formed at packing colloid 160 between each connection gasket 102, this moment, packing colloid 120 was to protrude from each connection gasket 102.
In addition, as shown in Figure 3, being familiar with this skill person can also with identical method, form the conductive pattern 101 that a conductive pattern 101 ' replaces Figure 1B or 4B in the step shown in Figure 1B or the 4B.Conductive pattern 101 ' has a plurality of lead 101a, 101b and a cooling pad 101c between lead 101a, 101b.Other detailed descriptions of relevant conductive pattern 101 ' all are equivalent to aforesaid conductive pattern 101, are just omitted at this.
Therefore, in the step shown in Fig. 1 C, then replace electronic components 10, be placed on the conductive pattern 101 ' among Fig. 3, and between electronic component 20 and lead 101a, 101b, form electric connection, be formed with thermal conductivity between this electronic component 20 and the cooling pad 101c and be connected with electronic component 20.In Fig. 3, conductive projection 22 is between electronic component 20 and lead 101a, 101b and constitute to electrically connect, and conductive projection 24 is between between electronic component 20 and the cooling pad 101c and the formation thermal conductivity is connected.Other detailed descriptions about electronic component 20 all are equivalent to aforesaid electronic component 10, are just omitted at this.
In the step shown in Fig. 1 E or the 2A, patterned cover curtain layer 130 is except the cover part is positioned at the electrically-conductive backing plate 100 of lead 101a, 101b opposition side, and more the cover part is positioned at the electrically-conductive backing plate 100 of cooling pad 101c opposition side.And in the step shown in Fig. 1 F or the 2B, remove the electrically-conductive backing plate 100 that not graphical cover curtain layer 130 covers, make the electrically-conductive backing plate 100 of staying lead 101a, 101b and cooling pad 101c opposition side respectively become a connection gasket 102, respectively less than lead 101a, 101b and the cooling pad 101c of correspondence.
Other can finish encapsulating structure shown in Figure 3 by the equivalent step of Fig. 1 D, 1G or 1H; Or, replace packing colloid shown in Figure 3 120 and welding resisting layer 140 with packing colloid 150 or 160 by the equivalent step of Fig. 2 C, 2D.
As mentioned above, the present invention is on the circuit of lead frame, form a connection gasket as the contact on the packaging body, and visual process requirement is controlled the size of above-mentioned connection gasket, when being assembled to the packaging body of semiconductor packing process manufacturing of the present invention on the printed circuit, just can reduce the incidence of bridge joint between contact, be the purpose of reaching the invention described above.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1. a semiconductor packing process is characterized in that it may further comprise the steps;
One electrically-conductive backing plate is provided, has opposite first surface and second surface;
From the subregion of this this electrically-conductive backing plate of first surface etchback, and form a conductive pattern, this conductive pattern comprises a plurality of leads;
Provide an electronic component on this conductive pattern, and between this electronic component and those leads, form electric connection;
Form a packing colloid and cover electric connection between this electronic component and those leads;
At the second surface of this electrically-conductive backing plate, form a patterned cover curtain layer, the cover part is positioned at this electrically-conductive backing plate of those lead opposition sides;
Remove this electrically-conductive backing plate that is not covered,, and make this electrically-conductive backing plate of staying those lead opposition sides respectively become a connection gasket, respectively less than those leads of correspondence with this subregion of hollow out by this cover curtain layer;
Form a packaging body comprise this packing colloid, this electronic component, this conductive pattern, with those connection gaskets and
Form a welding resisting layer between those connection gaskets.
2. semiconductor packing process according to claim 1 is characterized in that it more is included in before or after this packing colloid of formation, removes this cover curtain layer.
3. semiconductor packing process according to claim 2 is characterized in that wherein more comprising a step of cutting before or after removing this cover curtain layer, separate this packaging body.
4. semiconductor packing process according to claim 1 is characterized in that wherein said packing colloid more is formed between those connection gaskets, and substantially with those connection gasket coplines or protrude from those connection gaskets.
5. semiconductor packing process according to claim 1 is characterized in that wherein said welding resisting layer is substantially with those connection gasket coplines or protrude from those connection gaskets.
6. semiconductor packing process according to claim 1 is characterized in that wherein said packing colloid is to be formed to remove not before or after this electrically-conductive backing plate that is covered by this cover curtain layer.
7. semiconductor packing process according to claim 1, it is characterized in that wherein said conductive pattern comprises that more a cooling pad is between those leads, this electronic component more with between this cooling pad forms thermal conductivity and is connected, and this patterned cover curtain layer more cover part is positioned at this second surface of this cooling pad opposition side.
8. semiconductor packing process according to claim 7 is characterized in that it comprises that more formation one welding resisting layer is between those connection gaskets and this cooling pad.
9. semiconductor packing process according to claim 8 is characterized in that wherein said welding resisting layer is substantially with those connection gasket coplines or protrude from those connection gaskets.
10. semiconductor packing process is characterized in that it may further comprise the steps:
Provide first substrate and second substrate to be pressed into an electrically-conductive backing plate;
The subregion of this first substrate of etching, and form a conductive pattern, this conductive pattern comprises that a plurality of leads and a cooling pad are between above-mentioned lead;
Provide an electronic component on this conductive pattern, and form to electrically connect between this electronic component and those leads, this electronic component more with between this cooling pad forms thermal conductivity and is connected;
Form a packing colloid and cover electric connection between this electronic component and those leads, this cooling pad;
Form a patterned cover curtain layer, the cover part is positioned at this second substrate of those lead opposition sides;
Remove this second substrate that is not covered,, and make this second substrate of staying those leads and this cooling pad opposition side respectively become a connection gasket, respectively less than those leads and this cooling pad of correspondence with this subregion of hollow out by this cover curtain layer;
Form a packaging body comprise this packing colloid, this electronic component, this conductive pattern, with those connection gaskets; And
Form a welding resisting layer between those connection gaskets.
11. semiconductor packing process according to claim 10 is characterized in that it more is included in before or after this packing colloid of formation, removes this cover curtain layer.
12. semiconductor packing process according to claim 11 is characterized in that wherein more comprising a step of cutting before or after removing this cover curtain layer, separate this packaging body.
13. semiconductor packing process according to claim 10 is characterized in that wherein said packing colloid more is formed between those connection gaskets, and substantially with those connection gasket coplines or protrude from those connection gaskets.
14. semiconductor packing process according to claim 11 is characterized in that wherein said welding resisting layer is substantially with those connection gasket coplines or protrude from those connection gaskets.
15. semiconductor packing process according to claim 10 is characterized in that wherein said first substrate is identical or different with the material of this second substrate.
16. semiconductor packing process according to claim 10 is characterized in that wherein said packing colloid is to be formed to remove not before or after this electrically-conductive backing plate that is covered by this cover curtain layer.
17. semiconductor packing process according to claim 16 is characterized in that it comprises that more formation one welding resisting layer is between those connection gaskets and this cooling pad.
18. semiconductor packing process according to claim 17 is characterized in that wherein said welding resisting layer is substantially with those connection gasket coplines or protrude from those connection gaskets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100679193A CN100403530C (en) | 2005-04-28 | 2005-04-28 | Semiconductor packing process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100679193A CN100403530C (en) | 2005-04-28 | 2005-04-28 | Semiconductor packing process |
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|---|---|
| CN1855460A CN1855460A (en) | 2006-11-01 |
| CN100403530C true CN100403530C (en) | 2008-07-16 |
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| CNB2005100679193A Active CN100403530C (en) | 2005-04-28 | 2005-04-28 | Semiconductor packing process |
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| CN101546739B (en) * | 2008-03-28 | 2010-12-15 | 宏齐科技股份有限公司 | Chip packaging structure reaching electrical connection without routing and method for manufacturing same |
Citations (3)
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|---|---|---|---|---|
| CN1315823A (en) * | 2000-03-08 | 2001-10-03 | 三洋电机株式会社 | Method for manufacturing circuit device and circuit device |
| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
| US20030207498A1 (en) * | 2002-04-29 | 2003-11-06 | Shafidul Islam | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
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2005
- 2005-04-28 CN CNB2005100679193A patent/CN100403530C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
| CN1315823A (en) * | 2000-03-08 | 2001-10-03 | 三洋电机株式会社 | Method for manufacturing circuit device and circuit device |
| US20030207498A1 (en) * | 2002-04-29 | 2003-11-06 | Shafidul Islam | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
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| CN1855460A (en) | 2006-11-01 |
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