CN100401510C - 半导体装置、半导体主体及其制造方法 - Google Patents

半导体装置、半导体主体及其制造方法 Download PDF

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CN100401510C
CN100401510C CNB2004800061014A CN200480006101A CN100401510C CN 100401510 C CN100401510 C CN 100401510C CN B2004800061014 A CNB2004800061014 A CN B2004800061014A CN 200480006101 A CN200480006101 A CN 200480006101A CN 100401510 C CN100401510 C CN 100401510C
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electrical connection
semiconductor body
semiconductor
district
power supply
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CN1757110A (zh
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J·A·A·登奥登
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Sheng Investment Co ltd
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Koninklijke Philips Electronics NV
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    • H01L2924/3011—Impedance

Abstract

本发明涉及包含半导体主体(11)的半导体装置(10)，在该半导体主体中形成了IC且该半导体主体在其表面上具有多个用于IC的连接区(1)，包括至少两个用于电源连接的连接区(1A)，半导体主体(11)的下侧设有多个另外的连接区(2)，这些另外的连接区域(2)通过电连接(3)连接到连接区(1)，电连接(3)位于半导体主体(11)的侧面上且与其电绝缘，半导体主体(11)粘附到引线框(4)并在框架(4)的引线(4A)和连接区(1)之间形成导线连接(5)。根据本发明，电连接(3)包含多个平行的间距规则的条形导体(3A)，用于电源连接的连接区(1A)中的每一个均通过两个或者多个所述条形导体(3A)连接到另外的连接区(2)，该另外的连接区(2)直接连接到框架(4)的引线(4B)，而连接区域的其余部分(1B)通过导线连接(5)直接连接到引线(4)。该装置(10)具有非常稳定的电源电压和优良的高频性能，而电源电流可以非常大。本发明还包含适用于该装置(10)中的半导体主体(11)及该装置(10)的制作方法。

Description

半导体装置、半导体主体及其制造方法
技术领域
本发明涉及包含半导体主体的半导体装置，该半导体主体具有衬底和半导体区域，该半导体主体含有多个集成电路形式的半导体元件，该半导体主体的表面设有多个电连接区，包括至少两个用于电源连接的电连接区，与该表面相对的半导体主体的一侧设有多个另外的电连接区，该另外的电连接区通过电连接连接到位于该半导体主体表面上的电连接区，该电连接位于与该表面成一角度的该半导体主体的侧面上并与该侧面电绝缘，并且该半导体主体粘附到一引线框，且另外的电连接形成于形成引线框一部分的第一连接导体和电连接区之间。优选为该装置提供合成树脂密封，该装置构成一种重要的电子模块。本发明还涉及可以适当地用于该装置中的半导体主体以及该装置的制造方法。
背景技术
由日本专利说明书JP-A-08-255810已知开篇段落中所述类型的半导体装置，该专利申请于1996年10月1以上述序号公开，在所述文件(见图3)中，所示的连接导体框，通常称为引线框，其上粘附了半导体IC(集成电路)，特别是具有很高集成度的IC。连接区位于其上侧，其中两个连接区用于电源连接，另外的连接区位于其下侧面，这些连接区域通过在IC的侧面上延伸的电连接而互连。在IC和形成引线框一部分的连接导体(即所谓的引线)之间形成导线互连。考虑到高度集成，IC上的导线连接(见图4)仅位于IC的下侧上的另外连接导体上，或者位于IC的侧面上的电连接上。由此，IC的上表面可以完全用于形成有源半导体元件。
已知装置的缺点在于，对于工作于越来越大的电源电流和越来越高的频率的未来IC而言，该装置适用性稍差。
发明内容
因此本发明的目标是提供在开篇段落中所述类型的半导体装置，该装置结合了高的集成度、低工作电压和极好的高频行为。
为实现该目标，开篇段落中所述类型的装置的特征在于，电连接包含多个间距规则的平行的条形导体，且用于电源连接的电连接区通过两个或者多个所述条形导体分别连接到另外的电连接区，该另外的电连接区直接连接到形成引线框一部分的第二连接导体，而其它电连接区通过所述另外的电连接直接连接到形成引线框一部分的第一连接导体。本发明首先是基于这样的认识：未来IC的电源电流将大幅增大，达到甚至高于100A的值。本发明另外还基于这样的认识：越来越大的电源电流使得极难稳定半导体主体上的电源电压。这一问题随着电源电压的减小而增大，这是目前的趋势，导线连接和电源连接区域之间的阻抗导致电源电压的DC(直流)偏差。因此，IO(输入输出)噪声容限降低，并出现附加的功率消耗。由于更高的动态阻抗所致的电源电压振荡引起信号完整性的进一步降低。通过IC的侧面将电源连接连接到IC下侧上的另外的连接导体，可以容易地在用于电源连接的连接区域和形成引线框一部分的连接导体之间形成直接电连接。由此，根据本发明的装置中排除了与导线连接相关的(动态)阻抗问题。此外，电源连接的自感应也非常小，使得外部AC(交流)退耦-通过电容连接到IC-对IC的电源具有更佳的影响。
在IC的侧面上使用两个或者多个、优选多个条形导体以形成相关连接区和相关另外连接区之间的连接，可允许非常高的电源电流而不存在上述问题。此外，IC侧面上条形导体的“斑马纹”图案的重要附加的及令人惊奇的优点在于，可以获得与连接区的位置相关的布局自由度。毕竟，这些条形导体可以置于半导体主体边缘附近的任何位置，每次仍然与(很)多个条形导体接触，且不与连接到或者将连接到相邻连接区的条形导体短路。另一方面，借助该“斑马纹”图案，可以排除由于大电流流过电连接在其内形成太大的机械应力及相关热耗散。
在根据本发明的半导体装置的优选实施例中，该半导体装置因此包含大量用于电源连接的电连接区，每个电连接区分别向集成电路供应电源电流的一部分，且这些电连接区位于半导体主体表面的边缘，并通过多个所述条形导体分别连接到单个另外的电连接区。很多个电连接区是指几百个用于电源连接的连接区域。下述认识将有助于解释这一点。如果太多的半导体元件，例如CMOS IC的MOS(金属氧化物半导体)晶体管，连接到单个电源连接，所述晶体管的电源电压的稳定性受到影响。通过每次减少耦合到单个电源连接的晶体管的数目或者为每个电源提供更大功率的连接，可以大幅改善所述稳定性。
优选地，可以因此置于半导体主体表面上各处/任何地方的上述电源连接随后分组耦合到置于该半导体主体边缘的电源部分。用于电源连接的这些电连接区优选地为细长的，最长侧平行于该半导体主体的侧面延伸并直接与其邻接。
如果条形导体的宽度范围为10至100μm并相互之间距离的范围为1至100μm，可获得优良的结果。条形导体的宽度及其间距的选择也取决于其制作技术。为此，不同的方法是可能的，这将在稍后部分讨论。
在一更有利的实施例中，该半导体主体用合成树脂封装密封，设有导线连接的引线框的连接导体从该封装侧向凸出，且在该封装的下侧上所述另外的电连接区是电可达的。所述电连接区可以定形成适用于所谓的表面安装技术。然而，或者，所述电连接区可以优选地采取从封装凸出的引脚的形式，并以与位于IC边缘的I/O(输入/输出)信号引脚相似的方式粘附和安装在例如PCB(印刷电路板)上。
本发明还包含适用于根据本发明的半导体装置的半导体主体，其具有衬底和半导体区域，且该半导体主体合有多个集成电路形式的半导体元件，该半导体主体的表面设有多个电连接区，包括至少一个用于电源连接的电连接区，与该表面相对的半导体主体的一侧设有多个另外的电连接区，这些另外的电连接区通过电连接连接到位于半导体主体表面上的电连接区，电连接位于与该表面成一角度的半导体主体的侧面上并与其电绝缘，其特征在于：电连接包含多个间距规则的平行条形导体，且用于电源连接的电连接区中的每一个均通过两个或者多个所述条形连接体连接到另外的电连接区。
优选地，该半导体主体包含许多个用于多个电源连接的电连接区，所述电连接区分别为集成电路的一部分提供电源电流，位于该半导体主体的表面的边缘，且分别通过多个所述条形导体连接到分开的另外连接区。用于半导体主体内IC的电源电压的许多个连接优选每次成组地耦合到用于电源连接的电连接区之一，所述连接区是细长的，最长侧平行于该半导体主体的侧面延伸。优选地，所述条形导体的宽度范围为10至100μm，相互间距离的范围为1至100μm。
本发明还涉及一种半导体装置的制造方法，其中该半导体主体具有衬底和半导体区域，该半导体主体含有多个集成电路形式的半导体元件，该半导体主体的表面设有多个电连接区，包括至少一个的用于电源连接的电连接区，与该表面相对的半导体主体的一侧设有多个另外的电连接区，这些另外的电连接区通过电连接连接到位于半导体主体表面上的电连接区，电连接位于与该表面成一角度的半导体主体的侧面上并与其电绝缘，该半导体主体粘附到引线框且另外的电连接形成于形成引线框一部分的第一连接导体和电连接区之间，其特征在于：电连接形成为多个间距规则的平行条形导体，且用于电源连接的电连接区中的每一个均通过两个或者更多个所述条形导体连接到另外的电连接区，该另外的电连接区直接连接到形成引线框一部分的第二连接导体，而其它的电连接区通过另外的电连接直接连接到形成引线框一部分的第一连接导体。
在根据本发明的方法的第一实施例中，通过在半导体主体上提供掩模形成所述条形导体，该掩模覆盖其侧面并局部地设有狭缝，提供该掩模之后在该掩模上沉积导电层。
在另一个改变中，形成许多个半导体主体以使其相互集成，在各个半导体主体将被互相分离的表面的区域上形成孔，所述孔的壁覆盖有导电层，之后各个半导体主体被相互隔离，由每个孔内的导电层形成两个条形导体，所述导体之一位于一半导体主体的侧面上而另外一个位于相邻半导体主体的侧面上。
附图说明
参考下文中描述的(一个/多个)实施例，本发明的这些方面及其它方面变得明显并将得到详述。
附图中：
图1为根据本发明的半导体装置的实施例的示意性俯视图；
图2为图1中所示装置从由II表示的方向观察的示意性侧视图；
图3为图1中所示装置从由III表示的方向观察的示意性侧视图；
图4示出了使用根据本发明的方法的一个制作阶段中图1的装置；以及
图5示出了使用根据本发明的方法的另一个实施例的一个制作阶段中图1的装置。
具体实施方式
这些图未按比例绘制，某些尺寸(诸如沿厚度方向的尺寸)为了清晰起见而被夸大。不同附图中的相应区域或部分尽可能地用相同的参考数字表示。
图1为根据本发明的半导体装置的实施例的示意性俯视图，图2和图3分别为从图1中由II、III表示的方向观察的图1装置的示意性侧视图。该半导体装置10包含半导体主体11，该半导体主体具有衬底(此处为硅)和位于该衬底上的半导体区域(此处为硅)，该半导体主体含有多个集成电路形式的半导体元件，其表面211设有用于该集成电路的多个电连接区域1，包括至少两个用于电源连接的1A。与表面211相对的半导体主体11的一侧设有多个另外的电连接区域2，这些另外的电连接区域2通过二氧化硅层与衬底绝缘，并通过电连接3连接到半导体主体11表面上的电连接区域1，其中电连接3位于半导体主体11的侧面上并(此处是通过二氧化硅绝缘层112)与其电绝缘，所述侧面基本上与表面211相垂直地延伸。半导体主体11(此处通过焊接)粘接到引线框4，且另外的电连接5形成于形成引线框4的一部分的连接导体4A和电连接区1之间。
根据本发明，电连接3包含多个间距规则的条形平行导体3A，通过两个或者多个所述条形导体3A将每个用于电源连接的电连接区1A连接到另外的电连接区2，该另外的电连接区2直接连接到形成引线框4一部分的连接导体4B，而其它电连接区1B通过另外的电连接5(此处为导线连接5)直接连接到形成引线框4一部分的连接导体4A。这具有诸多优点，特别是如果该IC包含许多半导体元件并且引线框4相应地包含许多，例如好几百个连接导体4A、4B。最重要的优点为即使是在电源电压(更)低且电源电流非常高时，也有稳定的电源电压和优良的高频行为。此外，条形导体3A的“类似斑马纹”的图案一方面提供了连接区域(位置)的巨大设计自由度。另一方面，借助该图案3，可以排除大电流通过电连接3在其中引起的机械应力以及相关的热耗散可能呈现过高的值。
在本示例中，装置10包含许多用于电源连接的电连接区1A，每个电连接区1A为集成电路的一部分提供电源连接并位于半导体主体11表面的边缘，并且分别通过多个条形导体3A连接到单独的另外电连接区2。用于电源连接的电连接区1A优选地(象本示例中一样)为细长形，最长侧平行于半导体主体11的侧面延伸。在本示例中，条形导体3A的宽度约为10μm，其间距也约为10μm。这意味着表面积为1cm2的IC的侧面可容纳约10000/20＝500个条形导体3A。注意，与这些附图所示相反，半导体主体11的1、3、4侧面也可设有条形导体3A的斑马纹图案。
在本示例中，装置10的电学及机械最易受损部分用合成树脂封装(此处为环氧树脂材料)12密封，设有导线连接5的引线框4的连接导体4A从该封装的侧向凸出，且位于所述封装下侧的另外的电连接区2是可电可达的。在本示例中，该另外的连接区域2凭借以下事实是可到达的，其通过连接导体4B连接到从封装12凸出的引脚4C。图中示成平坦的导体4A也可以向下偏斜。由此，本示例的装置10可以适用于最终安装于PCB上。
图4示出了采用根据本发明的方法的一个制作阶段中图1的装置。在半导体主体11内形成IC，在其上侧设有连接区1A、1B的期望图案，并在其下侧上设有另外连接区2的期望图案之后，在该半导体主体11上放置掩模40，该掩模是由例如金属制成的。该掩模覆盖半导体主体11的上侧并覆盖其侧面的一部分。掩模40的侧面设有狭缝状的孔41。接着，该组件置于气相沉积或者溅射装置内之后，气相沉积或者溅射诸如铝的导电层。在孔41内，由此形成将电连接区1连接到另外的连接区域2的条形导体3A。如果需要，狭缝状孔41的一小部分可以在掩模40的上侧内的狭缝状凹进部分内延伸。这使得可以更加容易建立条形导体3A和半导体主体11的上边缘附近的连接区1A之间的连接。设有凹进部分的该板形掩模也可在半导体主体11倒置之后置于其下侧上，由此可以以类似的方式实现另外的连接区域2和条形导体3A之间更佳的电学接触。在此之后，再次除去掩模40，半导体主体11例如通过焊接安装到框架4上。提供导线连接5和封装12之后，装置10就可用于最终的组件或用途。
图5示出了采用根据本发明的方法的另一个实施例的一个制作阶段中图1的装置。在单个半导体主体111仍然含有许多个半导体主体11的阶段，半导体主体111的表面覆盖了掩模层(未示出)。图5只示出9个半导体主体11A...11H。在这些半导体主体11A...11H将最终被相互分开的位置50处，使用光刻和刻蚀在该掩模层内形成孔51。接着，通过在孔51的位置进行刻蚀，在半导体主体111内形成孔洞51。随后，例如使用气相沉积，在孔51内提供导电层52，由此使其壁上覆盖导电层52。接着，再次除去掩模层，由于所谓的剥离，位于所述掩模层上的导电层52的一些部分也会被除去。如果使用诸如锯切的分割方法最终将单个半导体主体11A...11H分割开，每个孔洞51内的导电层52被分成两个部分，每个部分形成两个相邻半导体主体11D、11E等的侧面上的条形导体3A。接着以与诸如图4的讨论中所示的相同方式进行另外的处理。
本发明不限于上述示例，本领域的技术人员在本发明的范围内可以进行许多变化和调整。例如，可以制造具有不同几何结构与/或不同尺寸的装置。尤其要注意，对于直接将IC输出和输入的信号连接到引线框导体的另外电连接，不仅可以利用导线连接，还可以利用所谓的凸点和相关表面安装技术。在所述情况中，引线框的一部分必须位于半导体主体的表面上方。通过使用不位于一个平面内的引线框可以实现这一点。使用两个分开的引线框也是可能的，其中一个用于半导体主体上侧，一个用于半导体主体的下侧。
至于该引线框，据观察，其也可以指具有连接导体的任何电学绝缘载体。该载体可含有本领域中已知的聚合物或陶瓷介电材料，或者可含有半导体衬底。后一个实施例组成了堆叠式管芯排列。然而，出于成本的原因，优选使用传统引线框。
同样地，制作方法也可以有许多变化。例如，在半导体主体的侧面上提供条形导体，或者可以采用所谓的3D光刻，在这种情况下，使用光刻和刻蚀将位于待形成的条形导体之间的导电层的一部分除去。或者通过使用激光束局部地清除导电层的一部分，可以除去所述过渡部分。该方法也可以用于例如分离半导体主体，来代替锯切。
最后要注意，该半导体主体可包含半导体衬底。假如这样的话，使用绝缘层将所述另外连接区与其电绝缘。如果需要，所述另外连接区的一个或者多个可以通过所述层内的开口连接到该衬底。如果该半导体主体设在绝缘衬底上，正如所谓的衬底转移技术的情形，当然可以省去所述层。当然仍必须为其上存在条形导体迹线的半导体主体的侧面提供绝缘。通过在该侧面上提供绝缘层可以实现这一点。由于在这种情况下该半导体主体本身相对薄，也可以通过热氧化将该侧面与半导体主体的表面绝缘。

Claims (13)

1.一种包含半导体主体(11)的半导体装置(10)，该半导体主体具有衬底和半导体区域，该半导体主体含有多个集成电路形式的半导体元件，该半导体主体的表面设有多个电连接区(1)，包括至少两个用于电源连接的电连接区(1A)，与该表面相对的半导体主体(11)的一侧设有多个另外的电连接区(2)，这些另外的电连接区(2)通过电连接(3)连接到位于半导体主体(11)表面上的电连接区(1)，电连接(3)位于与该表面成一角度的半导体主体(11)的侧面上并与其电绝缘，该半导体主体(11)粘附到引线框(4)且另外的电连接(5)形成于形成引线框(4)一部分的第一连接导体(4A)和电连接区(1)之间，其特征在于：电连接(3)包含多个间距规则的平行条形导体(3A)，且用于电源连接的电连接区(1A)中的每一个均通过两个或者多个所述条形导体(3A)连接到另外的电连接区(2)，该另外的电连接区(2)直接连接到形成引线框(4)一部分的第二连接导体(4B)，而其它的电连接区(1B)通过另外的电连接(5)直接连接到形成引线框(4)一部分的第一连接导体(4A)。
2.根据权利要求1所述的包含半导体主体(11)的半导体装置(10)，其特征在于：该半导体装置包含许多用于电源连接的电连接区(1A)，用于电源连接的电连接区(1A)中的每一个向所述集成电路提供一部分电源电流，且位于半导体主体(11)表面的边缘，并通过多个所述条形导体(3A)分别连接到单个另外的电连接区(2)。
3.根据权利要求2所述的包含半导体主体(11)的半导体装置(10)，其特征在于：用于电源连接的电连接区(1A)是细长的，最长一侧平行于半导体主体(11)的侧面延伸并邻接该侧面。
4.根据权利要求1、2或3所述的包含半导体主体(11)的半导体装置(10)，其特征在于：条形导体(3A)的宽度范围为10至100μm，相互间距离范围为1至100μm。
5.根据权利要求1至3中任何一项所述的包含半导体主体(11)的半导体装置(10)，其特征在于：该半导体主体(11)用合成树脂封装(12)密封，设有导线连接(5)的引线框(4)的第一连接导体(4A)从该封装侧向凸出，且在其下侧上的另外电连接区(2)是电可达的。
6.根据权利要求1至3中任何一项所述的包含半导体主体(11)的半导体装置(10)，其特征在于：所述另外的电连接(5)为导线连接。
7.适用于根据权利要求1所述的半导体装置(10)的半导体主体(11)，其具有衬底和半导体区域，且该半导体主体合有多个集成电路形式的半导体元件，该半导体主体(11)的表面设有多个电连接区(1)，包括至少一个用于电源连接的电连接区(1A)，与该表面相对的半导体主体的一侧设有多个另外的电连接区(2)，这些另外的电连接区(2)通过电连接(3)连接到位于半导体主体(11)表面上的电连接区(1)，电连接(3)位于与该表面成一角度的半导体主体(11)的侧面上并与其电绝缘，其特征在于：电连接(3)包含多个间距规则的平行条形导体(3A)，且用于电源连接的电连接区(1A)中的每一个均通过两个或者多个所述条形导体(3A)连接到另外的电连接区(2)。
8.根据权利要求7所述的半导体主体(11)，其特征在于：半导体主体(11)包含许多用于电源连接的电连接区(1A)，这些用于电源连接的电连接区(1A)中的每一个分别向集成电路的一部分提供电源电流，位于半导体主体(11)表面的边缘，并通过多个所述条形导体(3A)分别连接到单个另外的电连接区(2)。
9.根据权利要求8所述的半导体主体(11)，其特征在于：用于电源连接的电连接区(1A)是细长的，最长侧平行于半导体主体(11)的侧面延伸并直接邻接该侧表面。
10.根据权利要求7、8或9所述的半导体主体(11)，其特征在于：该条形导体(3A)的宽度范围为10至100μm，且相互间距离范围为主至100μm。
11.包含半导体主体(11)的半导体装置(10)的制作方法，该半导体主体(11)具有衬底和半导体区域，该半导体主体含有多个集成电路形式的半导体元件，该半导体主体的表面设有多个电连接区(1)，包括至少一个用于电源连接的电连接区(1A)，与该表面相对的半导体主体(11)的一侧设有多个另外的电连接区(2)，这些另外的电连接区(2)通过电连接(3)连接到位于半导体主体(11)表面上的电连接区(1)，电连接(3)位于与该表面成一角度的半导体主体(11)的侧面上并与其电绝缘，该半导体主体(11)粘附到引线框(4)且另外的电连接(5)形成于形成引线框(4)一部分的第一连接导体(4A)和电连接区(1)之间，其特征在于：电连接(3)形成为多个间距规则的平行条形导体(3A)，且用于电源连接的电连接区(1A)中的每一个均通过两个或者更多个所述条形导体(3A)连接到另外的电连接区(2)，该另外的电连接区(2)直接连接到形成引线框(4)一部分的第二连接导体(4B)，而其它的电连接区(1B)通过另外的电连接(5)直接连接到形成引线框(4)一部分的第一连接导体(4A)。
12.根据权利要求11所述的方法，其特征在于：通过在半导体主体(11)上提供掩模(40)形成条形导体(3A)，该掩模覆盖该半导体主体的侧面并原位地设有狭缝(41)，且在提供掩模(40)之后，在其上沉积导电层。
13.根据权利要求11所述的方法，其特征在于：形成许多半导体主体(11)，使其相互集成，并在单个半导体主体将被相互分离的表面区域(50)上形成孔(51)，所述孔洞的壁被覆盖导电层(52)，之后单个的半导体主体(11)被互相分离，每个孔(51)内的导电层(52)形成两个条形导体(3A)，所述导体之一位于半导体主体(11)的侧面上，另一个位于相邻半导体主体(11)的侧面上。
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