CN100401485C - Packing method capable of increasing percent of pass for multiple chip package - Google Patents
Packing method capable of increasing percent of pass for multiple chip package Download PDFInfo
- Publication number
- CN100401485C CN100401485C CNB021122350A CN02112235A CN100401485C CN 100401485 C CN100401485 C CN 100401485C CN B021122350 A CNB021122350 A CN B021122350A CN 02112235 A CN02112235 A CN 02112235A CN 100401485 C CN100401485 C CN 100401485C
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- Prior art keywords
- chips
- chip
- packing
- many pieces
- glue
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention provides a packing method capable of increasing the qualified rate of multi-chip packing. The traditional multi-chip packing method has the problem of low qualified rate. The packing method capable of increasing the qualified rate of multi-chip packing comprises the steps that a base plate is prepared, a plurality of chips are obtained by a plurality of circular scribing chips, one of the chips or part of the chips is fed and placed on the base plate, one of the chips or part of the chips is welded with a line, glue dropping is carried out, one of the chips or part of the chips is covered by plastic packing glue which is in the state of liquid at room temperature, bulges are formed and solidified, one of the chips or part of the chips, which is covered, is tested, the rest chips of the chips are fed and welded with lines, the whole component which comprises the base plate and the chips is moulded and pressed, the plastic packing glue which is melted at high temperature is punched in moulds, and the plastic packing glue is formed on the chips. The method of the present invention can effectively enhance the qualified rate.
Description
Technical field
The present invention relates to a kind of method for packing of chip, relate in particular to a kind of method for packing of multicore sheet.
Background technology
MCM (Multl Chip Modulus), i.e. multicore sheet encapsulation is by extensive and a large amount of technology of using in the present integrated circuit encapsulation field.This technology can be enclosed two or more chips in a device, thereby makes device have more strong functions.
Its specific embodiment is summarized as follows.Please refer to Figure 1A-Fig. 1 C, in this example with the example that is encapsulated as of three pieces of chips.Shown in Figure 1A, at first, prepare a suitably substrate 101 of size, then, after the wafer scribing, carry out last slice, that is, 3 pieces of chip 102A, 102B and 10C3 are gone up to substrate 101; Then, shown in Figure 1B, 3 pieces of chips are carried out the bonding wire step respectively, promptly chip 102A, 102B and 102C are electrically connected on the soldered ball 104 at substrate 101 back sides (shown in Fig. 1 C) by gold thread 103; At last for chip and substrate behind the bonding wire carry out mold pressing procedure, promptly with high temperature down the plastic packaging glue 105 of fusing inject moulds, plastic packaging glue 105 is solidificated on the substrate 101, chip 102A, 102B and 102C and gold thread 103 are protected.
There are the following problems for above-mentioned this traditional multicore sheet method for packing:
1. owing to put a plurality of chips in the device, cause when carrying out mold pressing procedure, mobile plastic packaging glue is subjected to the obstruction of different chip and gold thread, and fluidised form is in a mess in the mould, thereby gold thread is caused very big impact, failure mode such as cause short circuit or open circuit.Especially for smaller chip,, can cause bigger influence because the gold thread that connects is less, more sparse.
2. when chip failure in a plurality of chips, entire device all will be scrapped, and it is very low to cause encapsulating yields.Special in the example of Fig. 1, there is one piece than large chip and two pieces of less chips.Usually, the cost of large chip can be much larger than little chip.So when little chip failure, although bigger chip is normal, entire device all will be scrapped.This just causes the device of the qualification rate of high cost and encapsulation much smaller than single chip.
Summary of the invention
Therefore, the problem according to conventional art exists the objective of the invention is to traditional multicore sheet encapsulation technology is improved, and proposes a kind of multicore sheet method for packing that can improve the encapsulation qualification rate effectively.
According to above-mentioned purpose of the present invention, multicore sheet method for packing provided by the invention comprises:
Prepare a substrate;
A plurality of wafer scribings are obtained many pieces of chips, one of many pieces of chips or a part of chip are carried out last slice, be placed on the described substrate;
Described one piece of chip or a part of chip are carried out bonding wire;
By a glue process, be down that liquid plastic packaging glue covers the formation projection with described one piece of chip or a part of chip with normal temperature, and solidify;
To testing through the described one piece of chip or a part of chip that cover;
Segment chip remaining in the described many pieces of chips is carried out last slice and bonding wire;
The entire device that comprises described substrate and described many pieces of chips is carried out mold pressing, and the plastic packaging glue that melts down with high temperature pours in the mould, forms plastic packaging glue on described many pieces of chips.
Aforesaid multicore sheet method for packing, one of described many pieces of chips or a part of chip are little chip.
Aforesaid multicore sheet method for packing offers one or more cavitys on described substrate, one of described many pieces of chips, part or all is positioned in the described cavity.
As mentioned above, in multicore sheet method for packing of the present invention, many pieces of chips to be packaged two parts have been divided into, to when mold pressing procedure, carry out a glue process earlier by easy impaired (little) chip, cover for liquid plastic packaging glue down with normal temperature, reduce the possibility of its damage, simultaneously, semi-finished product after this step are tested, other is worth higher chip to continue encapsulation after test passes, to improve the qualification rate of end product, reduce or eliminate the situation that causes the full wafer integrated circuit to be scrapped because of lower-cost chip is impaired substantially and take place.
Description of drawings
Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.In the accompanying drawing:
Figure 1A-C shows the schematic diagram of traditional multicore sheet method for packing;
Fig. 2 A-F shows the schematic diagram of multicore sheet method for packing of the present invention;
Fig. 3 A-B shows two variation examples that multicore of the present invention is levied encapsulating structure.
Embodiment
Please refer to the process that Fig. 2 A-F describes multicore sheet method for packing of the present invention below.At first, the same with conventional method, prepare a substrate 1, to a plurality of wafer scribings, obtain many pieces of chips, from many pieces of chips, pick out-piece chip or a part of chip, principle can be select the chip that needs protection or volume less or be worth lower chip.In the present embodiment, be example still, but should be appreciated that multicore sheet method for packing of the present invention is not limited to this, but can be applied to any chip that comprises more than two pieces or two pieces with three pieces of chips.As described in Fig. 2 A, pick out two pieces of less chip 2A and 2B according to mentioned above principle, be placed on the substrate 1, finish an operation; Then, chip 2A and 2B are carried out bonding wire, chip 2A and 2B are electrically connected to substrate 1 back side by gold thread 3.Last slice operation here is identical with traditional technology with the bonding wire operation, therefore, just launches no longer in detail to discuss at this.
Next step is the present invention and other committed step of conventional art phase region; promptly to above-mentioned through last slice and bonding wire after segment chip cover; promptly; by a glue process; cover chip 2A, 2B and gold thread 3 thereof for liquid plastic packaging glue 6 down with normal temperature; solidify the back and form projection, with protection chip 2A, 2B and gold thread thereof.Because in this step is plastic packaging glue be liquid state under the normal temperature, therefore, can not cause gold thread to drift about.Can improve little core and levy the rate of finished products of encapsulation.Above-mentioned steps can be referring to Fig. 2 B and Fig. 2 C, and wherein Fig. 2 C is the vertical view of Fig. 2 B.
After finishing above-mentioned steps, earlier these semi-finished product to be tested, this test can utilize testing equipment to carry out automatically, the step below continuing under the situation of test passes.
Then, to the chip of remainder, promptly chip 2C carries out last slice and the bonding wire operation, and its method is the same, and can be referring to Fig. 2 D and Fig. 2 E.At last, entire device is carried out mold pressing, promptly the plastic packaging glue that melts down with high temperature pours in the mould, forms plastic packaging glue 5 on all chips.At this moment, because the little chip of easily impaired when mold pressing procedure (easily causing the gold thread drift) is covered by plastic-sealed body 6, therefore, when this mold pressing procedure, can not cause the gold thread drift phenomenon again, therefore, this mold pressing procedure can not cause bad to little chip, thereby can improve rate of finished products and qualification rate effectively.
Fig. 3 A and Fig. 3 B show two kinds of distortion of the present invention.As shown in Figure 3A, on substrate 1, offer cavity 7, in the time of last, little chip 2A and 2B are placed in the cavity 7, can reduce the height of the projection of liquid plastic packaging glue formation like this.Certainly, also can play the effect that reduces integrated circuit thickness equally for large chip 2C is provided with cavity 8 (shown in Fig. 3 B).
Claims (3)
1. a multicore sheet method for packing comprises:
Prepare a substrate;
A plurality of wafer scribings are obtained many pieces of chips, one of many pieces of chips or a part of chip are carried out last slice, be placed on the described substrate;
Described one piece of chip or a part of chip are carried out bonding wire;
Carry out a glue then, be down that liquid plastic packaging glue covers the formation projection with described one piece of chip or a part of chip with normal temperature, and solidify;
To testing through the described one piece of chip or a part of chip that cover;
Segment chip remaining in the described many pieces of chips is carried out last slice and bonding wire;
The entire device that comprises described substrate and described many pieces of chips is carried out mold pressing, and the plastic packaging glue that melts down with high temperature pours in the mould, forms plastic packaging glue on described many pieces of chips.
2. multicore sheet method for packing as claimed in claim 1 is characterized in that one of described many pieces of chips or a part of chip are little chip.
3. multicore sheet method for packing as claimed in claim 1 or 2 is characterized in that, offers one or more cavitys on described substrate, and one of described many pieces of chips, part or all is positioned in the described cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021122350A CN100401485C (en) | 2002-06-26 | 2002-06-26 | Packing method capable of increasing percent of pass for multiple chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021122350A CN100401485C (en) | 2002-06-26 | 2002-06-26 | Packing method capable of increasing percent of pass for multiple chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1464540A CN1464540A (en) | 2003-12-31 |
| CN100401485C true CN100401485C (en) | 2008-07-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021122350A Expired - Fee Related CN100401485C (en) | 2002-06-26 | 2002-06-26 | Packing method capable of increasing percent of pass for multiple chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100401485C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7400037B2 (en) * | 2004-12-30 | 2008-07-15 | Advanced Chip Engineering Tachnology Inc. | Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP |
| CN100356532C (en) * | 2005-03-26 | 2007-12-19 | 阎跃军 | Liquid resin dropping packaging method |
| CN103165479B (en) * | 2013-03-04 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of multichip system class encapsulation structure |
| CN110600432A (en) * | 2019-05-27 | 2019-12-20 | 华为技术有限公司 | Packaging structure and mobile terminal |
| CN110808244A (en) * | 2019-10-29 | 2020-02-18 | 长春希龙显示技术有限公司 | LED display unit surface packaging method based on modeling technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155760A (en) * | 1995-12-15 | 1997-07-30 | 国际商业机器公司 | Controlled profile multiple chip modules |
| CN1180927A (en) * | 1996-10-17 | 1998-05-06 | 国际商业机器公司 | High performance, low cost multi-chip module package |
| US6239496B1 (en) * | 1999-01-18 | 2001-05-29 | Kabushiki Kaisha Toshiba | Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same |
| US6301121B1 (en) * | 1999-04-05 | 2001-10-09 | Paul T. Lin | Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process |
-
2002
- 2002-06-26 CN CNB021122350A patent/CN100401485C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155760A (en) * | 1995-12-15 | 1997-07-30 | 国际商业机器公司 | Controlled profile multiple chip modules |
| CN1180927A (en) * | 1996-10-17 | 1998-05-06 | 国际商业机器公司 | High performance, low cost multi-chip module package |
| US6239496B1 (en) * | 1999-01-18 | 2001-05-29 | Kabushiki Kaisha Toshiba | Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same |
| US6301121B1 (en) * | 1999-04-05 | 2001-10-09 | Paul T. Lin | Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1464540A (en) | 2003-12-31 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Shanghai Guo Shou Jing Road, Pudong Zhangjiang hi tech Park No. 669 Patentee after: Riyueguang Packaging & Test (shanghai) Co., Ltd. Address before: Shanghai Guo Shou Jing Road, Pudong Zhangjiang hi tech Park No. 669 Patentee before: Weiyu Tech Test Packing Co., Ltd. |
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| C56 | Change in the name or address of the patentee |
Owner name: RIYUEGUANG ENCAPSULATION TESTING ( SHANGHAI ) CO., Free format text: FORMER NAME: WEIYU TECHNOLOGY TEST ENCAPSULATION CO., LTD. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080709 Termination date: 20150626 |
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| EXPY | Termination of patent right or utility model |