CN100399539C - Technique for forming gapless shallow channel insulation area by subatmospheric CVD method - Google Patents
Technique for forming gapless shallow channel insulation area by subatmospheric CVD method Download PDFInfo
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- CN100399539C CN100399539C CNB2005100879895A CN200510087989A CN100399539C CN 100399539 C CN100399539 C CN 100399539C CN B2005100879895 A CNB2005100879895 A CN B2005100879895A CN 200510087989 A CN200510087989 A CN 200510087989A CN 100399539 C CN100399539 C CN 100399539C
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Abstract
The invention discloses a trench insulation area process, firstly forming an isolation trench in a semiconductor substrate; making SACVD (selected area chemical vapor deposition) to deposit a silicon oxide layer on the semiconductor substrate and making the silicon oxide fill the isolation trench, where the silicon oxide layer forms a joint in the isolation trench; making a low-temperature vapor annealing process to eliminate the joint in hydrogen/oxygen gas; and finally making a high temperature annealing process to compact the silicon oxide layer in inert gas with a temperature higher than 900 deg.C.
Description
Technical field
The present invention relates to the manufacturing of semiconductor integrated circuit, (sub-atmospheric pressure chemical vapor deposition, SACVD) technology forms the technology of seamless (seamless) shallow trench insulating regions to relate in particular to a kind of utilization time aumospheric pressure cvd.
Background technology
In recent years, along with semiconductor technology design live width continue dwindle, be implemented on the semiconductor substrate surface, in order to the trench isolation of electrical isolation element effectively or be called shallow-channel insulation (shallowtrench isolation, STI) technology also becomes more and more important problem, and how effectively to fill up a major challenge that narrow day by day insulation irrigation canals and ditches have also become this technical field.
Traditional shallow-channel insulation technology is to utilize chemical vapour deposition (CVD) (chemical vapor deposition earlier, CVD) method, fill up dielectric layer with being formed in the insulation irrigation canals and ditches of substrate surface, and then etch-back or remove the outer additional dielectric layer of insulation irrigation canals and ditches in chemico-mechanical polishing (CMP) mode, form smooth substrate surface.But along with semiconductor technology enters the deep-sub-micrometer epoch, improving constantly of integrated circuit density and development that component size is day by day dwindled, ladder covering (step coverage) ability that makes aforesaid chemical gaseous phase depositing process to provide has been not enough to deal with the bigger situation of depth-width ratio (aspect ratio) when irrigation canals and ditches, just is not easy dielectric layer is filled up irrigation canals and ditches fully.
For improving the problems referred to above, have the chemical vapour deposition technique of multiple Improvement type to be suggested, wherein being proved to possess through part Study with auxiliary time aumospheric pressure cvd (ozone-assisted SACVD) technology of ozone has the excellent step covering power and the uniformity.The auxiliary time aumospheric pressure cvd technology of above-mentioned ozone is to utilize ozone and silicon tetraethyl methane (TEOS) as the initial gas of reaction, the all thick silica layer of inferior condition of normal pressure deposit that is about 60 holders (torr) in for example reaction pressure, and be accompanied by follow-up high-temperature annealing step usually, for example about 1000 ℃ of temperature and in the nitrogen environment with the silica layer densification that is deposited.
Yet the auxiliary time aumospheric pressure cvd technology of aforesaid ozone but still has many shortcomings and awaits further overcoming and improvement in practical application.The silicon oxide thin film itself that is deposited with the auxiliary time aumospheric pressure cvd technology of existing ozone at high temperature can shrink, for example after handling 30 minutes under 1050 ℃, have up to about shrinkage amplitude of about 7%, and the characteristic of SACVD silicon oxide thin film is also relatively poor, and for example, the wet etching rate is very fast.In addition, as shown in Figure 1, auxiliary time another the more serious problem of aumospheric pressure cvd technology of ozone is owing to time aumospheric pressure cvd film growth characteristic mainly is to be grown up to the centre by the sidewall 22 of irrigation canals and ditches 20 to fill up irrigation canals and ditches, therefore, finally can in the middle of the irrigation canals and ditches 20 of substrate 10, form impervious seam (seam) 50, and this fault in seam 50 can't be removed with traditional nitrogen environment annealing way, and be subjected to the erosion of follow-up cleaning step easily, cause being communicated with problems such as the formation of groove and polysilicon lines short circuit.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of technology of shallow trench insulating regions of improvement, utilizes time aumospheric pressure cvd technology and low-temperature steam annealing (steam anneal) technology, reaches the purpose of seamless filled insulation irrigation canals and ditches.
For reaching above-mentioned purpose of the present invention, the invention provides a kind of trench insulation zone technology.Semi-conductive substrate is provided earlier, is formed with a mask layer on it; Carry out a photoetching and etch process, in this mask layer, form an opening, expose this Semiconductor substrate of part; Via this this Semiconductor substrate of opening etching, form insulation irrigation canals and ditches; Carry out time aumospheric pressure cvd (SACVD) technology, deposition one silica layer on this Semiconductor substrate, and fill up this insulation irrigation canals and ditches, this silica layer forms a seam in these insulation irrigation canals and ditches; Carry out a low-temperature steam annealing process, in hydrogen and oxygen atmosphere and under 500-800 ℃ the annealing temperature, eliminate this seam; Carry out a high-temperature annealing process at last, this silica layer of densification under 900-1100 ℃ temperature and in the inert gas environment.
In order to make those skilled in the art can clearer understanding feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 illustrated is the generalized section of existing shallow trench insulating regions;
What Fig. 2 to 5 illustrated is the generalized section that the preferred embodiment of the present invention forms the technology of gapless shallow canal insulating regions;
Fig. 6 forms the flow chart of the technology of gapless shallow canal insulating regions for the preferred embodiment of the present invention.
The main element symbol description
10 Semiconductor substrate, 20 insulation irrigation canals and ditches
22 trench sidewalls, 24 irrigation canals and ditches bottom
30 mask layers, 32 pad oxides
34 pad silicon nitride layers, 36 openings
42 thermal oxidation layings, 50 seams
52 ozone-silicon tetraethyl methane silica layer 56 irrigation canals and ditches corners
Embodiment
In order further to clearly demonstrate the content that the present invention's time aumospheric pressure cvd technology forms the technology of gapless shallow canal insulating regions, below promptly describe its manufacturing process and step in detail with reference to Fig. 2 to 6, what wherein Fig. 2 to 5 illustrated is the generalized section that the preferred embodiment of the present invention forms the technology of gapless shallow canal insulating regions, and Fig. 6 forms the flow chart of the technology of gapless shallow canal insulating regions for the preferred embodiment of the present invention.
At first, as shown in Figure 2, on semi-conductive substrate 10, for example on the silicon substrate, cover the pad oxide 32 that a thickness is about 30 dust to 200 dusts.Pad oxide 32 can be to utilize chemical vapour deposition technique or thermal oxide growth mode to form.Subsequently, on pad oxide 32, cover the pad silicon nitride layer 34 that a thickness is about 500 dust to 2000 dusts, and with pad oxide 32 jointly as mask layer 30.
As shown in Figure 3, then in mask layer 30, form opening 36 with photoetching process and etch process, and then the Semiconductor substrate 10 of utilizing mask layer 30 to come out via opening 36 downward etch exposed as etching mask, forming insulation irrigation canals and ditches 20, its depth H is approximately between 3500 dust to 6000 dusts.According to a preferred embodiment of the invention, the depth-width ratio of insulation irrigation canals and ditches 20 (that is the insulation depth H of irrigation canals and ditches 20 and the ratio of width W) is greater than 4.5.Next, carry out a thermal oxidation technology, form thermal oxidation laying 42 to go up with 24 surfaces, bottom in the sidewall 22 of insulation irrigation canals and ditches 20.
As shown in Figure 4, then carry out time aumospheric pressure cvd technology, use ozone and silicon tetraethyl methane (TEOS) as the initial gas of reaction, be about all thick ozone-silicon tetraethyl methane silica layer 52 of inferior condition of normal pressure deposit of 60 holders (torr) in for example reaction pressure.Ozone-silicon tetraethyl methane silica layer 52 covers on the mask layer 30 and fills up insulation irrigation canals and ditches 20.As previously mentioned, owing to time aumospheric pressure cvd film growth characteristic mainly is to be grown up to the centre by the sidewall 22 of insulation irrigation canals and ditches 20 to fill up irrigation canals and ditches, therefore, finally can in the middle of irrigation canals and ditches 20, form impervious seam 50, and this fault in seam can't be removed with traditional nitrogen environment annealing way, and be subjected to the erosion of follow-up cleaning step easily, cause being communicated with problems such as the formation of groove and polysilicon lines short circuit.
According to another preferred embodiment of the invention, ozone-silicon tetraethyl methane silica layer 52 can deposit under different ozone-silicon tetraethyl methane ratio.Compared to the ozone-silicon tetraethyl methane silica layer that arrives the thickness of being wanted with identical ozone-silicon tetraethyl methane ratio primary depositing, with the ozone-silicon tetraethyl methane silica layer of different ozone-silicon tetraethyl methane ratio step deposition repeatedly, its film characteristics is preferable.
As shown in Figure 5, for addressing the above problem, to reach the purpose of seamless filled insulation irrigation canals and ditches, then carry out low-temperature steam annealing (steam anneal) technology, it is hydrogen and the oxygen that feeds high flow capacity in the high temperature furnace pipe (not shown), the flow-rate ratio of hydrogen and oxygen is about between 1: 2 to 3: 1, is carrying out under 500 ℃ to 800 ℃ the temperature about about 30 minutes to 60 minutes.According to a preferred embodiment of the invention, after deposition ozone-silicon tetraethyl methane silica layer 52, with flow 5 to 20 liters/minute (L/min), 15 liters/minute hydrogen for example, and 5 to 20 liters/minute of flows, for example 10 liters/minute oxygen feeds temperature and is about the annealing of carrying out in 700 ℃ the boiler tube more than at least 30 minutes, can reach seamless filled insulation irrigation canals and ditches, eliminate seam 50.
What need pay special attention to is, if above-mentioned steam annealing temperature is higher than more than 800 ℃, the corner 56 that then can make insulation irrigation canals and ditches 20 on the contrary is by oxidation significantly, cause insulation irrigation canals and ditches 20 corner sphering (cornerrounding) effects, therefore and have influence on the area size of active region, therefore and be not suitable for using the temperature that is higher than more than 800 ℃ to carry out this steam annealing step.In addition, from experimental result, in above-mentioned low-temperature steam annealing process procedure, the high flow capacity of keeping hydrogen/oxygen also has its necessity, could eliminate seam 50 effectively because need keep the hydrogen/oxygen of high flow capacity.
After finishing the low-temperature steam annealing process, just continue with higher temperature, for example 900 ℃ to 1100 ℃ high temperature carries out the densification of ozone-silicon tetraethyl methane silica layer 52 in nitrogen environment or inert gas environment.Above-mentioned low-temperature steam annealing process and high temperature nitrogen annealing process can carry out before and after (in-situ) in same boiler tube, perhaps also can carry out in different annealing devices respectively, are not specially limited.Follow-up flatening process, for example chemico-mechanical polishing program, then identical with existing skill, repeat no more.
See also Fig. 6, what it illustrated is the flow chart that the preferred embodiment of the present invention forms the technology of gapless shallow canal insulating regions.The technological process 60 that the present invention forms gapless shallow canal insulating regions mainly includes four steps, and wherein irrigation canals and ditches are etched with step 62 and the formation of thermal oxidation laying in order to insulate; Step 64 is for filling up the insulation irrigation canals and ditches with the auxiliary SACVD technology of ozone; Step 66 is the seam removal process, is that the CVD insulating barrier that will be deposited with the auxiliary SACVD technology of ozone carries out steam annealing with relatively low temperature (600 ℃～800 ℃) in the hydrogen/oxygen environment of high flow capacity; At last, step 66 is the high temperature nitrogen annealing process, fills up the CVD insulating barrier of insulation irrigation canals and ditches in order to densification.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (6)
1. technology of making the trench insulation zone may further comprise the steps:
In semi-conductive substrate, form insulation irrigation canals and ditches;
Carry out time aumospheric pressure cvd technology, deposition one silica layer on this Semiconductor substrate, and fill up this insulation irrigation canals and ditches, this silica layer forms a seam in these insulation irrigation canals and ditches;
Carry out a low-temperature steam annealing process, eliminate this seam in hydrogen and oxygen atmosphere and under 500-800 ℃ the annealing temperature; And
Carry out a high-temperature annealing process, this silica layer of densification under 900-1100 ℃ temperature and in the inert gas environment.
2. the technology in manufacturing trench insulation as claimed in claim 1 zone wherein forms the insulation irrigation canals and ditches and may further comprise the steps in Semiconductor substrate:
On described Semiconductor substrate, form a mask layer;
Carry out a photoetching and etch process, in this mask layer, form an opening, expose this Semiconductor substrate of part;
Via this this Semiconductor substrate of opening etching, form insulation irrigation canals and ditches.
3. the technology in manufacturing trench insulation as claimed in claim 2 zone, wherein this mask layer comprises a pad oxide and a pad silicon nitride layer.
4. the technology in manufacturing trench insulation as claimed in claim 2 zone, wherein this time aumospheric pressure cvd technology is to use ozone and silicon tetraethyl methane as the initial gas of reaction.
5. the technology in manufacturing trench insulation as claimed in claim 2 zone, wherein employed this hydrogen and oxygen in this low-temperature steam annealing process, its hydrogen flowing quantity is between 5 to 20 liters/minute, oxygen flow is between 5 to 20 liters/minute.
6. the technology in manufacturing trench insulation as claimed in claim 2 zone, wherein the annealing time of this low-temperature steam annealing process is at least above 30 minutes.
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| CNB2005100879895A CN100399539C (en) | 2005-07-28 | 2005-07-28 | Technique for forming gapless shallow channel insulation area by subatmospheric CVD method |
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| CN100399539C true CN100399539C (en) | 2008-07-02 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8187948B2 (en) | 2008-02-18 | 2012-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid gap-fill approach for STI formation |
| CN101740326A (en) * | 2008-11-10 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Annealing method |
| US8043884B1 (en) * | 2010-05-24 | 2011-10-25 | Nanya Technology Corporation | Methods of seamless gap filling |
| CN103531523A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
| US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
| JP2004311631A (en) * | 2003-04-04 | 2004-11-04 | Kyoshin Engineering:Kk | Steam annealing method |
| US20050136684A1 (en) * | 2003-12-23 | 2005-06-23 | Applied Materials, Inc. | Gap-fill techniques |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
| US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
| JP2004311631A (en) * | 2003-04-04 | 2004-11-04 | Kyoshin Engineering:Kk | Steam annealing method |
| US20050136684A1 (en) * | 2003-12-23 | 2005-06-23 | Applied Materials, Inc. | Gap-fill techniques |
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