CN100388252C - Method for realizing double port synchronous memory device and related apparatus thereof - Google Patents
Method for realizing double port synchronous memory device and related apparatus thereof Download PDFInfo
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- CN100388252C CN100388252C CNB2004101021139A CN200410102113A CN100388252C CN 100388252 C CN100388252 C CN 100388252C CN B2004101021139 A CNB2004101021139 A CN B2004101021139A CN 200410102113 A CN200410102113 A CN 200410102113A CN 100388252 C CN100388252 C CN 100388252C
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Abstract
The present invention provides a method for realizing a double-port synchronous memory device by a single-port memory and a related device thereof. A double-port synchronous memory device triggered by a clock pulse can synchronously receive a reading command and a writing command within the same period of the clock pulse for simultaneously reading/writing data; a single-port memory only carries out the reading command or the writing command within the same time. When the present invention realizes a multi-port synchronous memory device by the single-port memory with low cost and small layout area, the single-port memory firstly finishes one command within the same period, and then continuously executes the next command so that the reading command and the writing command are finished when one period is finished for realizing the function of the double-port synchronous memory device.
Description
Technical field
The present invention relates to a kind of method and relevant apparatus of realizing the multiport synchronous memory device, particularly relate to and a kind ofly can realize the method and the relevant apparatus of multiport synchronous memory device with one-port memory low-cost, little layout area.
Background technology
In modern information society, various data, file, data and audio-visual message can both be handled fast, propagate, manage and store with the form of electric signal (especially digital and electronic signal), and various electronic circuit that is used for transmission electronic signal, administration of electronic data also just becomes the emphasis of present information manufacturer research and development.Wherein, the multiport synchronous memory device that can carry out data read/write synchronously just has purposes widely.Under the triggering of time clock, the instruction that the multiport synchronous memory device can synchronous receiving data reads and writes in same clock cycle, and in same clock cycle, finish data read and write; That is to say, in the time will writing to some address in the memory storage, can also simultaneously other data be read by other address of this memory storage to given data.
Because the characteristic that the multiport synchronous memory device can read while write, make the multiport synchronous memory device can be conveniently used for realizing the various buffers that carry out the sequence management, similarly be first-in first-out (FIFO, first-in-first-out) buffer also can be realized out impact damper on data transfer path.For instance, in the comparatively complicated control circuit of function, often will be to different work requirements (task) sort (queue), with each work requirements of series processing, and fifo buffer just can be used to store the work requirements in the ordering, the work requirements of different order can be temporary in fifo buffer in regular turn, and the work requirements that is deposited earlier in buffer can be read in advance, and is handled in advance.In other words, the function class of fifo buffer is similar to the storehouse (stack) of a first-in first-out, it can be read inputing to data temporary in the buffer earlier, simultaneously can also with after input to buffer data keep in, and double port synchronous memory device just in time can satisfy the functional requirement of fifo buffer.
In like manner, on data transfer path, when a certain device A will transfer to each data another device B in regular turn,, just can between device A and device B, an impact damper be set if device B can not synchronously receive according to the transfer rate of installing A; Device A can be according to its transfer rate with data transmission to impact damper (write buffer just), the receiving velocity that device B then can allow according to its running and by receiving data (just with data by reading in the impact damper) in the impact damper.Because device A and B may will write impact damper/read simultaneously, so impact damper just can utilize double port synchronous memory device to realize.
By above-mentioned discussion as can be known, double port synchronous memory device can be applied in the various electronic circuits widely.Yet in known technology, double port synchronous memory device is that higher with cost, that layout area is bigger dual-ported memory (just dual-port static random access memory, two-port staticrandom access memory) is realized.In dual-ported memory, each storage unit (cell) that is used for storing the one digit number certificate is equipped with two access ports, and each access port all will be provided with specific access control transistor.And dual-ported memory also will be provided with two independently data transmission links; Each data transmission link is connected in each storage unit via an access port of each storage unit respectively.For instance, certain storage unit C1 and C2 are equipped with one first access port and one second access port, first access port of storage unit C1, C2 all is connected in first data transmission link, and second access port of storage unit C1 and C2 all is connected in second data transmission link.When double port synchronous memory device to read synchronously write fashionable, if will be with a certain data by reading among the storage unit C1 and another data being write to storage unit C2, first access port of storage unit C1 just can be opened (conducting), and the data of storage unit C1 can be transferred out by first data transmission link; Simultaneously, first access port of storage unit C2 is then closed (not conducting), allows storage unit C2 can mistakenly the data of storage unit C2 not transmitted data via first data transmission link.At storage unit C1 by first access port during with data transmission to the first data transmission link, second access port of storage unit C2 then is unlatching/conducting, and data can be transferred to storage unit C2 and write to storage unit C2 via second data transmission link; Simultaneously, second access port of storage unit C1 is then closed/not conducting, allows storage unit C1 can not receive the data that will transfer to storage unit C2 by second data transmission link mistakenly.
Though above-mentioned known dual-ported memory can be realized the function of double port synchronous memory device really, but because each storage unit all will be provided with two access ports and corresponding access control transistor in the dual-ported memory, make that also the shared layout area of dual-ported memory is bigger, circuit structure is comparatively complicated, the time of design, the manufacturing is also relative with cost higher, is unfavorable for popularizing of double port synchronous memory device.
Summary of the invention
Therefore, fundamental purpose of the present invention, promptly be to provide a kind of method and relevant apparatus that can utilize one-port memory to realize double port synchronous memory device, so that utilize layout area less, one-port memory with low cost (similarly being the single port static RAM) is realized double port synchronous memory device, overcomes the shortcoming of known technology.
One-port memory only can carry out the single instruction of reading or write at one time.But one-port memory (especially static memory) can be carried out the read/write instruction quite apace, realize double port synchronous memory device and will in same clock cycle, carry out data read/write fashionable synchronously, the present invention makes one-port memory carry out in the preceding semiperiod earlier exactly and reads or write one of instruction, carry out another instruction again in the later half cycle, so just can be in a clock cycle finish data read/write, realize the function of double port synchronous memory device with one-port memory.
When reality realized, the present invention's control interface of one one-port memory can being arranged in pairs or groups was realized multipor memory device.In one embodiment of the invention, control interface can be provided with a moderator, when receiving simultaneously, control interface read and writes 2 whens instruction, this moderator just can allow one of them instruction preferentially be transferred to one-port memory according to default right of priority, allow one-port memory carry out this instruction earlier, carry out the another one instruction then.For instance, it is preferential moderator can be redefined for reading command, reads and write 2 whens instruction when control interface receives in same clock cycle simultaneously, and moderator just can transfer to one-port memory with reading command earlier; After one-port memory finishes data read, will write instruction and transfer to one-port memory in second half is interim again, one-port memory can be write in the interim data of carrying out of second half.In other words, behind a time clock end cycle, the read/write instruction all is performed, has also just realized the function of multiport synchronous memory device in the equivalence.
In another embodiment of the present invention, the control interface of collocation one-port memory can be provided with the clock-pulse circuit of a frequency multiplication; When this control interface receives the triggering of external clock pulse and receives synchronously in the one-period in this outside time clock when reading and writing instruction, frequency doubling clock pulsing circuit in the control interface just can produce the internal clock pulse of a frequency multiplication according to this external clock pulse, and can make one-port memory read and to write instruction respectively by the running of this frequency multiplication internal clock pulse control one-port memory at the different cycles of internal clock pulse.Because the internal clock pulse frequency multiplication is in external clock pulse, the one-period of internal clock pulse only is half of external clock pulse one-period, so under the triggering of internal clock pulse, be exactly half to carry out reading and writing of data respectively before cycle of externally time clock in the one-port memory equivalence with later half, equally also externally finish reading and writing of data in the one-period of time clock, realize the function of multiport synchronous memory device.
In one-port memory, each storage unit of one-port memory only need be provided with single access port, so the cost of the layout area of one-port memory and the manufacturing all is lower than dual-ported memory.In general, each storage unit of single port static RAM can be formed by 6 transistors (being 6T) or 4 transistor 2 resistance of collocation (being 2R4T), the dual-port static random access storage unit then need form (2R6T) by 8 transistors (8T) or 2 resistance of 6 transistor collocation, so under identical memory capacity, the layout area of one-port memory, the cost of the manufacturing make the present invention to realize broad-spectrum double port synchronous memory device with cheaper cost, less layout area all less than dual-ported memory.
Description of drawings
What Fig. 1 illustrated is a typical double port synchronous memory device.
Fig. 2 is the sequential synoptic diagram of related signal when double port synchronous memory device operates among Fig. 1.
Fig. 3 is the function block schematic diagram of memory storage one embodiment of the present invention.
Fig. 4 is the sequential synoptic diagram of related signal when memory storage operates among Fig. 3.
Fig. 5 is the function block schematic diagram of another embodiment of memory storage of the present invention.
Fig. 6 is the sequential synoptic diagram of related signal when memory storage operates among Fig. 5.
Fig. 7 is the circuit diagram of storage unit in single port and the dual-ported memory.
The reference numeral explanation
10 double port synchronous memory devices, 20,40 memory storages
22,42 control interfaces, 24,46 one-port memories
26 moderators, 28,58 handover modules
30,50 address transfer modules, 32,52 locking module
34A-34B, 60A-60B delayer
48 gate generator 54A-54B sequential cells
The 62-64 storage unit
Wr, rd, WAD, RAD, MDI, MDO, swr, srd, sAD, sD signal
Ar, Aw address D r, Dw data
T, T2 cycle Inv phase inverter
T0-t1, ta-tb, tr, tw time point
Q1-Q4, K, M transistor CK, CK2 time clock
Embodiment
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of a typical double port synchronous memory device 10; Double port synchronous memory device 10 can be a static random access memory device, and it can be by outside receive clock pulse CK, signal wr, rd, WAD, RAD and MDI, and output signal MDO.Wherein, time clock CK is used for triggering the time sequences of double port synchronous memory device 10.Signal wr and rd then are respectively and write and read enable signal, when the level of these two signals changes high level into by low level, will carry out writing and reading of data to double port synchronous memory device 10 with regard to representing respectively.In other words, when signal wr or rd are enabled to high level, just be equivalent to send an instruction of reading or writing to double port synchronous memory device 10.When signal wr is enabled and when requiring that data are write to double port synchronous memory device 10, also can synchronously transmits an address information among the signal WAD, which address indication double port synchronous memory device 10 will write to data; The data that write then can transfer to double port synchronous memory device 10 in signal MDI.On the other hand, when signal rd is enabled and requires data are read in by double port synchronous memory device 10, signal RAD also can synchronously transfer to double port synchronous memory device 10 with an address information, double port synchronous memory device 10 is read the data of this address, and the data of reading are output among the signal MDO.
As discussed earlier, one of function of double port synchronous memory device is exactly to want synchronously to finish reading and writing of data in same clock cycle.Please refer to Fig. 2 (and in the lump with reference to figure 1); Fig. 2 is double port synchronous memory device 10 and finishes data read/the write sequential synoptic diagram of fashionable related signal waveform synchronously; The transverse axis of Fig. 2 is the time.As shown in Figure 2, in the same period T of time clock CK, signal wr, rd are enabled to high level in time point t0 simultaneously, just want double port synchronous memory device 10 to carry out data read simultaneously and write.Along with signal wr, rd are promoted to high level, also can synchronously transmit an address Aw and an Ar, the address that designation data writes/reads respectively among signal WAD, the RAD; And in signal MDI, the data Dw that be written into address Aw also can be transferred to double port synchronous memory device 10 simultaneously.When the one-period of time clock CK T when time point t1 finishes, double port synchronous memory device 10 should write to address Aw with data Dw, and the data Dr of address Ar can be read and be output in signal MDO, and data Dr can be obtained in by signal MDO at time point t1.
One of fundamental purpose of the present invention, to utilize one-port memory to realize desired dual-port synchronous access sequential among Fig. 2 exactly, just utilize one-port memory and can in same clock cycle, receive the instruction of read/write synchronously, and the requirement that can in same clock cycle, finish data read and write.Please refer to Fig. 3, Fig. 3 is the function block schematic diagram of memory storage one embodiment 20 of the present invention.Memory storage 20 is the functions that realize double port synchronous memory device with a control interface 22 collocation, one one-port memories 24 (it is a single port static RAM).As discussed earlier, one-port memory only can carry out single data read in fact at one time or write; And the one-port memory 24 among Fig. 3 just only can receive single address signal sAD, also only can transmit single data and export into signal sD.When signal swr was enabled, one-port memory 24 can write to the address of transmitting among the signal sAD with the data among the signal sD; And when signal srd was enabled, one-port memory 24 can be read data according to the address of transmitting among the signal sAD by this address, and was output in signal sD.Because all by same port (same signal) transmission, so the circuit structure of one-port memory 24 is simple, cost and layout area are all lower for the address of read/write and data, but its enable signal swr, srd of writing/reading can not be enabled simultaneously.
For making one-port memory 24 also can realize out the function of dual-port memory storage, control interface 22 of the present invention will suitably be converted to standard external signal rd, wr, WAD, RAD, MDI and the MDO of double port synchronous memory device exactly that one-port memory can receive controls signal swr, srd, sAD and sD.In the embodiments of figure 3, address transfer module 30, handover module 28 and a locking module 32 that is provided with a moderator (arbitrator) 26, two delayer 34A, 34B in the control interface 22 and is controlled by moderator 26.Wherein, moderator 26 can be considered a selection module; When moderator 26 receives the signal wr of activation simultaneously and rd by the outside, can select one of them signal earlier according to default right of priority, and with its prioritised transmission to one-port memory 24.For instance, moderator 26 can make signal rd have higher right of priority; When signal rd and wr by the while activation during to high level, moderator 26 just can preferentially allow the reading command of signal rd representative be transferred to one-port memory 24 earlier, next again transmission signal wr representative write instruction.The result who cooperates moderator 26 to arbitrate in read/write instruction synchronously, 30 of address transfer modules can enter the address among address signal RAD, the WAD to signal sAD in regular turn.If reading command is preferential, address transfer module 30 also can enter the address of reading among the signal RAD to signal sAD earlier; Will will write instruction when transferring to one-port memory 24 Deng moderator 26, address transfer module 30 also will be switched and change the address among the signal WAD is entered to signal sAD.In like manner, handover module 28 also can come the output of switch data to go into according to the arbitration result of moderator 26; If reading command preferentially is transferred to one-port memory 24 and is preferentially carried out, can be transferred to locking module 32 by the signal of exporting among the signal sD and be latched (latch); And when moderator 26 will with priority lower write instruction when transferring to one-port memory 24, the path that handover module 28 will the switch data transmission changes by the data transmission that will write among the signal MDI to signal sD.Can comprise one or more locks in the locking module 32 to latch/record data; In addition, each delayer 34A, 34B are used for the signal delay with moderator 26.
In other words, when outside signal wr, rd in same clock cycle during by activation simultaneously, moderator 26 can be selected one and successively carry out, and allows one-port memory 24 carry out data read/write one by one; In general, one-port memory 24 carries out the required time of read/write much smaller than a clock cycle, even the read/write of data is carried out one by one, still can in same clock cycle, successfully both be finished, also just finish the function of double port synchronous memory device in the equivalence.Realize the situation of dual-port stores synchronized access for further specifying memory storage 20, please further with reference to figure 4 (and in the lump with reference to figure 3); Fig. 4 is the sequential synoptic diagram of memory storage 20 of the present invention each related signal when carrying out the access of dual-port stores synchronized, and the transverse axis of Fig. 4 is the time.
As shown in Figure 4, at time point t0, to high level, representative will be carried out data in synchronization to memory storage 20 and read and write by the while activation for outside signal wr, rd.Simultaneously, data read/address Aw, Ar that writes and the data Dw that will write are also respectively at transferring to memory storage 20 among signal WAD, RAD and the MDI.When moderator 26 (Fig. 3) find signal wr at time point t0, when rd is enabled simultaneously, moderator 26 can preferentially allow reading command transmission earlier (suppose its be preset as read preferential), make signal rd can preferentially be transferred to one-port memory 24, just make level transitions among the signal rd preferentially be reflected in level transitions among the signal srd.Because the time delay that delayer 34A introduces between signal rd and signal srd, signal srd can postpone to change high level in time point ta.
When moderator 26 when time point t0 arbitration reading command is preferential, its arbitration result also can make address transfer module 30 preferentially the address Ar among the signal RAD be transferred among the signal sAD simultaneously.Simultaneously, handover module 28 also can switch to locking module 32, waits for the data of exporting among the signal sD.Arrived time point ta, address transfer module 30 should be can be stably transfers to the address Ar of data read among the signal sAD, also will make one-port memory 24 begin to carry out data read and time point ta changes the signal srd of high level into.Arrived time point tr, one-port memory 24 is finished data read, the data Dr of address Ar is read and is output in signal sAD, and the data Dr among the signal sAD will transfer to locking module 32 via handover module 28, by locking module 32 data Dr is latched, as the signal that will export among the signal MDO.
In other words, when memory storage 20 of the present invention synchronously receives outside when reading and writing instruction, be to select one by moderator 26 to carry out single reading and write one by one and control, make one-port memory 24 realize the function of synchronous dual-port memory storage with the one-port memory that utilizes low cost, little layout area in preceding half and the later half data read/write of carrying out respectively of same clock cycle.Certainly, memory storage 20 is if only receive the single instruction of reading or write in same clock cycle, and moderator 26 just can directly read this or write to instruct and transfer to one-port memory 24, directly carries out reading or writing of data.That is to say that in the one-period of time clock, no matter be that data read, data write or synchronous reading and writing, memory storage 20 can both correct carrying out, be as good as with the function of double port synchronous memory device.By also finding out among Fig. 4, in memory storage 20, the handoff functionality of address transfer module 30 and handover module 58 also can directly be controlled by time clock CK, in the preceding semiperiod of one-period (just when time clock CK is maintained high level), address among the address transfer module 30 transmission signal RAD, later half cycle (when time clock CK is maintained low level), the address among the address transfer module 30 transmission signal WAD.In like manner, handover module 58 also can switch running according to time clock CK.In order successively to arbitrate the right of priority of read/write instruction in the same one-period of time clock CK, moderator 26 can work in the time clock of upper frequency, and just frequency is higher than the time clock of time clock CK.
The single port synchronous memories can receive in the one-period of time clock and single read or write instruction and carry out data read or write.In the second embodiment of the present invention, the single port synchronous memories that just can utilize frequency multiplication to trigger is realized double port synchronous memory device.Please refer to Fig. 5; Fig. 5 is the function block schematic diagram of memory storage second embodiment 40 of the present invention.Be to cooperate an one-port memory 46 to realize the function of double port synchronous memory device in the memory storage 40 with control interface 42; Wherein, be provided with gate generator 48, delayer 60A and 60B, two sequential cell 54A, 54B, an address transfer module 50, all die change pieces 58 and a locking module 52 of a frequency multiplication in the control interface 42.Wherein, gate generator 48 can be a phase-locked loop (phase lock loop), is used for producing according to time clock CK the time clock CK2 of a frequency multiplication; That is to say that the cycle of time clock CK2 is half of cycle of time clock CK.Time clock CK2 promptly is used for triggering the time sequences of one-port memory 46.Under the triggering of time clock CK2, one-port memory 46 can receive one by signal srd or swr and read or write instruction in the one-period of time clock CK2, by the address that receives data read/write among the signal sAd, and the data that read or write by output among the signal sD or input.
In control interface 42, sequential cell 54A, 54B can select whether signal wr, the rd of outside will be transferred to delayer 60A, 60B with signal swr0, srd0 respectively according to the level variation of time clock CK and produce corresponding signal swr and srd.When practical operation, sequential cell 54A, 54B can use with door (AND gate) and realize.When outside signal wr, rd in the same one-period at time clock CK by activation simultaneously during to high level, sequential cell 54A can do time clock CK and signal rd and computing, allows the high level of signal rd be transmitted delayer 60A in the preceding semiperiod of time clock CK (just time clock CK is maintained the preceding semiperiod of high level); Sequential cell 54B then can do anti-phase (via the phase inverter inv anti-phase) of time clock CK and computing with signal wr, allows the high level of signal wr transfer to delayer 60B in the later half cycle of time clock CK (being exactly that time clock CK is maintained the low level later half cycle).In other words, sequential cell 54A, 54B can select the function of module to realize one respectively in preceding semiperiod and the later half cycle activation of time clock CK, and the instruction of reading and write synchronous among signal wr and the rd is transferred to signal swr0 and srd0 one by one.The function of address transfer module 50, handover module 58 and locking module 52 then is similar to the identical respective modules of title in the memory storage 20.
Please refer to Fig. 6 (and in the lump with reference to figure 5); The synoptic diagram of related signal sequential when Fig. 6 carries out the synchronous dual-port data access for memory storage 40, the transverse axis of Fig. 6 is the time.As shown in Figure 6, cooperate the one-period T of time clock CK, it is high level that outside signal rd, wr begin by activation synchronously at time point t0, to require memory storage 40 to carry out data read simultaneously and to write.Cooperate the running of sequence module 54A, signal srd0 can become high level with signal rd in the preceding semiperiod of time clock CK, just sends an instruction of reading to one-port memory 46 in the equivalence.Cooperate the triggering of time clock CK, in the preceding semiperiod of time clock CK, address transfer module 50 also can be transmitted in signal sAD with the address Ar that reads among the signal RAD, and handover module 58 also can switch to locking module 52.Because one-port memory 46 operates on the time clock CK2 of frequency multiplication, so concerning one-port memory 46, the signal srd that delayer 60A delay signal srd0 is produced is exactly the reading command of coming in period T 2 synchronous drivings of time clock CK2, and the address Ar among the signal sAD also is the data address of coming in time clock CK2 synchronous driving, so one-port memory 46 just can be finished reading of data in the one-period T2 among the time clock CK2 (the preceding semiperiod of time clock CK just), the data Dr of address Ar is read, transfer to locking module 52 via handover module 58, and data Dr is latched as exporting outside signal MDO to by locking module 52.
Arrived time point tb, the back half period of time clock CK just, sequential cell 54A can stop signal rd is transmitted in srd0, relatively, sequential cell 54B then can activation, and the high level among the signal wr is reacted to the high level of signal swr0, and produces the signal swr that postpones via delayer 60B.Simultaneously, 50 of address transfer modules change the address Aw that writes among the signal WAD are transmitted among the signal sAD, and handover module 58 also switches to signal MDI, and the data Dw among the signal MDI is transferred among the signal sD.Because the later half cycle of time clock CK is exactly another cycle of time clock CK2 in fact, so concerning one-port memory 46, it is to receive another by signal swr to write instruction in the new cycle of time clock CK2, and one-port memory 46 will write to address Aw with data Dw in this new period T 2.Arrived time point t1, the one-period T of time clock CK finishes, and concerning one-port memory 46, time clock CK2 has passed through two period T 2, has just carried out a data read and a secondary data one by one and write in each period T 2.In the equivalence, just in the one-period T of time clock CK, synchronously finish data read and the requirement that writes, realized the function of double port synchronous memory device.
Please refer to Fig. 7, what Fig. 7 illustrated is the circuit structure of the storage unit of one-port memory and dual-ported memory.Storage unit 62 is the storage unit of one-port memory, and it can store one data.As shown in Figure 7, storage unit 62 can be formed by transistor Q1 to Q4 and two transistor M; Transistor Q1 to Q4 forms the main circuit of data storage, and transistor M then is the access control transistor of access port, and whether be used for control store unit 62 can be in data transmission link D, D ' transmitting data.And the present invention is exactly the function that realizes out double port synchronous memory device with the formed one-port memory of single port storage unit.In comparison, known technology will could be realized out double port synchronous memory device with dual-ported memory; As shown in Figure 7, the storage unit 64 of dual-port needs to form with 8 transistors, and except transistor Q1 to Q4, storage unit 64 also will have four transistor M and K to manage two access ports of this storage unit.Wherein, whether two transistor M are used for control store unit 64 can be from data transmission link D1, D1 ' transmitting data, and can other two transistor K then are used for control store unit 64 from data transmission link D2, D2 ' transmitting data.By Fig. 7 more as can be known because the present invention can realize the function of double port synchronous memory device with one-port memory, so can significantly reduce the layout area of double port synchronous memory device, the cost of reduction double port synchronous memory device.
Generally speaking, the present invention is when realizing synchronous data access, be that the instruction of reading and write that receives synchronously in same clock cycle is handled in regular turn one by one, in same time clock, finish the data access requirement one by one, so just can realize the function of dual-port memory storage with one-port memory, reduce time and cost that the dual-port memory storage is manufactured, reduce the layout area of dual-port memory storage.In the memory storage 20 and 40 of aforementioned discussion, be afterwards to be written as example embodiments of the present invention are described, but the present invention can certainly write earlier again and read to read earlier.In addition, technical spirit of the present invention can be promoted and realize M port synchronous memory device, for instance, make memory storage 40 produce the time clock CK2 of M frequency multiplication, the frequency of enable clock pulse CK2 is M a times of time clock CK1, cooperate suitable address transfer module and handover module, just can realize M port synchronous memory device with one-port memory.In memory storage 20 and 40, the function available hardware circuit or the firmware of each module are realized; For instance, the function of address transfer module and handover module can realize with one or more multiplexers.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (6)
1. realize the method for a dual-port synchronous memory device with a storer for one kind, it includes:
Receive a reading command, this reading command is will be by reading data in this storer;
When receiving this reading command, receive one synchronously and write instruction; This writes instruction is data will be write to this storer;
When receiving this reading command and this and write instruction, carry out one and select step, in same clock cycle, successively execute this two instructions according to default right of priority, from these two instructions, select an instruction earlier and also carried out, after executing the instruction of selecting, carry out another instruction again; And
If when carrying out this selections step, select this reading command of execution earlier, then carry out a lock step writing down the data that this reading command is read,
Wherein, this storer is an one-port memory.
2. method as claimed in claim 1, it also includes:
When receiving this reading command, receive one synchronously and read the address, this reading command is to read data by the address of reading in this storer; And
When receiving this and write instruction, receive one synchronously and write the address, this writes instruction is data will be write in this storer this to write the address.
3. method as claimed in claim 1, it also includes:
Receive a time clock, a plurality of cycles are arranged in this time clock;
And when synchronously receiving this reading command and this and write instruction, be in same clock cycle, to receive this reading command and this writes instruction.
4. a memory storage, it includes:
One one-port memory is used for storage data; And
One control interface, it can receive one synchronously and write an instruction and a reading command, wherein this to write instruction be data will be write to this one-port memory, and this reading command is will be with data by reading in this one-port memory, and this control interface includes:
One selects module, when this control interface receives this reading command and this and writes instruction, this selection module can make this one-port memory successively execute this two instructions in same clock cycle, from these two instructions, select earlier an instruction earlier and make this one-port memory carry out this instruction, after executing the instruction of selecting, this selection module can make this one-port memory continue to carry out another instruction, wherein include a moderator in this selection module, be used for according to a right of priority of presetting preferentially from these two instructions, to select an instruction earlier;
One locking module, if this selects module to select to carry out earlier this reading command, then this locking module can write down the data that this reading command is read.
5. memory storage as claimed in claim 4, wherein this control interface is when receiving this reading command, also can receive one synchronously and read the address, this reading command is to read data by the address of reading in this one-port memory, and when this control interface when receiving this and writing instruction, also can receive one synchronously and write the address, this writes instruction is data will be write in this one-port memory this to write the address.
6. memory storage as claimed in claim 4, wherein this control interface also can receive a time clock, a plurality of cycles are arranged in this time clock, and this control interface being when synchronously receiving this reading command and this and write instruction, is to receive this reading command and this writes instruction in same clock cycle.
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| CNB2004101021139A Active CN100388252C (en) | 2004-12-14 | 2004-12-14 | Method for realizing double port synchronous memory device and related apparatus thereof |
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| US9105318B2 (en) | 2013-06-07 | 2015-08-11 | Industrial Technology Research Institute | Memory device and method operable to provide multi-port functionality thereof |
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| CN101877242B (en) * | 2009-04-30 | 2013-03-13 | 旭曜科技股份有限公司 | SRAM (Static Random Access Memory) compatible embedded DRAM (Dynamic Random Access Memory) device with hiding and updating capacity and double-port capacity |
| CN102571314B (en) * | 2012-02-02 | 2015-11-18 | 矽恩微电子(厦门)有限公司 | A kind of SPRAM full-duplex communication control circuit |
| CN103336750B (en) * | 2013-07-10 | 2015-10-28 | 广西科技大学 | Addressing dual-port memory controller integrated with storage unit |
| CN103886887B (en) * | 2014-03-31 | 2017-05-31 | 西安紫光国芯半导体有限公司 | A kind of dual-port static random access memory of use single-port memory cell |
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| CN110097902B (en) * | 2019-04-15 | 2021-01-29 | 中科亿海微电子科技（苏州）有限公司 | Read-write control module and method for same port and dual-port memory |
| CN113900580A (en) * | 2020-07-06 | 2022-01-07 | 旺宏电子股份有限公司 | Memory device, electronic device and reading method related to memory device |
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