CN100385681C - 半导体装置与其制造方法 - Google Patents

半导体装置与其制造方法 Download PDF

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CN100385681C
CN100385681C CNB2004100868434A CN200410086843A CN100385681C CN 100385681 C CN100385681 C CN 100385681C CN B2004100868434 A CNB2004100868434 A CN B2004100868434A CN 200410086843 A CN200410086843 A CN 200410086843A CN 100385681 C CN100385681 C CN 100385681C
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CN1612357A (zh
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葛崇祜
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置，包括：一基底、一第一外延层、一第二外延层、一第三外延层、一第一沟槽与一第二沟槽。该第一外延层位于该基底上且与该基底晶格失配。该第二外延层位于该第一外延层上且与该第一外延层晶格失配。该第三外延层位于该第二外延层上且与该第二外延层晶格失配，因此，该第三层可为应变硅。该第一沟槽延伸过该第一外延层。该第二沟槽延伸过该第三外延层且至少部分延伸过该第二外延层，至少部分该第二沟槽与至少部分该第一沟槽对准，以及该第二沟槽至少部分填入一绝缘材料。

Description

半导体装置与其制造方法
技术领域
本发明是有关于一种半导体装置的制造，且特别有关于一种应变硅结构。
背景技术
互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，简称CMOS)技术是目前用在制造超大规模集成电路(Ultra-Large ScaleIntegrated，简称ULSI)主要的半导体技术。在过去数十年中，金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)的尺寸缩小，使速度效能、电路密度与每单位半导体芯片的功能成本提供了重大的改善。当CMOS组件成比例缩小到100nm以下范围时，面临到重大挑战。一个可额外改善CMOS晶体管效能的方法，就是利用应变引起带结构变形与迁移率增加以增加晶体管组件电流。在二维拉伸应力下，硅的电子与电洞迁移率提高可达成。提高电子与电洞迁移分别改善了N沟道与P沟道的驱动电流，在应变硅中，电子可经更小的电阻且流动快了70％，此可使芯片无须进一步藉晶体管尺寸缩小就快了35％。
如图1A所示，晶体管应变硅层的制造有许多设计，如利用缓冲层或复合多层结构于块体硅基底20上，应变硅基底技术常利用微米级厚度的硅锗(silicon germanium，SiGe)变形缓冲层22，一无应变硅锗层24覆盖变形缓冲层22，该无应变硅锗层24具有比硅较大的自然晶格常数，由于无应变结晶硅与无应变结晶硅锗具有不同的晶格常数，故为晶格失配，因为硅薄层26的晶格被迫与无应变硅锗层24的晶格对齐，硅薄层26处于二维拉伸应力下磊晶地成长于无应变硅锗层24上，如图1B与图1C所示。再次参阅图1A，一晶体管28形成于硅层26上，此晶体管28包括一源极30、一漏极32与一栅极34，晶体管制造于应变硅层26上可增进电效能，又如图1A所示，晶体管28通常被一隔离区36所包围住(如浅沟隔离(Shallow Trench Isolation，简称STI)、硅的区域氧化(Local Oxidation of Silicon，简称LOCOS)、场氧化物(Field Oxide，简称FOX))。
变形硅锗缓冲层22与其下的硅基底20的晶格失配，可能会造成分散的、三维的差排网状结构，促使穿越差排38的应变缓和滑移，产生在变形缓冲区22上的差排可能传送到晶片表面，造成缺陷密度至每平方公分104-105个缺陷的程度，如此高的缺陷密度可能使利用此基底来生产集成电路产生重大障碍，也会使变形区下方的差排产生交叉排线表面的粗糙，此表面粗糙会是一个重大的问题，它会使主动区的沟道迁移率下降，因此，需要一个方法来降低应变是基底结构的缺陷密度。
发明内容
上述的问题与需要可藉由本发明的实施例解决。根据本发明的目的，提供一种半导体装置，包括一基底、依第一外延层、一第二外延层、一第三外延层、一第一沟槽与一第二沟槽。该第一外延层形成于该基底上，此第一层与此基底晶格失配；该第二外延层形成于该第一层上，且此第二层与第一层晶格失配；该第三外延层形成于该第二层上，且此第三层与第二层晶格失配；该第一沟槽延伸过第一层；该第二沟槽延伸过第三层且至少部分穿过第二层；至少部分第二沟槽与至少部分第一沟槽对准，且第二沟槽至少部分填入一绝缘材料。
根据本发明的另一目的是提供一种半导体装置的制造方法，此方法包括下列步骤，且此步骤的顺序可变化。一基底被提供；一第一外延层形成于该基底上，此第一层与基底晶格失配；一第一沟槽形成于上述第一层中；一第二外延层形于于上述第一层上，此第二层与第一层晶格失配；一第三外延层形成于上述第二层上，此第二层与第三层晶格失配；一第二沟槽形成于上述第三与第二层中，至少部分第二沟槽与至少部分第一沟槽对准。
根据本发明的另一目的是提供一种制造半导体装置的方法，此方法包括下列步骤，且此步骤的顺序可变化。一基底被提供；一第一外延层形成于上述基底上，此第一层与基底晶格失配；一第二外延层形成于上述第一层上，此第二层与第一层晶格失配；一第一沟槽形成于第二与第一层中；一第三外延层形成于第二层上，此第三层与第二层晶格失配；一第二沟槽形成于第三与第二层中，至少部分第二沟槽与至少部分第一沟槽对准。
附图说明
图1A为一剖面图，用以说明习知形成于应变硅基底上的晶体管；
图1B与图1C说明在二维张力下形成一硅层的方法；
图2-图7说明本发明实施例1的形成步骤；以及
图8-图11说明本发明实施例2的形成步骤。
符号说明：
20、42～基底                   22～变形缓冲层
24～无应变硅锗层               26～硅层
28～晶体管                     30～源极
32～漏极                       34～栅极
36～隔离区                     40～第一层
44～第一沟槽                   46～第一层与基底的界面
48～第一层的上表面             50～第二层
52～第二层材质填入第一沟槽中的部分
54～第二层的悬壁            56～第二层的上表面
60～第三层
62～第三层材质填入第一沟槽中的部分
64～第二沟槽                68～绝缘材料
72～第一层与第二层的界面
具体实施方式
为使本发明的上述和其它目的、特征和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下：
图2-图11显示本发明两个实施例的流程步骤。本发明实施例提供一种降低缺陷密度来改善应变硅结构的方法，如与先前设计比较(请参阅图1A)，在本发明的实施例中，达成降成缺陷密度的主要机制之一就是为晶粒界面提供自由表面，使排差经由这些自由表面移除；藉由在远离沟道区处(晶体管将要存在的地方)策略性地设置这些自由表面，可使差排被移离沟道区(及朝向或至自由表面)，下列所述的两个实施例将说明本发明实施例如何提供此自由表面且降低沟道区的缺陷密度。
图2-图7显示一本发明实施例1的流程步骤，首先于图2中，第一晶格失配外延层40形成在基底42上，在此例中，基底42为硅(即硅晶片)且第一层40为SiGe缓冲层，第一层40较佳为与基底42晶格失配。
接下来如图3所示，第一沟槽44形成在第一层40中，在图3里，显示了第一沟槽44的两个部分，此第一沟槽44的平面可依主动区的布局而改变，而第一沟槽44的深度与宽度也可依需要做改变，在此例中(图3)，第一沟槽44延伸过第一层40且进入第一基底42中，较佳为第一沟槽44延伸过第一层40与基底42的界面46；在其它实施例中(未显示)，第一沟槽44可以只部分延伸过第一层40或延伸过第一层且未延伸到基底42。
在形成第一沟槽44后，第一层40可经退火处理，此退火温度比形成第一层40的沉积温度还要高约100℃，退火处理第一层40可移除在第一层40结晶结构的排差或缺陷，且/或可造成第一层40内部排差移到或向一自由表面(即第一沟槽44)；第一层40的上表面48可被平坦化(在形成第一沟槽44前或后)，而后于其上再形成第二层50(随后讨论)，此平坦化可利用任何合适的平坦化制程，如化学机械研磨(CMP)，若第一层40经退火处理，较佳在退火之后再行一平坦化，此平坦化也可在退火之前进行；在其它实施例中，第一层40的退火与/或第一层40的平坦化可不进行。
如图4所示，形成第二晶格失配外延层50于第一层40上，此第二层50为一无应变的SiGe层；如图4所示，第二层50的材质可部分填入第一沟槽44中(请参阅图4中的52部分)；另外，第一沟槽44可先填入或部分填入其它材质(即绝缘材质)(未显示)，然后再于第一层40上形成第二层50；在此例中，虽然第一沟槽44在形成第二层50后依留有开口(请参阅图4)，且延伸向上过第二层50，但第一沟槽依44可能被第二层50所封闭，此情况端视任何于第一沟槽44中的第二层材料悬壁54的形成与第一沟槽44的宽度，在此情形下，第一沟槽44保留其开口较佳但非必须。
如同第一层40，第二层50可经退火处理，此退火温度可比形成第二层50的沉积温度还要高约100℃，退火处理第二层50可移除在第二层50结晶结构的排差或缺陷，且/或可造成第二层50内部排差移到或向一自由表面(即第一沟槽44)；第二层的上表面56在形成第三层60前(随后描述)可被平坦化；若第二层50经退火处理，最好在退火之后再行一平坦化，此平坦化也可在退火之前进行；在其它实施例中，第二层50的退火与/或第二层50的平坦化可不进行。
如图5所示，第三晶格失配外延层60形成于第二层50上，第三层60由于受第二层50与第三层60的晶格失配的影响，故为应变(处于二维张力)型态，在此例中，第三层60为处于二维张力下的应变硅(即请参阅第1C图)；如图5所示，第三层60的材料可部分填入第一沟槽44中(请参阅图5的62部分)，在此例中(请参阅图5)，虽然在形成第三层60后，但第一沟槽44依然留有开口，第一沟槽44依然可能被第三层60的形成所封闭，此情况端视任何于第一沟槽44中的第三层材料60悬壁的形成与第一沟槽44的宽度。
此第一与第二层40与50的厚度可分别约为2-3μm，而第三层60需够薄，如其厚度约为200埃，如此才不会于其中产生差排，若第三层60太厚，会因第二与三层50与60相异的晶格常数所造成的应力而产生裂缝或差排。如上所述，第一与第二层40与50可为SiGe层，在此例中，第二层50较佳具有比第一层40较高的锗浓度，以在彼此间形成一晶格失配区，如第一层40可为变形SiGe层。第一(40)、第二(50)与第三(60)层可不相同且各可由任何材料或材料组成/化合物所形成，例如(但不限于)：硅、锗、碳、半导体化合物与其组成。
虽然第一与第二层40与50各为单层，但其一或两者也可为复合层(即由多层来组成一层)，例如，第一层40可包括一变形组成层与一单一组成层；类似地，如第二层50包括一变形组成层与一单一组成层。基底42在本实施例中为一硅晶片，另外也可为一硅位于绝缘体上(SOI)结构(未显示)，或硅基底42包括一覆盖硅层的绝缘层(未显示)。熟习此技艺的人士应可了解本发明的实施例亦可应用许多其它可能材料或/与层组成。
在形成第一(40)、第二(50)与第三(60)层时，可利用任何外延层形成过程/技术(或其组成)，如包括(但不限于)：化学气相沉积(CVD)、MOCVD、HCVD、原子层沉积、应变硅分子束磊晶(SS-MBE)与上述的组合。
在图6中，第二沟槽64形成于第三与第二层60与50中，至少部分第二沟槽64与至少部分第一沟槽44对准(平行对准)，如图6所示，换句话说，第二沟槽64位于第一沟槽44上，然而，当第二沟槽64与第一沟槽44对准时，第二沟槽64并不需与第一沟槽44的中心一致；较佳为第二沟槽64与第一沟槽44对准且具有一深度，使第二沟槽64与第一沟槽44的开口连接。第二层的材质(即在第一沟槽44中的第二层50的悬壁部分54)是否会封闭住第二沟槽64底部的第一沟槽44，决于第二沟槽64在第二层50中的深度，如在一较佳的实施例中，第二沟槽64具有一约300埃的深度。
如图6所示的实施例，第二沟槽64延伸过第三层60且部分延伸过第二层50；在其它实施例里(未显示)，第二沟槽64可延伸过第二层50但未到第一层40；在另一实施例中(未显示)，第二沟槽64可延伸过第二层50且到第一层40，第二沟槽64的宽度最好比第一沟槽宽；在其它实施例中(未显示)，如第二沟槽64部分或全部的宽度可小于或等于第一沟槽44部分或全部的宽度，较佳为第二沟槽64的宽度与一般所使用的浅沟隔离(即请参阅图1A的STI 36)相等。
在图7中，第二沟槽64与部分未填满的第一沟槽44被填入一绝缘材料68，因此，被填满的第二沟槽64为一主动区的隔离区，也如图7所示，晶体管28形成，且部分晶体管28形成于第三层60上(即在此例中的应变硅层中)。
第一沟槽44提供一自由表面给差排，此可使缺陷移离晶体管28的沟道区，以消除或减少沟道区中的缺陷数目，如沟道区中的差排会产生漏电。第一沟槽44位于浅沟隔离(STI)区下方(即第二沟槽64)，使差排与/或缺陷移向浅沟隔离区下或中，由于浅沟隔离区中或下的缺陷一般并不会构成问题，且因它远离沟道区且一般并不会影响形成在主动区中组件的效能；再者，第一沟槽44越过第一与第二层40与50的接口72，此接口72的相对应力可降低或减少沟道区下的差排。
图8～图11显示本发明实施例2的流程步骤，图8～图11显示的实施例2与图2～图7所显示的实施例1类似，除第一沟槽44是在第二层50之后再形成(之前是在第二层50之前形成)外。首先在图8中，第一晶格失配外延层40(即SiGe层)形成于基底42(即硅晶片)上，第二晶格失配外延层50(即具有比第一层40高的Ge浓度的无应变的SiGe层)形成于第一层40上，第一层40可在第二层50于其上形成前经退火且/或平坦化处理(即实施例1所述)。
如图9所示，第一沟槽44形成在第二与第一层50与40中；如图9所示的实施例，第一沟槽44较佳延伸过第二层50、第一层40且延伸到基底42中；在其它实施例中(未显示)，第一沟槽44可延伸过第二层50且到第一层40中(但未到基底42中)；在此例中，第一沟槽44可延伸部分或整个第一层40。第二层50可在第三层60于其上形成前经退火且/或平坦化处理(即如实施例1所述)。
在图10中，一第三晶格失配外延层60(即硅)形成在第二层50上，第三层60因第二层50与第三层60间的晶格失配故为应变型态，第三层材料62可部分填入第一沟槽中，如图10所示。在图11中，一第二沟槽64与第一沟槽44对准形成(如实施例1所述)，且第二沟槽64被填入一绝缘材质68而形成一绝缘区，此绝缘材料68也可填入第一沟槽44中其余开口处，如图11所示。第二沟槽64可延伸进部分或整个第二层50；在其它实施例中(未显示)，第二沟槽64可延伸、部分延伸到与/或完全延伸过第一层40。如同图7，图11说明一晶体管28利用一应变硅结构。
在本发明的其它实施例中(未显示)，即如在实施例1与/或实施例2的多样化与/或额外步骤中，一沟槽可在第一层40形成于基底42上前形成在基底42中，当第一层形成时，此沟槽是否填入第一层40的材质取决于此于基底42的沟槽的深与宽，此位于基底42的沟槽最好够深且/或够宽，在第一层形成后，此沟槽就可延伸过第一层40(不管第一层材料的悬壁或填入)，第二层50也是，如图4。此揭露的好处在于熟习此技艺的人士可了解在本发明的实施例中，有许多其它可能材料或/与层组成。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求范围所界定者为准。

Claims (19)

1.一种半导体装置，包括：
一基底；
一第一外延层位于上述基底上，该第一外延层相对于上述基底晶格失配；
一第二外延层位于上述第一外延层上，该第二外延层相对于上述第一外延层晶格失配；
一第三外延层位于上述第二外延层上，该第三外延层相对于上述第二外延层晶格失配；
一第一沟槽延伸过上述第一外延层；以及
一第二沟槽延伸过上述第三外延层且至少部分延伸过上述第二外延层，以及该第二沟槽的宽度不等于该第一沟槽的宽度，至少部分该第二沟槽与至少部分上述第一沟槽对准，以及该第二沟槽至少部分填入一绝缘材料。
2.根据权利要求1所述的半导体装置，其中部分该第一沟槽延伸入至少部分该第二外延层或延伸入该基底中。
3.根据权利要求1所述的半导体装置，其中该第一沟槽至少部分填入该绝缘材料或至少部分填入该第二外延层的材料或至少部分填入该第三外延层的材料。
4.根据权利要求1所述的半导体装置，其中该第一外延层包括硅锗或锗。
5.根据权利要求1所述的半导体装置，其中该第二外延层包括无应变的硅锗或锗。
6.根据权利要求1所述的半导体装置，其中该第三外延层为应变硅或锗。
7.根据权利要求1所述的半导体装置，尚包括：
一晶体管形成于该第二沟槽邻近处且至少部分位于该第三外延层中。
8.一种半导体装置的制造方法，包括：
提供一基底；
形成一第一外延层于上述基底上，其中该第一外延层相对于上述基底晶格失配；
形成一第一沟槽于上述第一外延层中；
形成一第二外延层于上述第一外延层上，其中该第二外延层相对于上述第一外延层晶格失配；
形成一第三外延层于上述第二外延层上，其中该第三外延层相对于上述第二外延层晶格失配；以及
形成一第二沟槽于上述第三及第二外延层中，其中至少部分该第二沟槽与至少部分上述第一沟槽对准，该第二沟槽的宽度不等于该第一沟槽的宽度。
9.根据权利要求8所述的半导体装置的制造方法，其中该第一沟槽延伸至少部分过该第一外延层或延伸过该第一外延层且延伸入该基底中。
10.根据权利要求8所述的半导体装置的制造方法，其中该第二外延层的材料至少部分填入该第一沟槽。
11.根据权利要求8所述的半导体装置的制造方法，其中该第二沟槽与第一沟槽的开口连接。
12.根据权利要求8所述的半导体装置的制造方法，尚包括：
以一绝缘材料填入至少部分该第二沟槽；以及
若该第二沟槽开口向该第一沟槽且该第一沟槽未完全填满，以该绝缘材料填入该第一沟槽的开口剩余处。
13.根据权利要求8所述的半导体装置的制造方法，尚包括：
形成一晶体管于该第二沟槽邻近处，其中至少部分该晶体管形成于该第三外延层中。
14.根据权利要求8所述的半导体装置的制造方法，其中该第一外延层于一沉积温度沉积，且尚包括：
形成该第一沟槽后，于高于该沉积温度100℃的温度下对该第一外延层进行一退火。
15.一种半导体装置的制造方法，包括：
提供一基底；
形成一第一外延层于上述基底上，其中该第一外延层相对于上述基底晶格失配；
形成一第二外延层于上述第一外延层上，其中该第二外延层相对于上述第一外延层晶格失配；
形成一第一沟槽于上述第二与第一外延层中；
形成一第三外延层于上述第二外延层上，其中该第三外延层相对于上述第二外延层晶格失配；以及
形成一第二沟槽于上述第三及第二外延层中，其中至少部分该第二沟槽与至少部分上述第一沟槽对准，该第二沟槽的宽度不等于该第一沟槽的宽度。
16.根据权利要求15所述的半导体装置的制造方法，其中该第一沟槽延伸过该第二外延层且延伸入该第一外延层中或延伸过该第二与第一外延层且延伸入该基底中。
17.根据权利要求15所述的半导体装置的制造方法，其中该第二沟槽与第一沟槽的开口连接。
18.根据权利要求15所述的半导体装置的制造方法，尚包括：
以一绝缘材料填入至少部分该第二沟槽；以及
若该第二沟槽开口向该第一沟槽且该第一沟槽未完全填满，以该绝缘材料填入该第一沟槽的开口剩余处。
19.根据权利要求15所述的半导体装置的制造方法，尚包括：
形成一晶体管于该第二沟槽邻近处，其中至少部分该晶体管形成于该第三外延层中。
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002331077A1 (en) * 2001-08-13 2003-03-03 Amberwave Systems Corporation Dram trench capacitor and method of making the same
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
DE102004053307B4 (de) * 2004-11-04 2010-01-07 Siltronic Ag Mehrschichtenstruktur umfassend ein Substrat und eine darauf heteroepitaktisch abgeschiedene Schicht aus Silicium und Germanium und ein Verfahren zu deren Herstellung
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR101225816B1 (ko) * 2005-05-17 2013-01-23 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소한 변위 결함 밀도를 가지는 래티스 미스매칭된 반도체구조 및 디바이스 제조를 위한 관련 방법
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7186626B2 (en) * 2005-07-22 2007-03-06 The Regents Of The University Of California Method for controlling dislocation positions in silicon germanium buffer layers
CN101268547B (zh) 2005-07-26 2014-07-09 琥珀波系统公司 包含交替有源区材料的结构及其形成方法
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US7772635B2 (en) * 2005-10-27 2010-08-10 Micron Technology, Inc. Non-volatile memory device with tensile strained silicon layer
US7678630B2 (en) * 2006-02-15 2010-03-16 Infineon Technologies Ag Strained semiconductor device and method of making same
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US8154051B2 (en) * 2006-08-29 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. MOS transistor with in-channel and laterally positioned stressors
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
JP2010538495A (ja) 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション 多接合太陽電池
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
EP2415083B1 (en) 2009-04-02 2017-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US8716752B2 (en) * 2009-12-14 2014-05-06 Stmicroelectronics, Inc. Structure and method for making a strained silicon transistor
CN102456551A (zh) * 2010-10-21 2012-05-16 上海华虹Nec电子有限公司 外延生长方法
US8685816B2 (en) * 2012-06-11 2014-04-01 Globalfoundries Inc. Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures
US9945048B2 (en) * 2012-06-15 2018-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method
US9136343B2 (en) 2013-01-24 2015-09-15 Intel Corporation Deep gate-all-around semiconductor device having germanium or group III-V active layer
US9196709B2 (en) * 2013-02-01 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor regions in trenches
US9324632B2 (en) 2014-05-28 2016-04-26 Globalfoundries Inc. Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
US10274678B1 (en) * 2018-03-26 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming photonic devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1211826A (zh) * 1997-09-17 1999-03-24 日本电气株式会社 半导体器件
US20030030091A1 (en) * 2001-08-13 2003-02-13 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US20030049893A1 (en) * 2001-06-08 2003-03-13 Matthew Currie Method for isolating semiconductor devices
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
CN2751438Y (zh) * 2003-10-31 2006-01-11 台湾积体电路制造股份有限公司 半导体装置

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1040321A (en) * 1974-07-23 1978-10-10 Alfred C. Ipri Polycrystalline silicon resistive device for integrated circuits and method for making same
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5024723A (en) * 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5213986A (en) * 1992-04-10 1993-05-25 North American Philips Corporation Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
JP3321882B2 (ja) * 1993-02-28 2002-09-09 ソニー株式会社 基板はり合わせ方法
US5659192A (en) * 1993-06-30 1997-08-19 Honeywell Inc. SOI substrate fabrication
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5468657A (en) * 1994-06-17 1995-11-21 Sharp Microelectronics Technology, Inc. Nitridation of SIMOX buried oxide
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
JPH0832039A (ja) * 1994-07-12 1996-02-02 Nippondenso Co Ltd 半導体装置およびその製造方法
US5633588A (en) * 1994-09-16 1997-05-27 Hitachi Medical Corporation Superconducting magnet apparatus using superconducting multilayer composite member, method of magnetizing the same and magnetic resonance imaging system employing the same
FR2725074B1 (fr) * 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
JP3171764B2 (ja) * 1994-12-19 2001-06-04 シャープ株式会社 半導体装置の製造方法
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5882981A (en) * 1996-07-30 1999-03-16 Texas Instruments Incorporated Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
US5714777A (en) * 1997-02-19 1998-02-03 International Business Machines Corporation Si/SiGe vertical junction field effect transistor
JP2962272B2 (ja) * 1997-04-18 1999-10-12 日本電気株式会社 半導体装置の製造方法
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5985742A (en) * 1997-05-12 1999-11-16 Silicon Genesis Corporation Controlled cleavage process and device for patterned films
WO1998059365A1 (en) * 1997-06-24 1998-12-30 Massachusetts Institute Of Technology CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION
JP3443343B2 (ja) * 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
US6143070A (en) * 1998-05-15 2000-11-07 The United States Of America As Represented By The Secretary Of The Air Force Silicon-germanium bulk alloy growth by liquid encapsulated zone melting
US6558998B2 (en) * 1998-06-15 2003-05-06 Marc Belleville SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
JP3403076B2 (ja) * 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6258664B1 (en) * 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6355541B1 (en) * 1999-04-21 2002-03-12 Lockheed Martin Energy Research Corporation Method for transfer of thin-film of silicon carbide via implantation and wafer bonding
US6358791B1 (en) * 1999-06-04 2002-03-19 International Business Machines Corporation Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
US6516644B1 (en) * 1999-07-26 2003-02-11 Schlage Lock Company Method of master keying a system of locks
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
JP2003520444A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション 高温成長を不要とする低貫通転位密度格子不整合エピ層
TW452866B (en) * 2000-02-25 2001-09-01 Lee Tien Hsi Manufacturing method of thin film on a substrate
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
JP3528756B2 (ja) * 2000-05-12 2004-05-24 松下電器産業株式会社 半導体装置
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
US6466008B1 (en) * 2000-10-06 2002-10-15 Hewlett-Packard Company Method for matching the lengths of signal traces
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6410371B1 (en) * 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6410938B1 (en) * 2001-04-03 2002-06-25 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating
US6593181B2 (en) * 2001-04-20 2003-07-15 International Business Machines Corporation Tailored insulator properties for devices
US6358806B1 (en) * 2001-06-29 2002-03-19 Lsi Logic Corporation Silicon carbide CMOS channel
JP2005500690A (ja) 2001-08-13 2005-01-06 ハネウェル・インターナショナル・インコーポレーテッド オーバーレイヤーパターンを使用してウェハに担持された半導体デバイスの電流制御を提供すること
US7422961B2 (en) * 2003-03-14 2008-09-09 Advanced Micro Devices, Inc. Method of forming isolation regions for integrated circuits
US20040224469A1 (en) * 2003-05-08 2004-11-11 The Board Of Trustees Of The University Of Illinois Method for forming a strained semiconductor substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1211826A (zh) * 1997-09-17 1999-03-24 日本电气株式会社 半导体器件
US20030049893A1 (en) * 2001-06-08 2003-03-13 Matthew Currie Method for isolating semiconductor devices
US20030030091A1 (en) * 2001-08-13 2003-02-13 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
CN2751438Y (zh) * 2003-10-31 2006-01-11 台湾积体电路制造股份有限公司 半导体装置

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