CN100380636C - 用于整体成型组件的热增强封装及其制造方法 - Google Patents

用于整体成型组件的热增强封装及其制造方法 Download PDF

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CN100380636C
CN100380636C CNB038233193A CN03823319A CN100380636C CN 100380636 C CN100380636 C CN 100380636C CN B038233193 A CNB038233193 A CN B038233193A CN 03823319 A CN03823319 A CN 03823319A CN 100380636 C CN100380636 C CN 100380636C
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fin
substrate
tube core
molding composite
interconnective
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CN1685498A (zh
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丹尼尔·K.·劳
艾德华·L·T.·洛
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Advanced Interconnect Technology Ltd
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Abstract

给封装加入散热片(20)，以提高热性能及有利的电性能。在制造中，在接合后(例如导线或胶带键合或倒装片法键合)和阵列/整体成型前，将散热片前体(24)有利地设置到一组管芯上并固定。例如，封装条可以由一排(线性阵)管芯连接区组(例如以4×4矩阵形式)组成。散热片(20)可以沿封装条(10)容纳一个或多个这样的组。然后可以将封装条(10)切单，以形成单个的封装。每个切单的封装包括管芯(14)、其相关的衬底(16)(例如引线框或插板型衬底)以及作为散热片(20)的一部分散热片前体(24)。

Description

用于整体成型组件的热增强封装及其制造方法
相关申请的交叉参考
本发明要求2002年9月30日申请的美国临时专利申请No.60/415,189的利益，该申请在此结合作为参考。
技术领域
本发明涉及一种半导体器件封装。本发明尤其涉及热增强的模制塑料半导体器件封装。
背景技术
模制塑料封装为集成电路器件(管芯(die))提供外围保护。这样的封装典型地包括至少一个半导体器件(管芯)，其中所述的半导体器件带有电连接引线框型衬底或插板型衬底的输入/输出(I/O)焊垫，模塑复合物涂覆该器件以及至少部分衬底。典型地，利用导线键合、胶带键合或者倒装片键合法将该管芯上的输入/输出焊垫电连接衬底上的键合点。引线框型衬底或插板型衬底将输入/输出焊垫以及电路之间的电信号向外传输到封装。
在带有引线框型衬底的半导体器件封装中，电信号通过导电的引线框在至少一个管芯以及外部电路诸如印刷电路板之间传输。引线框包括多根引线，每根引线具有内部引线端以及相对的外部引线端。内部引线端电连接管芯上的输入/输出焊垫，外部引线端设置有连接外部电路的端子。外部引线端子端接在封装体的表面，该封装称作“无引线”封装。众所周知的无引线封装的实例包括无引线方形扁平(QFN)封装以及无引线双重扁平(DFN)封装，其中无引线方形扁平封装具有四组沿正方形封装体的底部周边设置的引线，无引线双重扁平封装具有两组沿封装体的底部相对侧设置的引线。
在带有插板型衬底的半导体器件封装中，电信号通过衬底在至少一个管芯以及外部电路诸如印刷电路板之间传输，其中所述的衬底包括通常是2或3薄层的多层绝缘材料，其上设置有电迹线、管脚、通道等。这种类型的衬底典型地用在网格阵列封装中，例如球栅阵列(BGA)封装、针栅阵列(PGA)封装、LGA(凸起栅格阵列)封装、精细球栅阵列(FBGA)封装、柔性球栅阵列(FxBGA)封装以及需要在封装上以合适的电路连接板节距(“栅格阵列”)设置的焊盘的其他类型的封装。在BGA和PGA型封装中，焊球、焊料突起或销针可以设置在焊盘上，以利于电路板连接。
在任一种模制塑料封装中，管芯工作产生的热量必须要除去，以维持其工作的安全。有些热量通过封装的绝缘组件诸如衬底和连接线部分而消散，剩余的热量由模塑复合物吸收。问题是模塑复合物是热的不良导体。因此，必须尝试改善模制塑料封装的散热性能。
增加模制塑料封装的散热性能的一个方法是在封装内部设置金属散热片。在一个通用的设计中，金属散热片设置在管芯的下方。例如，这样的散热片的实例提供在Mahulikar等的美国专利US5367196和US5608267，以及Parthasarathi的美国专利US5650663中，这些专利的全部内容在此引用一并提出。
在另一个通用的设计中，金属散热片设置在管芯的上方，使得管芯位于散热片和衬底之间。在该设计中，该散热片典型地包括向下正对的部分，该部分接触衬底或管芯或二者全部。向下正对的部分可以利用绝缘的粘结剂粘结衬底和/或管芯。这样的散热片典型地用作发散在比芯片大的区域上的整个密封剂中的热量。这样的散热片的实例提供在Guan等人的美国专利US6432742中。另一个这样的实例提供在Wang等人的美国专利US5977626中。不幸地，应用这种类型的散热片的封装的制造方法并不适合于装配较低成本的模制塑料封装所需的高水平的自动操作。
在Libre的申请号为US6432749的美国专利(‘749专利)中提供了使带有散热片的模制塑料封装的组装自动化的一个尝试，该专利的全部内容作为参照在此一并提出。该‘749专利描述了一种制造方法，其中以条状形式设置的散热片使多个封装同时被装配。散热片条设置在管芯和衬底的上方，模塑复合物设置在散热片、管芯和衬底的上方，使得密封剂材料的边缘与减小了横截面的柱状物相符合，其中该柱状物与相邻的散热片连接。然后将减小了横截面的柱状物截开以隔离该封装。其中衬底是引线框，该‘749专利中描述的是利用非传导粘结剂将散热片连接到引线框来防止短路。然而该方法用于自动化装配，该装配需要单独对封装进行模塑(也就是插槽成型(pocket molded))，以露出横截面柱状物，使其可以被切割。对每个封装使用单个模塑对于某些应用并不适合，因为其使得模塑工艺倾向于产生加工缺陷，例如单独的模塑相对于器件和衬底没有对齐。此外在’749专利中描述的方法需要使用不导电的粘结剂将散热片紧固在引线框上以防止电路短路。这是会产生缺陷的加工工艺中的另一个步骤。
因此，还需要一种热性能增强的模制塑料封装的自动加工方法，该方法并不需要复杂的加工步骤。
发明内容
本发明的目的就是提供一种能克服或减轻现有技术中上述的缺陷和不足的器件，其包括：具有通常相对的第一和第二表面的衬底，该衬底第一表面带有多个设置在其上的键合点(bond site)；具有通常相对的第一和第二表面的管芯，所述表面平行于衬底第一和第二表面，管芯第一表面具有多个设置在其上的输入/输出焊垫，输入/输出焊垫电连接键合点；密封该管芯和至少该衬底的第一表面的模塑复合物；以及至少部分嵌入在模塑复合物中的散热片。散热片具有外围切边部分，该外围切边部分与衬底和模塑复合物的相关外围切边部分对齐，并且没有凹进衬底和模塑复合物的相关外围切边部分。
该衬底可以是金属引线框，或者可以包括绝缘材料，所述绝缘材料具有设置在其上的第一导电体，第一导电体是从导电迹线、导电层、通道、管脚以及包括上述一种或多种的组合的至少其中之一选取的。一列第二导电体可以使衬底与外部电路电耦合，第二导电体是从焊球、焊料突起、焊剂、销针以及包括上述一种或多种的组合的至少其中之一中选取的。可以利用导线键合、胶带键合或倒装片法使管芯上的输入/输出焊垫与衬底上的键合点相连接。
在一个实施例中，散热片具有通常相对的第一和第二表面，所述的表面平行于管芯第一和第二表面。散热片第二表面由模塑复合物覆盖，散热片第一表面没有被模塑复合物覆盖。散热片可以包括从散热片第二表面伸出的突起，该突起与管芯接触。在另一个实施例中，散热片包括向下设置的支脚(leg)，其与衬底第一表面接触。散热片可以电连接该衬底。可选地，散热片完全与衬底分离。
在本发明的另一个方面，用于制造封装半导体器件的方法包括：将多个管芯设置在多个相互连接的衬底上；将多个管芯中的每个管芯上的输入/输出焊垫与多个相互连接的衬底中的相关衬底上的键合点电连接；将多个相互连接的散热片固定到多个管芯上；对多个管芯、键合点以及多个相互连接的散热片连续涂覆模塑复合物，并对其包覆成型，以形成多个相互连接的封装前体；以及对相互连接的封装前体进行切单，以提供多个封装。
在一个实施例中，多个相互连接的散热片包括向下设置的部分，该部分设置在多个相互连接的散热片的外围。将多个相互连接的散热片固定到多个管芯上包括将向下设置的部分设置在多个相互连接的衬底上，切单包括经由向下设置的部分切单，以提供具有完全与衬底隔开的散热片的封装。
本发明的一个或多个实施例的详细情况在下面的附图以及说明书中做了阐述。通过说明书、附图以及权利要求，本发明的其它的特征、目的以及优点将会显而易见。
附图说明
结合附图通过下面的详细描述，将会更加充分地理解本发明，其中相同部件的附图标记相同。
图1是本发明典型的带有插板型(interposer)衬底的封装条的横截面正视图；
图2是对图1中的条进行切单(singulate)得到的封装的横截面正视图；
图3是带有插板型衬底的封装条的另一实施例的横截面正视图；
图4是对图3中的条进行切单得到的封装的横截面正视图；
图5是本发明典型的带有引线框型衬底的封装条的横截面正视图；
图6是对图5中的条进行切单得到的封装的横截面正视图；
图7a是带有引线框型衬底的封装条的另一实施例的横截面正视图；
图7b是具有在管芯和散热前体之间设置的热传导材料的图7a中的封装条的横截面正视图；
图8a是对图7a中的条进行切单得到的封装的横截面正视图；
图8b是对图7b中的条进行切单得到的封装的横截面正视图；
图9是形成散热前体的相互连接的散热片阵列的俯视图；
图10是沿图9中的A-A部分截割得到的相互连接的散热片阵列的横截面正视图；
图11是沿图9中的A-A部分截割得到的包括有管芯接触突起的相互连接的散热片阵列的横截面正视图；
图12是形成散热前体的该相互连接的散热片阵列的另一实施例的俯视图；
图13是沿图12中的B-B部分截割得到的相互连接的散热片阵列的横截面正视图；
图14是沿图12中的B-B部分截割得到的包括有管芯接触突起的相互连接的散热片阵列的横截面正视图；
图15是形成散热前体的该相互连接的散热片阵列的另一实施例的俯视图；
图16是沿图15中的C-C部分截割得到的相互连接的散热片阵列的横截面正视图；
图17是沿图15中的C-C部分截割得到的包括有管芯接触突起的相互连接的散热片阵列的横截面正视图；
图18是在不同的加工阶段本发明的封装条的俯视图；
图19是沿图18中的D-D部分截割得到的封装条的横截面正视图；
图20是描述制造模制塑料封装的方法的流程图。
具体实施方式
参照附图1，在封装条10的截面正视图中，封装条10包括三个相互连接的封装前体12，每个封装前体包括管芯14，管芯14电连接衬底16，并涂覆有模塑复合物18。散热片20设置在管芯14的上方并部分地密封在每个封装前体12的模塑复合物18中。衬底16相互连接以形成部分衬底条22，散热片20相互连接以形成部分散热片前体24。散热片前体24包括向下设置的支脚26，其与衬底条22的边缘相耦合。
在封装条10的制造中，在管芯14已经电连接衬底条22之后并且在将模塑复合物18施加至散热片前体24、管芯14和衬底条22的一部分之前，将散热片前体24设置在管芯14之上。利用整体成型，模塑复合物18可以有利地施加于封装条10，其中模塑复合物18的连续涂覆使封装条10中的每个封装前体12包覆成型。将模塑复合物18处理完后，用诸如刀锯、冲压机、激光、水射流等将封装条10沿线28切割，以将封装前体12切单成单个的封装，其中一个封装如图2中的30所示。
如图2所示，每个切单的封装30包括电连接衬底条22的一部分(图1)和散热片前体24的一部分(图1)的管芯14，其中衬底条22的一部分形成封装30的衬底16，散热片前体24的一部分形成封装30的散热片20。散热片20至少部分地嵌入到模塑复合物18中，并具有外围切边部分32，该外围切边部分32分别与衬底16和模塑复合物18的相关外围切边部分34和36对齐，并且没有凹进衬底16和模塑复合物18的相关外围切边部分34和36。散热片20提高了封装30的温度，并有效地提高了封装30的电性能。此外，散热片20防护管芯14免受作用在封装30上的电磁力。
再次参照附图1，散热片前体24可以包括厚度减小的凹口区38，其设置在封装前体12的侧面。通过减少在切单过程中必须要切割的散热片前体24的厚度，厚度减小的凹口区38可以使封装前体12的切单容易。切单以后，凹口区38形成肩部，仍然嵌入在模塑复合物18中，如图2所示。模塑复合物18作用于该肩部，以使散热片20固定在模塑复合物18中。
在衬底条10中，向下设置的支脚26支撑封装条10中管芯14上方每个相互连接的散热片20。对封装前体12的切单使支脚26被除去，并导致封装30中的散热片20完全从衬底16分开。由于散热片20完全从衬底16分开，不需要现有技术的散热片设计中要用到的不导电的粘结剂，就确保了散热片20以及衬底16的电绝缘。
然而在许多封装设计中，将散热片20与衬底16电绝缘是有利的，在其它的应用中期望在散热片20和衬底16之间提供电连接。例如，可以预期通过将散热片20电连接与接地点相连的衬底16上的键合点而使散热片20电接地。为了这些应用的使用，可以使用散热片前体24的替换物，如图3所示。
在图3的实施例中，散热片前体24除了包括设置在散热片前体24周围的支脚26外，还包括向下设置的支脚52，其位于每个封装前体12之间。如线28所示，在支脚52与衬底条22相接触的部分对封装前体12进行切单，结果，在切单后，支脚52的部分仍然与每个衬底16相连接。
图4描述的是对图3中的封装条10切单后的一个封装54的横截面视图。如图4所示，每个支脚52粘结到形成在衬底16上的焊垫56上，以在其间形成电连接。优选地，支脚52用树脂粘结剂粘合在焊垫56上。
在图1-4的实施例中，管芯14上的每个输入/输出焊垫60和衬底16上的相关键合点62之间的电连接由导线键合或胶带键合来实现，其中导线64的一端或导电胶带(未示出)连接输入/输出焊垫60，导线64相反的一端连接键合点62。然而，应当认识到管芯14上的输入/输出焊垫60和衬底16上的相关键合点62之间的电连接可以可选择地通过倒装片型连接来实现，其中将管芯14倒装使得其输入/输出焊垫60可以直接与键合点62电连接。“直接”电连接意味着相互连接是通过倒装片法而不是使用插入导线键合或胶带键合来实现。合适的附件包括基本组分为从由金、锡和铅组成的组中选取的焊料。
在图1-4的实施例中，将衬底16描述为插板型衬底，其包括多个绝缘材料层，如图所示有3个薄层66，其上设有导电体72(例如迹线、管脚、通道等等)。导电体72端接在焊盘68上，焊盘68暴露在封装30或34的表面。另外的导电体70诸如焊锡珠、焊料突起、焊膏、销针等等可以连接到焊盘68上。电信号通过导线64、导电体72、焊盘68以及导电体70在管芯14的输入/输出焊垫60以及外部电路诸如印刷电路板之间传输。可以理解，本发明适用于带有插板衬底的模制塑料封装，本发明也适用于带有其它类型衬底的模制塑料封装。例如，图5-8描述的是带有引线框型衬底的模制塑料封装。
参照附图5，是带有金属引线框型衬底条22的封装条10的横截面正视图，该封装条包括三个相互连接的封装前体12，每个封装前体包括管芯14，管芯14电连接衬底16，并涂覆有模塑复合物18。衬底条22包括多个相互连接的引线框形式的衬底16。引线框型衬底16是由金属材料诸如铜或铜合金构成。每个衬底16包括管芯焊垫80以及多个与管芯焊垫80分隔开的引线28，管芯14粘附到管芯焊垫上。散热片20设置在管芯14的上方并部分地封装在每个封装前体12的模塑复合物18中，相邻的散热片20相互连接以形成散热片前体24。附图5的实施例中应用的散热片前体24实质上与附图1-4的实施例中描述的散热片前体24相似。
每根引线82具有内部引线端以及相对的外部引线端。键合点62形成在内部引线端，与管芯14上的输入/输出焊垫60电连接。外部引线端设有连接外部电路的焊盘68。引线82可以带有厚度减小的凹口区84，通过减少在切单过程中必须要切割的衬底16的厚度，厚度减小的凹口区84可以使封装前体12的切单容易。
在制造附图5的封装条10的过程中，在管芯14已经连接管芯焊垫80并且电连接引线82之后以及使用模塑复合物18之前，将散热片前体24设置在管芯14之上。利用整体成型，模塑复合物18可以有利地施加于封装条10上。将模塑复合物18处理完后，用诸如刀锯、冲压机、激光、水射流等将封装条10沿线28切割，以将封装前体12切单成单个的封装，其中一个封装如图6中的86所示。
如图6所示，每个切单的封装86包括散热片前体24(图5)的一部分，散热片前体24形成封装86的散热片20。散热片20至少部分地嵌入模塑复合物18中，并具有外围切边部分32，该外围切边部分32分别与衬底16和模塑复合物18的相关外围切边部分34和36对齐，并且没有凹进衬底16和模塑复合物18的相关外围切边部分34和36。与前述的实施例一样，散热片20提高了封装86的热性能以及便利的电性能。此外，散热片20防护管芯免受作用在封装86上的电磁力。
图7a和7b都是引线框型衬底的封装条的横截面正视图，其中管芯14电连接倒装型衬底。除了图7a和7b中的引线框型衬底16不包括管芯焊垫以及图7a和7b中的引线82在管芯14之下延伸以直接与输入/输出焊垫60电连接以外，封装条10基本上与图5中的封装条相似。与前述的实施例一样，用诸如刀锯、冲压机、激光、水射流等将封装条10沿线28切割，以将封装前体12切单成单个的封装。图7a描述的封装条10中的管芯14由模塑复合物18将其与散热片前体24隔开。除了在图7b的封装条10中散热片前体24是由一层具有比模塑复合物18的导热性高的材料连结到每个管芯上以外，图7b与图7a相同。例如，该材料层88可以是设置在管芯14的一层导热糊状物或一层金属材料。
如图8a和8b所示，每个切单的封装90包括直接和引线82电连接的管芯14。每个切单的封装90也包括散热片前体24(图7a和7b)的一部分，散热片前体24形成封装90的散热片20。散热片20至少部分地嵌入模塑复合物18中，并具有外围切边部分32，该外围切边部分32分别与衬底16和模塑复合物18的相关外围切边部分34和36对齐，并且没有凹进衬底16和模塑复合物18的相关外围切边部分34和36。与前述的实施例一样，散热片20提高了封装86的热性能以及电性能。在图8b的实施例中，设置在管芯14和散热片20之间的材料层通过增加管芯14和散热片20之间的热传导性，进一步增强了封装90的热性能。
用在图1、2以及5-8的实施例中的散热片前体24如附图9和10所示。散热片前体24包括多个相互连接的散热片20，每个散热片包括平坦的顶面92、相对的平坦的底面94以及肩部表面96，其中所述的肩部表面96围绕顶面92的周围延伸并凹陷入其中。每个散热片20通过一对连接杆98与相邻的散热片20相互连接。从图10所示的正视图中可以看出，连接杆98和肩部表面96形成了厚度减小的凹口区38。支脚26围绕散热片前体24的外围设置。可以看出，可以通过将散热片前体24的连接杆98形成图3和图4中所述的支脚52，来获得图3和图4的实施例中的散热片前体。
散热片前体24可以由其热传导性能比模塑复合物18大的一片任何材料构成。优选地，散热片前体24是金属，诸如铜、铝或者包含铜和铝中的一种或多种的合金。例如，当需要较高的热传导性时，优选使用铜和铜基合金，而当需要较轻重量的散热片时，优选使用铝或铝基合金。定义如下，术语“合金”指两种或多种金属混合物，或者含有某种非金属元素的一种或多种金属，与金属有关的术语“基”指的是包含至少50％重量百分比的特定元素的合金。每个散热片20的暴露在封装的顶部的部分，特别是顶部表面92，可以通过电镀金属诸如镍来防止氧化。也可以利用常规方法，例如用黑色氧化处理涂覆其表面，来对散热片20进行防锈和/或美学特性处理。
形成散热片前体24的该片导电材料优选地具有大约0.2mm至0.5mm的厚度，并且优选地大约为0.2mm至0.3mm。散热片前体24的特征包括连接杆98和支脚26可以通过使用任何已知的方法例如冲压、化学蚀刻、激光切割等来形成。通过弯曲将支脚26优选地形成为向下设置的形状。优选地利用控制减色法诸如化学蚀刻或激光切割来形成厚度减小的凹口区38。优选地充分蚀刻厚度减小的凹口区38来设置肩部96和连接杆98，它们的厚度大约在散热片20的厚度(例如顶部表面92和底部表面94之间的厚度)的25％至60％之间，更优选地界于该厚度的50％至60％之间。优选范围内的厚度在厚度减小的凹口区38内提供了充足的空间来接受模塑复合物18，其将散热片20固定在封装中，并减少了足够的金属量，使切单变得容易。
参照附图11，示出了散热片前体24的另一实施例，其中每个散热片20包括从底部表面94伸出的凸起100。当散热片20安装在封装中时，每个突起100与相关的管芯14接触，从而允许热量从管芯14直接传导到散热片20。可以利用环氧树脂、粘结剂等将散热片连接到管芯上。可以看出，具有突起的散热片可以用在图1-8的任一实施例中。
参照附图12和13，是散热片前体24的另一实施例。在图12的实施例中，散热片前体24包括多个相互连接的散热片20，每个散热片包括平坦的顶面92、相对的平坦的底面94以及肩部表面96，其中所述的肩部表面96围绕顶面92的周围延伸并凹陷入其中。每个散热片20通过凹进的平坦部分102与相邻的散热片20相互连接。从图13所示的正视图中可以看出，凹进的平坦部分102形成了厚度减小的凹口区38，其在切单中被切割。支脚26围绕散热片前体24的外围设置。多个通孔104设置在支脚26的贯通部分，其允许模塑复合物进入。
形成图12和13中的散热片前体24的该片导电材料优选地具有大约0.2mm至0.5mm的厚度，并且更优选地大约为0.2mm至0.3mm。散热片前体24的特征在于，诸如支脚26和通孔104可以使用任何已知的方法例如冲压、化学蚀刻、激光切割等来形成。通过弯曲使支脚26成形。优选地蚀刻肩部区域26将其厚度设置为散热片20的厚度(例如顶部表面92和底部表面94之间的厚度)的大约25％至60％之间，更优选地界于该厚度的50％至60％之间。优选范围内的厚度在厚度减小的凹口区38内提供了充足的空间来接受模塑复合物18，其将散热片20固定在封装中，并减少了足够的金属量，以使切单变得容易。如图14所示，图12和13中的散热片前体24也可以包括用于接触管芯14的凸起100。
参照附图15和16，是散热片前体24的另一实施例。在图15的实施例中，散热片前体24包括多个相互连接的散热片20，每个散热片包括平坦的顶面92、相对的平坦的底面94以及肩部表面96，其中所述的肩部表面96围绕顶面92的周围延伸并凹陷入其中。每个散热片20通过凹进的平坦部分102与相邻的散热片20相互连接。从图16所示的正视图中可以看出，图15和16的实施例对应图3中的散热片前体24，其中散热片前体24除了包括设置在散热片前体24的外围的支脚26外，还包括向下设置的支脚52，其设置在每个封装前体12之间。凹进的平坦部分102形成了支脚52的底部，其在切单中被切割。多个通孔104设置在支脚26和52的贯通部分，其允许模塑复合物进入。通孔104的数量和位置可以根据图15和16所描述的情形而变化，以设置支脚26和52的不同的图形，如果如图3和4所述，散热片20电连接衬底16，这种情况是必要的。
形成图15和16中的散热片前体24的该片导电材料优选地具有大约0.2mm至0.5mm的厚度，并且更优选地大约为0.2mm至0.3mm。散热片前体24的特征在于：诸如通孔104可以通过使用任何已知的方法例如冲压、化学蚀刻、激光切割等来形成。通过弯曲使支脚26和52成形。优选地蚀刻肩部26，将其厚度设置为散热片20厚度(例如顶部表面92和底部表面94之间的厚度)的大约25％至60％之间，更优选地界于该厚度的50％至60％之间。如图17所示，图15和16中的散热片前体24也可以包括用于接触管芯14的凸起100。
在上述的每个实施例中，封装条10和其相关的散热片前体24以及衬底条22被描述为具有三个相互连接的封装前体12列或矩阵。然而，可以看出，本发明适用于任何带有两个或多个相互连接的封装前体12数组或矩阵的封装条10。例如，图18和19描述了封装条10，该封装条构建成相互连接的封装前体的2×2的矩阵。
图18是在制造的不同阶段本发明的封装条10的实例的平面视图。图19是图18的封装条10的截面正视图，图20是描述用于制造模制塑料封装的方法118的流程图，其可以用于制造这里所述的任一实施例。在方法118中，利用任何常规的方法，诸如焊接、环氧树脂、双面胶带等(方法118的模块120)，将每个管芯14固定在衬底条22上。在将管芯14固定在衬底条22上后，单独将导线64连接到管芯14上的输入/输出焊垫60以及衬底条22上的键合点62之间(模块122)。可选地，利用倒装片法将输入/输出焊垫60电连接键合点62的时候，同步执行步骤120和122，每个管芯14和衬底条22之间的电连接也用于将管芯14机械连接在衬底上。
在使管芯14电连接衬底条22后，如果需要使散热片20连接每个封装中的管芯14，可将热传导材料88(图7b)应用到管芯的背面(模块124)。然后将散热片前体24设置在管芯14上，散热片前体24中的每个散热片20在其各自的管芯14上方排列，并且利用焊接、环氧树脂、双面胶带等，将散热片前体24上的支脚26结合到衬底条22(模块126)。
散热片前体24在适当位置后，利用整体成型方法将模塑复合物18涂覆封装前体12(模块128)。即，模塑复合物18的连续涂覆使封装前体12阵列中的每个封装前体包覆成型。如图18所示，每个散热片20的顶表面92保持从模塑复合物18露出。在将模塑复合物18处理完后，可以将该导电体阵列70(例如焊球、焊料突起、焊剂、销针等)接合到衬底条(模块130)。然后，利用任何常规方法，例如锯、冲压、激光或水射流，沿线28将封装前体12切单，以提供单个的封装(模块132)。可以看出，方法118可以包括不同的检验步骤、固化(curing)步骤、清洗步骤或者其它特殊封装设计中所必需的步骤。
消除了与现有技术的方法相关的一些复杂的加工步骤后，方法118提供了热增强的模制塑料封装的自动制造。例如，方法118允许使用整体成型技术来对封装条中的封装进行模塑。结果，本发明避免了现有技术的热增强模制塑料封装制造中所使用的单独模塑技术。此外，由于本发明的散热前体24并不需要粘接单个封装内的衬底，因此本发明消除了现有技术方法中的利用绝缘粘结剂将散热片固定到单个封装前体内的衬底的需要。
已经描述了本发明的多个实施例。然而，可以理解在不背离本发明的精神和范围下可以对本发明做出不同的修改。相应地，其它实施例也在下列权利要求范围之内。

Claims (25)

1.一种器件，包括：
带有相对的第一和第二表面的衬底(16)，该衬底(16)第一表面带有多个设置在其上的键合点(62)；
安装在衬底(16)的第一表面上的管芯(14)，该管芯(14)带有相对的第一和第二表面，所述表面平行于衬底(16)第一和第二表面，该管芯(14)第一表面具有设置在其上的多个输入/输出焊垫(60)，输入/输出焊垫(60)电连接键合点(62)；
密封该管芯(14)和该衬底(16)的至少第一表面的模塑复合物(18)；
散热片(20)，其至少部分嵌入在模塑复合物(18)中，并且具有沿着所述器件的整个外围边与衬底(16)和模塑复合物(18)的相关外围切边部分(34、36)都对齐的外围切边部分(32)，并且散热片(20)的该外围切边部分(32)没有凹进衬底(16)和模塑复合物(18)的相关外围切边部分(34、36)。
2.根据权利要求1的器件，其中散热片(20)具有相对的第一和第二表面，所述的表面平行于管芯(14)第一和第二表面，该散热片(20)第二表面由模塑复合物(18)覆盖，模塑复合物(18)没有覆盖散热片(20)第一表面。
3.根据权利要求2的器件，其中通过其热传导性比模塑复合物(18)的热传导性高的材料(88)将散热片(20)与管芯热连接。
4.根据权利要求2的器件，其中散热片(20)包括从散热片(20)第二表面伸出的突起(100)，该突起与管芯(14)接触。
5.根据权利要求1的器件，其中散热片(20)包括向下设置的支脚(52)，其与衬底(16)第一表面接触。
6.根据权利要求5的器件，其中散热片(20)电连接衬底(16)。
7.根据权利要求1的器件，其中散热片(20)完全与衬底(16)分离。
8.根据权利要求1的器件，其中散热片(20)包括设置在其内的通孔(104)，用于使散热片(20)和衬底(16)之间的模塑复合物(18)进入。
9.根据权利要求1的器件，其中衬底(16)是金属引线框。
10.根据权利要求1的器件，其中衬底(16)包括绝缘材料(66)，所述绝缘材料(66)具有设置在其上的第一导电体(72)，第一导电体(72)是从导电迹线、导电层、通道、销针以及包括上述一种或多种的组合的至少其中之一选取的。
11.根据权利要求10的器件，其进一步包括：
一列第二导电体(70)，其用于使衬底(16)与外部电路电耦合，第二导电体(70)是从焊球、焊料突起、焊剂、销针以及包括上述一种或多种的组合的至少其中之一选取的。
12.根据权利要求1的器件，其进一步包括：
多个导线(64)或导电胶条，每个导线(64)或导电胶条在管芯(14)第一表面上的输入/输出焊垫(60)以及衬底第一表面上的键合点(62)之间电连接。
13.根据权利要求1的器件，其中管芯(14)上的输入/输出焊垫(60)以倒装片法的方式直接电连接衬底(16)上的键合点。
14.一种用于制造封装半导体器件的方法，该方法包括：
将多个管芯(14)设置到多个相互连接的衬底(16)上；
将多个管芯中的每个管芯(14)上的输入/输出焊垫(60)与多个相互连接的衬底中的相关衬底(16)上的键合点(62)电连接；
将多个相互连接的散热片(20)固定到多个管芯(14)上；
通过对多个管芯(14)、键合点(62)以及多个相互连接的散热片(20)的连续并不中断的模塑复合物(18)涂覆来包覆成型，以形成一块相互连接的封装前体(12)；以及
对相互连接的封装前体(12)进行切单，以提供多个封装。
15.根据权利要求14的方法，其中散热片(20)具有相对的第一和第二表面，所述的表面平行于管芯(14)第一和第二表面，并且该包覆成型使得散热片(20)第二表面被模塑复合物(18)覆盖，散热片(20)第一表面没有被模塑复合物(18)覆盖。
16.根据权利要求15的方法，其进一步包括：
在电连接之后和包覆成型之前，将热传导材料(88)施加到多个管芯的背面，该热传导材料(88)的热传导性比模塑复合物(18)的热传导性高。
17.根据权利要求15的方法，其中散热片(20)包括从散热片(20)第二表面伸出的突起(100)，该突起与管芯(14)接触。
18.根据权利要求14的方法，其中多个相互连接的散热片(20)包括向下设置部分，该部分设置在多个相互连接的散热片的外围，并且其中将多个相互连接的散热片固定到多个管芯上包括将向下设置的部分设置到多个相互连接的衬底上，该切单包括经由向下设置的部分切单，以提供带有完全与衬底隔开的散热片(20)的封装(30)。
19.根据权利要求14的方法，其进一步包括：
将多个散热片中的每个散热片(20)与多个衬底中的相关的衬底(16)电连接。
20.根据权利要求14的方法，其中散热片(20)包括设置在其中的孔穴，其用于使模塑复合物(18)进入散热片(20)和衬底(16)之间。
21.根据权利要求14的方法，其中衬底(16)是金属引线框。
22.根据权利要求14的方法，其中衬底(16)包括绝缘材料(66)，所述绝缘材料(66)具有设置在其上的第一导电体(72)，该第一导电体(72)是从导电迹线、导电层、通道、销针、以及包括上述一种或多种的组合的至少其中之一选取的。
23.根据权利要求22的方法，进一步包括：
将一列第二导电体(70)与衬底(16)电耦合，第二导电体(70)是从焊球、焊料突起、焊剂、销针以及包括上述一种或多种的组合的至少其中之一选取的。
24.根据权利要求14的方法，其中将输入/输出焊垫(60)电连接键合点(62)包括：
导线键合或胶带键合输入/输出焊垫(60)与键合点(62)。
25.根据权利要求14的方法，其中将输入/输出焊垫(60)与键合点(62)电连接包括：
以倒装片法方式将输入/输出焊垫(60)直接电连接键合点(62)。
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Families Citing this family (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI239080B (en) * 2002-12-31 2005-09-01 Advanced Semiconductor Eng Semiconductor chip package and method for the same
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US8211753B2 (en) * 2003-08-26 2012-07-03 Stats Chippac Ltd. Leadframe-based mold array package heat spreader and fabrication method therefor
TWI233170B (en) * 2004-02-05 2005-05-21 United Microelectronics Corp Ultra-thin wafer level stack packaging method and structure using thereof
TWI374525B (en) * 2004-05-11 2012-10-11 Taiwan Semiconductor Mfg Cut-out heat slug for integrated circuit device packaging
US7084494B2 (en) * 2004-06-18 2006-08-01 Texas Instruments Incorporated Semiconductor package having integrated metal parts for thermal enhancement
KR100631403B1 (ko) * 2004-09-23 2006-10-09 삼성전자주식회사 방열판을 장착한 반도체 패키지 및 그 제조 방법
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
US7851268B2 (en) * 2005-04-09 2010-12-14 Stats Chippac Ltd. Integrated circuit package system using heat slug
CN101834167A (zh) 2005-06-06 2010-09-15 罗姆股份有限公司 半导体装置、基板及半导体装置的制造方法
CN100466210C (zh) * 2005-07-15 2009-03-04 矽品精密工业股份有限公司 散热型半导体封装件及其制法
US8643163B2 (en) * 2005-08-08 2014-02-04 Stats Chippac Ltd. Integrated circuit package-on-package stacking system and method of manufacture thereof
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
DE602005013084D1 (de) 2005-09-15 2009-04-16 Infineon Technologies Ag Elektromagnetische Abschirmung von Gehäusen mit einem Laminatsubstrat
US8624346B2 (en) 2005-10-11 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Exclusion zone for stress-sensitive circuit design
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8039951B2 (en) 2006-01-19 2011-10-18 United Test And Assembly Center Ltd. Thermally enhanced semiconductor package and method of producing the same
US8022512B2 (en) * 2006-02-28 2011-09-20 Unisem (Mauritus) Holdings Limited No lead package with heat spreader
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US7741158B2 (en) * 2006-06-08 2010-06-22 Unisem (Mauritius) Holdings Limited Method of making thermally enhanced substrate-base package
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US20080157300A1 (en) * 2006-12-27 2008-07-03 Shih-Fang Chuang Thermally Enhanced IC Package and Method
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
TWI332255B (en) * 2007-03-20 2010-10-21 Orient Semiconductor Elect Ltd Heat block
US7952167B2 (en) * 2007-04-27 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line layout design
US8125052B2 (en) * 2007-05-14 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure with improved cracking protection
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
US8643172B2 (en) * 2007-06-08 2014-02-04 Freescale Semiconductor, Inc. Heat spreader for center gate molding
US8643147B2 (en) 2007-11-01 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with improved cracking protection and reduced problems
US8178956B2 (en) * 2007-12-13 2012-05-15 Stats Chippac Ltd. Integrated circuit package system for shielding electromagnetic interference
CN101226888B (zh) * 2008-02-15 2010-09-15 日月光半导体制造股份有限公司 散热型芯片封装工艺及其构造
US8154134B2 (en) * 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US8072047B2 (en) * 2008-05-21 2011-12-06 Stats Chippac Ltd. Integrated circuit package system with shield and tie bar
US8334582B2 (en) * 2008-06-26 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protective seal ring for preventing die-saw induced stress
US20100052156A1 (en) * 2008-08-27 2010-03-04 Advanced Semiconductor Engineering, Inc. Chip scale package structure and fabrication method thereof
US8390112B2 (en) 2008-09-30 2013-03-05 Intel Corporation Underfill process and materials for singulated heat spreader stiffener for thin core panel processing
US7863722B2 (en) * 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
US7906836B2 (en) 2008-11-14 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US7951643B2 (en) * 2008-11-29 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
US8368180B2 (en) * 2009-02-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line metal structure
CN101533816B (zh) * 2009-05-06 2011-02-09 友达光电股份有限公司 导电凸块结构及显示面板的芯片焊接结构
US20110012257A1 (en) * 2009-07-14 2011-01-20 Freescale Semiconductor, Inc Heat spreader for semiconductor package
CN102097395A (zh) * 2009-12-11 2011-06-15 日月光半导体（上海）股份有限公司 具有内嵌芯片的基板结构
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8653635B2 (en) * 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9159643B2 (en) * 2012-09-14 2015-10-13 Freescale Semiconductor, Inc. Matrix lid heatspreader for flip chip package
US8921994B2 (en) 2012-09-14 2014-12-30 Freescale Semiconductor, Inc. Thermally enhanced package with lid heat spreader
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
TWI471988B (zh) * 2012-11-13 2015-02-01 矽品精密工業股份有限公司 半導體封裝件之製法
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9653405B2 (en) * 2013-02-20 2017-05-16 Infineon Technologies Ag Chip arrangement and a method of manufacturing a chip arrangement
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
CN104916597B (zh) * 2014-03-14 2018-06-05 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
JP6017492B2 (ja) 2014-04-24 2016-11-02 Ｔｏｗａ株式会社 樹脂封止電子部品の製造方法、突起電極付き板状部材、及び樹脂封止電子部品
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
JP5944445B2 (ja) * 2014-07-18 2016-07-05 Ｔｏｗａ株式会社 樹脂封止電子部品の製造方法、突起電極付き板状部材、樹脂封止電子部品、及び突起電極付き板状部材の製造方法
CN105633027B (zh) * 2014-11-05 2019-07-16 无锡超钰微电子有限公司 扇出晶圆级芯片封装结构及其制造方法
JP2016092300A (ja) * 2014-11-07 2016-05-23 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
KR102117477B1 (ko) * 2015-04-23 2020-06-01 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조방법
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
TWI594380B (zh) * 2015-05-21 2017-08-01 穩懋半導體股份有限公司 封裝結構及三維封裝結構
US9892935B2 (en) 2015-05-28 2018-02-13 International Business Machines Corporation Limiting electronic package warpage with semiconductor chip lid and lid-ring
US9666556B2 (en) * 2015-06-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip packaging
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
JP6605382B2 (ja) * 2016-03-30 2019-11-13 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
TWI643297B (zh) * 2016-12-20 2018-12-01 力成科技股份有限公司 具有內置散熱片之半導體封裝構造
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6359341B1 (en) * 1999-01-21 2002-03-19 Siliconware Precision Industries, Co., Ltd. Ball grid array integrated circuit package structure
US6409859B1 (en) * 1998-06-30 2002-06-25 Amerasia International Technology, Inc. Method of making a laminated adhesive lid, as for an Electronic device
US6432749B1 (en) * 1999-08-24 2002-08-13 Texas Instruments Incorporated Method of fabricating flip chip IC packages with heat spreaders in strip format

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367196A (en) * 1992-09-17 1994-11-22 Olin Corporation Molded plastic semiconductor package including an aluminum alloy heat spreader
US5608267A (en) * 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
JPH06349893A (ja) * 1993-06-02 1994-12-22 Citizen Watch Co Ltd フリップチップ接続半導体パッケージ
US6271579B1 (en) * 1993-10-08 2001-08-07 Stratedge Corporation High-frequency passband microelectronics package
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5471011A (en) * 1994-05-26 1995-11-28 Ak Technology, Inc. Homogeneous thermoplastic semi-conductor chip carrier package
US5929513A (en) * 1994-08-16 1999-07-27 Fujitsu Limited Semiconductor device and heat sink used therein
JP3297251B2 (ja) * 1995-06-20 2002-07-02 株式会社東芝 携帯形電子機器
US5650663A (en) * 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5919329A (en) 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6432752B1 (en) 2000-08-17 2002-08-13 Micron Technology, Inc. Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages
US6432742B1 (en) * 2000-08-17 2002-08-13 St Assembly Test Services Pte Ltd. Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages
JP2002289756A (ja) * 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
TW498516B (en) * 2001-08-08 2002-08-11 Siliconware Precision Industries Co Ltd Manufacturing method for semiconductor package with heat sink
US6534859B1 (en) * 2002-04-05 2003-03-18 St. Assembly Test Services Ltd. Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6409859B1 (en) * 1998-06-30 2002-06-25 Amerasia International Technology, Inc. Method of making a laminated adhesive lid, as for an Electronic device
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6359341B1 (en) * 1999-01-21 2002-03-19 Siliconware Precision Industries, Co., Ltd. Ball grid array integrated circuit package structure
US6432749B1 (en) * 1999-08-24 2002-08-13 Texas Instruments Incorporated Method of fabricating flip chip IC packages with heat spreaders in strip format

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