CN100353545C - 具有封装内电源的较低外形封装及其封装方法 - Google Patents

具有封装内电源的较低外形封装及其封装方法 Download PDF

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CN100353545C
CN100353545C CNB028267222A CN02826722A CN100353545C CN 100353545 C CN100353545 C CN 100353545C CN B028267222 A CNB028267222 A CN B028267222A CN 02826722 A CN02826722 A CN 02826722A CN 100353545 C CN100353545 C CN 100353545C
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encapsulation
integrated circuit
circuit lead
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substrate
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CN1613150A (zh
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埃莉诺·拉瓦丹姆
理查德·弗尔英格
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    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

具有封装内电源(PSIP)特征的封装(10)可包括位于管芯(14)外部的电荷泵(16),以可具有更小的管芯尺寸。管芯(14)可被安装在具有球栅阵列的焊球阵列(34)的衬底上。封装(40)可具有和无PSIP能力的封装基本相同的尺寸。在一个实施例中,可以使用环氧树脂(18)来将无源组件(16)安装到管芯(14)上。在另一个实施例中,尺寸减小了的无源组件(32)可以安装在具有球栅阵列(34)的衬底(26)上一个没有焊球的区域(33)中。

Description

具有封装内电源的较低外形封装及其封装方法
技术领域
本发明一般地涉及集成电路,具体地说涉及用于封装集成电路管芯(die)的设计。
背景技术
可以通过微电子工艺来在衬底上加工集成电路芯片,所述衬底可以是硅晶片(silicon wafer)。一般地,同时在单个晶片上形成由刻划线隔开的多个芯片(晶块(dice))。通过在所述刻划线上进行分块(dicing)或切割(sawing)来分离各个晶块或芯片。
各个晶块需要电耦合到外部电路。然而,晶块非常脆弱,而且小得不易处理。另外,它们还可能容易被环境所污染和腐蚀,并且在操作期间易于过热,除非热量被散发掉。管芯封装向管芯提供了机械支持、电连接、对污染和腐蚀的防御、以及操作期间的散热。
封装管芯的工艺可包括将管芯附接到封装、从封装上的引线到管芯上的焊盘(pad)的导线的焊接、以及用于保护管芯的包装。
封装内电源(PSIP)设计用位于管芯外部的电感性电荷泵取代了管芯内的电容性电荷泵,但PSIP仍与管芯位于同一封装内。所获得的管芯尺寸的减小降低了加工成本。
外部电感性电荷泵包括独立的无源电路元件例如电感器和电容器,它们被包括在具有管芯的封装内。由于未将电荷泵集成到管芯中,因此所获得的封装一般较大。从而,可获得成本的节省,但代价是封装尺寸较大。
较大的封装尺寸在一些应用中可能会是个问题。设计者可能不愿使用PSIP部件,因为使用PSIP可能需要重新设计板卡布局以适应较大的封装尺寸。在一些情形下,可能难于获得额外的板卡空间。
因此,需要基本可保持非PSIP外形参数的PSIP封装。
发明内容
本发明的一个技术方案提供了一种用于电子器件的封装,其包括衬底、安装在所述衬底上的集成电路管芯,以及电荷泵,所述电荷泵包括安装在所述集成电路管芯上并且电耦合到所述集成电路管芯的无源组件,其中所述无源组件从所述集成电路管芯开始的延伸距离小于或等于16密耳。
本发明的另一技术方案提供了一种方法,其包括:形成衬底、将集成电路管芯安装在所述衬底上、形成具有电荷泵的封装,所述电荷泵在所述封装内耦合到所述集成电路管芯,以及在所述集成电路管芯上安装无源组件,并将所述无源组件电耦合到所述集成电路管芯,使得所述无源组件从所述集成电路管芯开始的延伸距离小于或等于16密耳。
附图说明
图1是根据本发明的一个实施例,用于集成电路的封装的放大截面图;
图2是根据本发明的另一个实施例,用于集成电路的封装的放大截面图;并且
图3是图2所示的实施例的底面视图。
具体实施方式
参考图1,根据本发明的一个实施例的球栅阵列(BGA)封装10可包括衬底12,衬底12可使用多个焊球25而电连接到外部电路。封装10可包含附接到衬底12的集成电路管芯14,所述附接例如使用合适的粘合剂18。在一个实施例中,一组低外形无源组件16a和16b形成位于管芯14外部的电荷泵。组件16a和16b可以例如使用粘合剂18而附接到管芯14的上表面。
电荷泵组件16可包括电感器和电容器。粘合剂18可以是环氧树脂粘合剂。而且,由于电荷泵组件16位于封装10内(虽然在管芯14外部),因此所述封装可以是封装内电源(PSIP)。
引线接合(wirebond)20在衬底12和管芯14之间,以及在衬底12和无源组件16之间提供电连接。保护性包装24包装了管芯14和组件16,构成了模制阵列封装(MAP)。
通过使用PSIP,可以获得较小的管芯14。然而,传统上,封装10的尺寸可能会超过通常包括相同的电器件的非PSIP封装的外形参数,因为它没有集成组件16。
封装10基本上可保持对应的非PSIP封装的外形参数,因此封装10可以适合到板卡上为执行相同功能的对应的非PSIP封装而分配的空间内。结果,可以实现一种精简的封装10,其具有较低的成本,同时基本保持了对应的(但更昂贵的)非PSIP封装的外形参数。
在一些实施例中,可以将无源组件16选择成具有不超过16密耳的高度。在一些实施例中,通过使用与针栅阵列(PGA)封装技术相比具有相对较低的垂直外形的BGA封装技术,还可以进一步减小这一封装10的垂直外形。通过使用诸如用户选择的(user-dispensed)环氧树脂作为粘合剂18的附接方法,而非将无源组件16表面安装(surface mount)到管芯14旁边的衬底12上,可以减小封装的x、y尺寸。
参考图2,在另一个PSIP实施例中,球栅阵列(BGA)封装26可包括安装到衬底28上的集成电路管芯29。在一个示例中,可以使用包装30来包装衬底28的上表面。使用位于衬底28的下表面上的多个焊球34来将封装26电连接到外部电路。包括电感器和电容器的无源组件32a和32b构成位于管芯29下方外部的的电荷泵。
参考图3,组件32可附接到衬底28下面没有焊球34的中央区域33之内。随后,通过表面安装焊球34来将封装26附接到外部电路。
在一个实施例中,无源组件32a和32b的高度不超过焊球34的高度。因此,无源组件32可以包括在BGA衬底28的下表面上,这一做法与将无源组件32集成到管芯29内的情况相比而言,不会增加封装26的高度。因此,封装26由于它的PSIP设计而具有管芯29尺寸较小这一优点,同时它仍具有基本相同的外形参数。
尽管已针对有限数量的实施例来描述了本发明,本领域内的技术人员将会认识到可以从其实现大量的修改和变动。所附权利要求应覆盖所有落在本发明的真正精神和范围之内的所有这种修改和变动。

Claims (14)

1.一种用于电子器件的封装,包括:
衬底;
安装在所述衬底上的集成电路管芯;以及
电荷泵,其包括安装在所述集成电路管芯上并且电耦合到所述集成电路管芯的无源组件,其中所述无源组件从所述集成电路管芯开始的延伸距离小于或等于16密耳。
2.如权利要求1所述的封装,包括附接到所述衬底的具有多个焊球的球栅阵列。
3.如权利要求2所述的封装,其中所述无源组件粘合性地附接到所述集成电路管芯。
4.如权利要求3所述的封装,其中所述无源组件和所述集成电路管芯使用引线接合而电连接到所述衬底。
5.如权利要求1所述的封装,其中所述无源组件是电感器。
6.如权利要求1所述的封装,其中所述无源组件是电容器。
7.如权利要求1所述的封装,其中所述封装是模制阵列封装。
8.如权利要求1所述的封装,其中所述封装使用封装内电源技术。
9.一种方法,包括:
形成衬底;
将集成电路管芯安装在所述衬底上;以及
形成具有电荷泵的封装,所述电荷泵在所述封装内耦合到所述集成电路管芯;以及
在所述集成电路管芯上安装无源组件,并将所述无源组件电耦合到所述集成电路管芯,使得所述无源组件从所述集成电路管芯开始的延伸距离小于或等于16密耳。
10.如权利要求9所述的方法,包括将具有多个焊球的球栅阵列附接到所述衬底。
11.如权利要求10所述的方法,包括将所述无源组件粘合性地附接到所述集成电路管芯。
12.如权利要求11所述的方法,包括使用引线接合来将所述无源组件电连接到所述衬底,以及将所述集成电路管芯连接到所述衬底。
13.如权利要求9所述的方法,包括形成模制阵列封装。
14.如权利要求9所述的方法,包括使用封装内电源技术。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7823279B2 (en) * 2002-04-01 2010-11-02 Intel Corporation Method for using an in package power supply to supply power to an integrated circuit and to a component
US7626247B2 (en) * 2005-12-22 2009-12-01 Atmel Corporation Electronic package with integral electromagnetic radiation shield and methods related thereto
US20090243051A1 (en) * 2008-03-28 2009-10-01 Micron Technology, Inc. Integrated conductive shield for microelectronic device assemblies and associated methods
WO2010059724A2 (en) * 2008-11-20 2010-05-27 Qualcomm Incorporated Capacitor die design for small form factors
CN101882613B (zh) * 2009-05-04 2012-05-23 奇景光电股份有限公司 具有芯片封圈的集成电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
JPH11177015A (ja) * 1997-12-11 1999-07-02 Canon Inc 半導体パッケージおよび半導体パッケージ実装用中間基板
US5982018A (en) * 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
US6229385B1 (en) * 1999-01-29 2001-05-08 Linear Technology Corporation Control feature for IC without using a dedicated pin
WO2001039252A2 (en) * 1999-11-22 2001-05-31 The Board Of Trustees Of The University Of Illinois Active package for integrated circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803610A (en) * 1986-04-07 1989-02-07 Zdzislaw Gulczynski Switching power supply
SE509679C2 (sv) * 1997-04-10 1999-02-22 Ericsson Telefon Ab L M Förfarande för att styra en likspänning från en DC-DC- omvandlare och en DC-DC-omvandlare
US6512680B2 (en) * 1997-09-19 2003-01-28 Canon Kabushiki Kaisha Semiconductor package
US6040622A (en) * 1998-06-11 2000-03-21 Sandisk Corporation Semiconductor package using terminals formed on a conductive layer of a circuit board
US6664628B2 (en) * 1998-07-13 2003-12-16 Formfactor, Inc. Electronic component overlapping dice of unsingulated semiconductor wafer
US20030038366A1 (en) * 1999-03-09 2003-02-27 Kabushiki Kaisha Toshiba Three-dimensional semiconductor device having plural active semiconductor components
US6335566B1 (en) * 1999-06-17 2002-01-01 Hitachi, Ltd. Semiconductor device and an electronic device
US6300677B1 (en) * 1999-08-31 2001-10-09 Sun Microsystems, Inc. Electronic assembly having improved power supply bus voltage integrity
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US6348818B1 (en) * 2000-08-14 2002-02-19 Ledi-Lite Ltd. Voltage-adder LED driver
US6522192B1 (en) * 2000-10-11 2003-02-18 Tropian Inc. Boost doubler circuit
US6538494B2 (en) * 2001-03-14 2003-03-25 Micron Technology, Inc. Pump circuits using flyback effect from integrated inductance
US7067914B2 (en) * 2001-11-09 2006-06-27 International Business Machines Corporation Dual chip stack method for electro-static discharge protection of integrated circuits

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5982018A (en) * 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
JPH11177015A (ja) * 1997-12-11 1999-07-02 Canon Inc 半導体パッケージおよび半導体パッケージ実装用中間基板
US6229385B1 (en) * 1999-01-29 2001-05-08 Linear Technology Corporation Control feature for IC without using a dedicated pin
WO2001039252A2 (en) * 1999-11-22 2001-05-31 The Board Of Trustees Of The University Of Illinois Active package for integrated circuit

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AU2002351348A1 (en) 2003-07-30
US6812566B2 (en) 2004-11-02
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US20030123239A1 (en) 2003-07-03
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CN1613150A (zh) 2005-05-04
WO2003061005A2 (en) 2003-07-24

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