CN100342507C - 制造应变mosfet的结构和方法 - Google Patents

制造应变mosfet的结构和方法 Download PDF

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CN100342507C
CN100342507C CNB2005100042715A CN200510004271A CN100342507C CN 100342507 C CN100342507 C CN 100342507C CN B2005100042715 A CNB2005100042715 A CN B2005100042715A CN 200510004271 A CN200510004271 A CN 200510004271A CN 100342507 C CN100342507 C CN 100342507C
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史蒂文·W.·贝德尔
布鲁斯·B.·多丽丝
张郢
朱慧珑
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GlobalFoundries Inc
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Abstract

本发明提供了一种形成缺陷减少的应变Si薄膜的方法和器件，其中所述应变Si薄膜形成在非导电衬底表面上竖直定向的翅片。所述应变Si薄膜或翅片可以形成半导体沟道，该沟道具有较小的尺寸，同时也具有较少的缺陷。所述应变Si翅片通过在驰豫SiGe块侧面上生长Si而形成。电介质栅极，例如氧化物，高k材料，或两者的组合可以在所述应变Si薄膜表面上形成。此外，在基本上不影响应变Si薄膜中的应力的情况下，驰豫SiGe块可以去除，而可以在以前被驰豫SiGe块占据的表面上形成第二栅极氧化物。因此，可以形成具有在非导电性衬底表面上竖直定向的应变Si薄膜的半导体器件，其中所述应变Si薄膜的定向可以使其形成小尺寸的沟道，而可以接近两侧和顶部，以便形成单栅极，双栅极或更多栅极的MOSFET和翅片式FET，具有缺陷数目减少的和/或尺寸减小的沟道。

Description

制造应变MOSFET的结构和方法
发明领域
本发明涉及制造具有应变Si形成的竖直栅极的MOSFET，尤其涉及制造具有应变Si形成的竖直栅极的单栅极和双栅极MOSFET和翅片式FET。
背景技术
随着半导体器件的缩小，传统的器件制造技术已经接近其尺寸缩放的实用极限。例如，当沟道的长度缩小到约50nm之下时，器件开始表现出短沟道效应，包括对于缩短的沟道长度，阈值电压下降。可以通过更高的掺杂浓度来减轻不需要的短沟道效应，但更高的掺杂浓度导致产生不需要的载流子迁移率下降的效应，增大了寄生结电容，并且如果掺杂浓度过高，会增大亚阈值偏移。
一种使短沟道和逆短沟道效应最小化的方法包括通过良好控制的注入和退火形成最优的掺杂型面。然而，仔细控制注入和退火增加了制造工艺成本，并且随着沟道长度的进一步减小，其有效性最终受到限制。还出现了由于栅极氧化物的厚度和源/漏极结深度的限制造成的尺寸缩放限制，而削弱了较小器件的功能。
另一种获得进一步减小的尺寸的方法包括制造的沟道型面的困难。这样的型面包括双栅极，三栅极，四栅极，ω栅极，π栅极和翅片式FET的MOSFET设计。这些设计中有些受到比如导致增大寄生电容的栅极对准误差等的设计问题困扰。
另一种避免某些尺寸缩放问题的可能方法是通过改进材料的性能来改进器件的性能。例如，应变Si产生了更高的载流子迁移率，导致形成更快和/或更慢的功率消耗器件。由于应变Si晶体结构的变化(即，其对称和晶格常数由于其应变状态而不同)，应变Si薄膜具有优于体式Si的电性能。具体而言，应变Si可以具有更高的电子和空穴迁移率，它们分别转变成n型和p型晶体管的更高的驱动电流能力。因此，包含应变Si的器件可以具有改善的性能，而不必要减小器件的尺寸。然而，在应变Si的确允许进一步降低尺寸的情况下，性能的提高还可以进一步改善。
然而，应当指出，在通过利用应变Si实现高性能器件的过程中重要的指标是制造出低缺陷密度的应变Si薄膜。尤其是，减少应变Si薄膜中的位错数量特别重要，以便降低泄漏，改进载流子迁移率。
在晶格参数不同于Si的衬底上生长硅膜，产生了应变Si薄膜。因此，应变Si薄膜的缺陷数量可以与下方的生长所述薄膜的衬底中缺陷的数量成比例。在Si沟道中位错数量的增加可能增大器件在处于“关断”阶段时的漏电流。当不适当地形成时，应变Si薄膜可能包含大量的缺陷，并且随后的应变Si薄膜将表现出较差的性能，因此基本上抵消了使用应变Si薄膜的任何优点。
因此，为了进一步降低半导体器件尺寸和功率需求，希望生产具有最少缺陷比如位错的应变Si薄膜。具有较少缺陷的应变Si薄膜可以改善半导体器件的性能。
发明内容
在本发明的一方面，一种方法，包含在衬底上形成弛豫SiGe块，并且在所述衬底上至少邻近所述弛豫SiGe块一侧形成应变Si薄膜。所述方法还包括位于所述应变Si薄膜一侧形成栅极氧化物，从而形成应变沟道区。
在另一方面，本发明包括一种方法，包含在氧化物衬底上形成弛豫SiGe块，并且在所述弛豫SiGe块顶部上形成第一氮化物分隔层。在所述氧化物衬底上邻近所述弛豫SiGe块的第一侧和所述第一氮化物分隔层的一侧形成第二氮化物分隔层，且在所述弛豫SiGe块的第二侧外延地形成应变Si薄膜。
在另一方面，本发明包括用于半导体器件的沟道，包含在非导电衬底上竖直定向的应变Si形成的翅片。
附图说明
图1-8示出了形成本发明的实施例的步骤。
图9-14示出了形成本发明的器件的步骤；
图15-19示出了形成本发明的实施例的另一些步骤。
具体实施方式
本发明涉及形成具有应变Si形成的沟道的MOSFET。在本发明中，通过产生应变Si薄膜而提高了晶体管的性能。由于应变Si的尺寸较小，当比如通过外延生长技术形成时，通常缺陷(例如，位错)的密度非常低。这种低缺陷薄膜可以通过在氧化物晶片上驰豫SiGe上形成竖直的SiGe条或块而形成。在SiGe条或块的一侧可以用氮化物覆盖。竖直的SiGe条或块的另一侧可以使用选择性外延生长工艺由小尺寸的Si薄膜覆盖。由于与所述SiGe衬底的晶格常数不匹配，所述Si薄膜将会发生应变。由于Si膜的尺寸较小，和SiGe衬底的驰豫结构，减轻了形成位错的倾向。完成后，应变Si可以进行进一步处理，从而形成多种类型的MOSFET，比如具有单栅极，双栅极或更多栅极的翅片式FET。
图1示出了在氧化物晶片10上的弛豫SiGe层12。尽管在该示例中使用氧化物晶片，但可以使用适于半导体器件制造的任何非导电衬底。弛豫SiGe层12可以通过任何本领域公知的适当方法在氧化物晶片10上形成，这些方法比如晶片键合或氧注入退火。在一个实施例中，SiGe层12的厚度在30nm和80nm之间，但其他厚度也在本发明的考虑之中。
图2示出了淀积在弛豫SiGe层12上的薄氧化物层14。第一多晶硅层16在氧化物层14上形成。然后，光致抗蚀剂18淀积在第一多晶硅层16上，且形成图案，而使第一多晶硅层16的一部分被光致抗蚀剂18覆盖，第一多晶硅层16的一部分被暴露。薄氧化物层14的典型厚度约5至20nm，第一多晶硅层16为40nm至100nm。每层都通过本领域公知的方法制成。
图3示出了蚀刻工艺的结果，其中第一多晶硅层16的暴露部分和下方的薄氧化物层14被蚀刻掉，留下第一多晶硅16的一部分。蚀刻工艺使用公知的方法来选择性地蚀刻多晶硅和氧化物。光致抗蚀剂层18也在第一多晶硅16和氧化物层14在蚀刻之后被去除。因此，SiGe层12的第一部分暴露，SiGe层12的第二部分被薄氧化物层14和第一多晶硅层16覆盖。接着，使用本领域公知的任何氮化物形成工艺在SiGe层12顶部邻接薄氧化物层14的边缘和第一多晶硅层16形成第一氮化物分隔层20。
图4示出了另一蚀刻步骤，其中使用类似于参照图3描述的蚀刻工艺对暴露的SiGe层12进行选择性蚀刻。在图4中，没有被第一氮化物分隔层20、和薄氧化物层14以及第一多晶硅层16覆盖的驰豫SiGe层12的所述部分，被蚀刻掉，而露出下面的氧化物晶片10的一部分。然后在所述氧化物晶片10的暴露部分上邻接蚀刻的驰豫SiGe层12的边缘形成第二氮化物分隔层22。第一氮化物分隔层20邻近第二氮化物分隔层22。
图5示出了选择性地蚀刻第一多晶硅层16和薄氧化物层14的剩余部分的结果。在薄氧化物层14和第一多晶硅层16下面的驰豫SiGe层的所述部分在该工艺中被蚀刻掉。因此，从氧化物晶片10顶部的初始驰豫SiGe层12留下被成形为SiGe块24的驰豫SiGe。SiGe块24在一侧被第二氮化物层22围绕，在预部被第一氮化物分隔层20围绕，使SiGe块24的一侧暴露。
图6示出了在SiGe块24的暴露侧上外延生长的“应变”Si薄膜26。使用选择性地生长工艺，而使Si薄膜26仅在SiGe块24的暴露部分上生长。在该工艺中，Si薄膜26具有大于其厚度的高度，且在氧化物晶片10的表面上竖直定向。因为Si薄膜26可以以基本上任何纵横比(高度除以厚度)形成，包括大于1的那些纵横比，所以Si薄膜26可以表现为在氧化物晶片10上竖直定向的“翅片”。
此外，Si薄膜26可以与SiGe块24的高度大致相同。因此，Si薄膜26的高度可以通过调节驰豫SiGe层12的层高度进行控制。SiGe层12的高度可以在其通过本领域公知的方法形成的过程中进行控制。而且，Si薄膜26的厚度可以在通过器件制造领域公知的适当方法进行的生长工艺中控制。Si薄膜26的厚度可以约50(埃)至约200，但在需要的情况下可以使用其他的厚度。
Si薄膜26可以用作从缺陷数目减少和/或尺寸较小的沟道而受益的实际上任何类型的器件中的半导体器件的沟道。因此，可以在Si沟道的一部分上形成至少一个栅极氧化物，其中在所述栅极氧化物两侧的Si薄膜26上分别形成源极区域/漏极区域。所形成的结构，因为它是竖直定向的，所以可以从衬底上方接近沟道两侧和顶部。这种几何形状可以使栅极氧化物围绕所述沟道，且可以在断路状态所述沟道几乎全部耗尽。也可以接近源极/漏极区域的两侧，以便更好地掺杂和更好的引线连通性。
通过在驰豫SiGe块24的表面上生长Si薄膜26，减少了在所形成的Si薄膜26上的缺陷数目，比如位错。Si薄膜26中的位错也最小化，因为仅生长小尺寸的薄膜。此外，应变Si薄膜由于其晶格在SiGe晶格上形成而实现其内部应变。即，SiGe块24具有比Si薄膜的大的晶格常数(原子之间的不同尺寸)，即单独地，Si通常具有小于SiGe的晶格，因为Si材料的晶格常数与SiGe的晶格常数不匹配。然而，在本发明的结构中，Si层的晶格将趋于匹配SiGe的晶格。由于Si的晶格(通常较小)与SiGe掩模匹配，所以Si层处于张应力下。即，SiGe掩模将试图获得平衡状态，这样导致在SiGe上形成的Si侧壁层产生应力。这一体积的应力硅可以用作应变沟道。因此，Si薄膜26可以描述为低缺陷应变Si翅片或沟道。
图7示出了使用离子注入在Si薄膜26的暴露侧上形成栅极氧化物28。例如可以使用Vt(阈值电压)离子注入技术，且注入角可以朝侧面的栅极氧化物28倾斜。栅极氧化物28的示例厚度约9至约20，但在需要时可以形成其他厚度。也可以使用高“k”材料，比如HfO2，来代替氧化物作为栅极电介质。
图8示出了淀积在第一和第二氮化物分隔层20和22、SiGe块24、Si薄膜26和栅极氧化物28上的第二多晶硅层30。虽然第二多晶硅层30示为共形层，但可以形成非共形层，或具有根据器件形成的后续步骤需要而在共形和非共形之间某处的形状的层。例如，多晶硅层30的厚度可以从约700至约1500。
从图8所示的结构可知，可以制造各种器件，包括例如应变SiMOSFET，比如具有单应变栅极的翅片式FET，或具有应变双栅极的翅片式FET。图9-14示出了制造单栅极器件的示例，图15-19示出了制造双栅极翅片式FET型器件的示例。此外，也可以从图8所示的机构制造三栅极器件，具有围绕应变Si薄膜的顶部和两侧的栅极电介质。虽然示出了单栅极器件和双栅极器件，但可以从图8所示的结构制造任何类型的器件，该器件可以受益于位错减少的竖直应变Si薄膜。
参照图9，示出了制造的器件的顶视图，其中在第二多晶硅层30上淀积光致抗蚀剂且形成图案。如图9所示，光致抗蚀剂102淀积在Si薄膜26的区域内的第二多晶硅层30上，这将形成所形成的器件的栅极。图10示出了图9的结构侧视图，其中光致抗蚀剂102在第二多晶硅层30上。
图11示出了在使用本领域公知的蚀刻工艺，比如湿法蚀刻而蚀刻了图9的光致抗蚀剂102之后所形成的结构的顶视图。尤其是，蚀刻步骤留下将成为两个源极/漏极区域104的部分，在栅极区域106每一侧有一个。在源极/漏极区域104中，暴露出氧化物晶片10、在下面的Si薄膜26侧面和顶部上的栅极氧化物28、和第二氮化物分隔层22。在图11中Si薄膜26不可见。
图12示出了图11所示器件的剖面。如图12所示，在源极/漏极区域104中进行离子注入，在栅极区域106的两侧形成延伸部分。可以使用任何适于制造器件的源极/漏极注入的离子注入工艺，如本领域所公知。此外可以使用大倾角离子注入，例如对于硼注入来说约0.2-1keV的能量级别，对于砷来说1-2keV的能量级别。
图13示出了通过在氧化物晶片10上邻近第二多晶硅层30淀积氮化物，然后蚀刻而形成氮化物分隔层108之后，所制造的器件的顶视图。图14示出了覆盖栅极氧化物28和第二氮化物分隔层22上的氮化物分隔层108。在形成氮化物分隔层108之后，在适于制造的器件的时候，可以进行其他的步骤，包括源极/漏极注入和退火。
从图8所示的结构开始，图15示出了在形成应变Si双栅极翅片式FET的过程中的后续步骤，它是另一种类型的示例，其中可以实现本发明包括的应变Si薄膜。如图15所示，淀积氧化物薄膜202，且例如使用CMP(化学机械平面化)平面化。然后蚀刻掉剩余的氧化物薄膜202，使第二多晶硅层30的一部分暴露在氧化物薄膜202上方。氧化物薄膜202可以例如使用定向HDP(高密度等离子体)淀积，从而在氮化物分隔层20和22上方的区域，优先将大多数氧化物淀积在平面上，较少的氧化物淀积在多晶硅30的顶部上。
图16示出蚀刻第二多晶硅层30的一部分，使第一和第二氮化物层20和22的一部分暴露。适当的蚀刻工艺可包括任何选择性蚀刻多晶硅的工艺，和任何选择性地蚀刻氧化物的蚀刻工艺，比如湿法蚀刻。在蚀刻之后，第一和第二氮化物分隔层20和22暴露，且伸出到第二多晶硅层30上方。第二多晶硅层30将形成第一和第二氮化物分隔层20和22、以及栅极氧化物28基底附近的突出区域。
图17示出了两个氮化物分隔层20和22的湿式选择性蚀刻和SiGe块24的湿式蚀刻结果。在整个制造工艺中，普通的蚀刻剂可以用于蚀刻氮化物，包括例如氟和氯。Si3N4至SiO2的选择性蚀刻可以利用沸腾的H3PO4溶液(例如85％H3PO4，180℃)进行，因为这种溶液腐蚀SiO2非常慢。对于Si3N4来说蚀刻速度为～10nm/min，但小于SiO2的1mm/min。Si3N4可以在浓缩的HF或缓冲的HF中在室温下蚀刻。然而，HF还蚀刻SiO2。使用反应离子等离子体蚀刻工艺，下述蚀刻化学制品可以用于Si3N4:CHF3/O2；CH2F2；CH2CHF2。通过去除SiGe块24以及第一和第二氮化物分隔层，20和22，应变Si薄膜26具有用于进一步处理的暴露侧面，比如添加另一栅极氧化物。
图18示出了通过栅极氧化工艺形成第二栅极氧化物208，该工艺分别在器件的暴露部分和Si薄膜26上形成薄氧化物层204。尤其是，在Si薄膜26上形成的薄氧化物层205的所述部分构成栅极氧化物205的第二栅极氧化物208部分。栅极氧化物205还包括在前面步骤中形成的第一栅极氧化物207。例如通过热氧化物生长工艺可以形成第二栅极氧化物208，从而形成高质量的氧化物。
而且图18示出了淀积在所述器件表面上的薄多晶硅层。然后对所述结构进行直接蚀刻，从而在薄氧化物层204一侧上形成薄多晶硅分隔层206。尤其是，薄多晶硅分隔层206邻近第二栅极氧化物208形成。多晶硅分隔层206可以避免栅极氧化物208进一步被蚀刻。薄多晶硅分隔层206可以例如约100厚。此外，形成薄多晶硅分隔层206，而使薄氧化物层204的部分暴露在第二多晶硅层30的顶部上。
图19示出了对薄氧化物层204的暴露部分的蚀刻。可以使用任何选择性地蚀刻氧化物层的工艺，从而去除薄氧化物层204的暴露部分。在完成氧化物蚀刻之后，淀积多晶硅而在衬底上形成第三多晶硅层210。所形成的结构包括垂直于氧化物晶片10直立的应变Si 26翅片，在其侧面和顶部被栅极氧化物205围绕。应变Si 26的竖直翅片侧面都可以从氧化物晶片10的表面上方被接近(和触及)。而且，应变Si 26的竖直翅片包括源极/漏极区域，其两侧和顶部可以在氧化物晶片10上方被接近。
利用本领域公知的制造步骤可以继续对图19所示的器件进行处理，从而生产完整的双栅极翅片式FET器件，该器件具有应变Si薄膜。
虽然已经根据实施例描述了本发明，但本领域的技术人员将认识到本发明可以在所附权利要求的主旨和范围内进行改进。例如，本发明可以容易地用于体式基底。

Claims (22)

1.一种用于形成半导体结构的方法，包含：
在衬底上形成驰豫SiGe块；
在驰豫SiGe块的与衬底相邻的一侧上形成应变Si薄膜，从而形成应变沟道区域。
2、如权利要求1所述的方法，其特征在于还包含形成栅极，该栅极包含位于所述应变Si薄膜至少一侧上的至少氧化物和高k材料之一。
3、如权利要求2所述的方法，其特征在于还包含去除所述驰豫SiGe块，露出所述应变Si薄膜的一侧，并形成栅极，该栅极包含在所述应变Si薄膜的暴露侧上的至少氧化物和高k材料之一。
4、如权利要求2所述的方法，其特征在于所述应变Si薄膜厚度在约50和200之间，栅极的厚度在约9和20之间。
5、如权利要求1所述的方法，其特征在于所述应变Si薄膜是选择性地外延生长的。
6、如权利要求1所述的方法，其特征在于还包含在所述驰豫SiGe块的顶部上形成第一氮化物分隔层，且在所述驰豫SiGe块第二侧和第一氮化物分隔层一侧上形成第二氮化物分隔层。
7、如权利要求1所述的方法，其特征在于所述应变Si薄膜具有大于厚度的高度。
8、如权利要求1所述的方法，其特征在于所述SiGe块通过在衬底上形成驰豫SiGe层且蚀刻掉部分所述驰豫SiGe层而形成。
9、如权利要求1所述的方法，其特征在于还包含：
在所述驰豫SiGe层上形成薄氧化物层；
在所述薄氧化物层上形成多晶硅层；
在所述多晶硅层的一部分上形成光致抗蚀剂；以及
蚀刻掉所述多晶硅层的暴露部分、和所述氧化物层的一部分，从而露出所述驰豫SiGe层的一部分；以及
在所述驰豫SiGe层的顶部邻近所述薄氧化物层和多晶硅层的边缘形成第一氮化物分隔层。
10、如权利要求9所述的方法，其特征在于还包含：
蚀刻所述驰豫SiGe层的暴露部分，从而露出衬底的一部分；
在所述暴露的衬底上邻近所述驰豫SiGe层的边缘和第一氮化物分隔层形成第二氮化物分隔层；
蚀刻掉所述多晶硅层的剩余部分，薄氧化物层和在所述薄氧化物层下方的所述驰豫SiGe层的一部分，从而形成具有第一和第二氮化物分隔层的所述驰豫SiGe块。
11、一种形成半导体结构的方法，包含：
在氧化物衬底上形成驰豫SiGe块；
在所述驰豫SiGe块的第一部分上形成第一氮化物分隔层；
在所述氧化物衬底上邻近所述驰豫SiGe块的另一部分和第一氮化物分隔层的一部分形成第二氮化物分隔层；
在所述驰豫SiGe块的暴露侧外延地形成应变Si薄膜。
12、如权利要求11所述的方法，其特征在于所述应变Si薄膜具有大于厚度的高度。
13、如权利要求12所述的方法，其特征在于所述应变Si薄膜形成位于所述氧化物衬底上竖直定向的应变Si薄膜翅片。
14、如权利要求12所述的方法，其特征在于还包含形成栅极，该栅极包含在所述应变Si薄膜的与所述SiGe块相对的第一表面上的至少氧化物和高k材料之一。
15、如权利要求11所述的方法，其特征在于所述应变Si薄膜的高度基本上等于SiGe块的高度。
16、如权利要求15所述的方法，其特征在于还包含：
形成栅极，该栅极包含在所述应变Si薄膜顶部的氧化物和高k材料至少之一；
去除第一和第二氮化物分隔层；
去除所述SiGe块，从而露出所述应变Si薄膜的第二侧；以及
形成栅极，该栅极包含在所述应变Si薄膜第二侧上的氧化物和高k材料至少之一。
17.一种半导体结构，包含：
具有在非导电性衬底上竖直定向的应变Si翅片的沟道。
18.如权利要求17所述的结构，其特征在于所述应变Si薄膜的厚度在约50和200之间。
19.如权利要求17所述的结构，其特征在于所述应变Si薄膜在驰豫SiGe块上外延生长，其中所述驰豫SiGe包含约0％至约100％范围内的Ge。
20.如权利要求17所述的结构，其特征在于还包含栅极，该栅极包含在所述应变Si薄膜的第一侧上形成的氧化物和高k材料至少之一。
21.如权利要求20所述的结构，其特征在于还包含栅极，该栅极包含在所述应变Si薄膜的顶部和第二侧上形成的氧化物和高k材料至少之一。
22.如权利要求20所述的结构，其特征在于所述Si薄膜是低缺陷应变Si翅片。
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