CA985739A - Contacting integrated circuit chip terminal through the wafer kerf - Google Patents

Contacting integrated circuit chip terminal through the wafer kerf

Info

Publication number
CA985739A
CA985739A CA180,182A CA180182A CA985739A CA 985739 A CA985739 A CA 985739A CA 180182 A CA180182 A CA 180182A CA 985739 A CA985739 A CA 985739A
Authority
CA
Canada
Prior art keywords
integrated circuit
circuit chip
chip terminal
wafer kerf
contacting integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA180,182A
Other versions
CA180182S (en
Inventor
Eric M. Hubacher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA985739A publication Critical patent/CA985739A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
CA180,182A 1972-10-24 1973-09-04 Contacting integrated circuit chip terminal through the wafer kerf Expired CA985739A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00300075A US3849872A (en) 1972-10-24 1972-10-24 Contacting integrated circuit chip terminal through the wafer kerf

Publications (1)

Publication Number Publication Date
CA985739A true CA985739A (en) 1976-03-16

Family

ID=23157593

Family Applications (1)

Application Number Title Priority Date Filing Date
CA180,182A Expired CA985739A (en) 1972-10-24 1973-09-04 Contacting integrated circuit chip terminal through the wafer kerf

Country Status (7)

Country Link
US (1) US3849872A (en)
JP (1) JPS5120259B2 (en)
CA (1) CA985739A (en)
DE (1) DE2351761A1 (en)
FR (1) FR2203977B1 (en)
GB (1) GB1437024A (en)
IT (1) IT1014510B (en)

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US5241266A (en) * 1992-04-10 1993-08-31 Micron Technology, Inc. Built-in test circuit connection for wafer level burnin and testing of individual dies
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
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US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
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US5942766A (en) * 1997-09-17 1999-08-24 Lucent Technologies, Inc. Article and method for in-process testing of RF products
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DE10125029B4 (en) * 2001-05-22 2008-08-21 Qimonda Ag Use of a Kerf-type subcircuit semiconductor device and method
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US6759311B2 (en) 2001-10-31 2004-07-06 Formfactor, Inc. Fan out of interconnect elements attached to semiconductor wafer
US6917194B2 (en) * 2003-08-27 2005-07-12 International Business Machines Corporation External verification of package processed linewidths and spacings in semiconductor packages
JP4515143B2 (en) * 2004-05-10 2010-07-28 三菱電機株式会社 Method for manufacturing thermal flow rate detection element
JP2006261504A (en) * 2005-03-18 2006-09-28 Fujitsu Ltd Semiconductor apparatus and its testing method
DE102005022600A1 (en) * 2005-05-10 2006-11-23 Atmel Germany Gmbh Integrated circuit with balancing elements and method of making the same
US7274201B2 (en) * 2005-05-19 2007-09-25 Micron Technology, Inc. Method and system for stressing semiconductor wafers during burn-in
US8457920B2 (en) * 2010-05-28 2013-06-04 International Business Machines Corporation Performance improvement for a multi-chip system via kerf area interconnect
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US3742254A (en) * 1971-01-27 1973-06-26 Texas Instruments Inc Automatic mos grounding circuit

Also Published As

Publication number Publication date
IT1014510B (en) 1977-04-30
JPS4975279A (en) 1974-07-19
FR2203977B1 (en) 1979-01-05
US3849872A (en) 1974-11-26
FR2203977A1 (en) 1974-05-17
GB1437024A (en) 1976-05-26
DE2351761A1 (en) 1974-04-25
JPS5120259B2 (en) 1976-06-23

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