CA2698356A1 - Method and apparatus for pre-emptively arbitrating on an acyclic directed graph - Google Patents
Method and apparatus for pre-emptively arbitrating on an acyclic directed graph Download PDFInfo
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- CA2698356A1 CA2698356A1 CA2698356A CA2698356A CA2698356A1 CA 2698356 A1 CA2698356 A1 CA 2698356A1 CA 2698356 A CA2698356 A CA 2698356A CA 2698356 A CA2698356 A CA 2698356A CA 2698356 A1 CA2698356 A1 CA 2698356A1
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- node
- adjacent
- nodes
- signal
- determining
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- 238000000034 method Methods 0.000 title claims 10
- 125000002015 acyclic group Chemical group 0.000 title abstract 2
- 238000004590 computer program Methods 0.000 claims 4
- 230000001902 propagating effect Effects 0.000 claims 4
- 238000001514 detection method Methods 0.000 abstract 1
- 230000001960 triggered effect Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40078—Bus configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40084—Bus arbitration
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/48—Routing tree calculation
Abstract
A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established.
Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.
Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.
Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
Claims (25)
1. A computer system comprising a plurality of components, the plurality of components each having at least one communications node wherein the communications nodes of the plurality of components are interconnected by communications links, the communications nodes and communications links comprising a bus of a directed acyclic graph wherein one node is designated a root node, all nodes coupled to only one adjacent node being designated leaf nodes, all other nodes in the directed acyclic graph being designated branch nodes, the directed acyclic graph having established hierarchical parent-child relations ships between all adjacent nodes proceeding from the root node down to any leaf nodes wherein a leaf node has only one parent node and all nodes adjacent to the root node are child nodes with respect to the root node but parent nodes with respect to other adjacent nodes, the root node being defined as having no parent node, the computer system further comprising:
means for propagating a "Bus Initialization" (BI) signal from any node determining that bus initialization is necessary;
means for sustaining the BI signal for a predetermined period of time; and means for propagating that signal throughout the directed acyclic graph to all nodes in the directed acyclic graph.
means for propagating a "Bus Initialization" (BI) signal from any node determining that bus initialization is necessary;
means for sustaining the BI signal for a predetermined period of time; and means for propagating that signal throughout the directed acyclic graph to all nodes in the directed acyclic graph.
2. A first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the first node comprising:
means for determining a first determination that a parent-child relationship between the first node and one of the at least one adjacent node is to be changed;
means for sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the first determination; and means for communicating with the at least one adjacent node to perform bus initialization.
means for determining a first determination that a parent-child relationship between the first node and one of the at least one adjacent node is to be changed;
means for sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the first determination; and means for communicating with the at least one adjacent node to perform bus initialization.
3. A first node as in claim 2, wherein said means for communicating comprises:
means for delaying for a period before propagating a "You Are My Parent" (YAMP) signal from the first node to any of the at least one adjacent node to increase a chance of the first node to become a parent of the at least one adjacent node.
means for delaying for a period before propagating a "You Are My Parent" (YAMP) signal from the first node to any of the at least one adjacent node to increase a chance of the first node to become a parent of the at least one adjacent node.
4. A first node as in claim 3, wherein the period is sufficient long such that the first node receives a "You Are My Parent" (YAMP) signal from each of the at least one adjacent node to become a parent of the at least one adjacent node.
5. A first node as in claim 2, wherein said means for communicating comprises:
means for determining an unique address of the first node for communication with the at least one adjacent node.
means for determining an unique address of the first node for communication with the at least one adjacent node.
6. A first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the first node comprising:
means for determining a change in status of a second node in communication with the first node through a point-to-point link;
means for sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the change; and means for performing bus initialization in communication with the at least one adjacent node.
means for determining a change in status of a second node in communication with the first node through a point-to-point link;
means for sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the change; and means for performing bus initialization in communication with the at least one adjacent node.
7. A first node as in claim 6, wherein the change in status comprises one of:
a) addition of the second node in communication with the first node; and b) removal of the second node in communication with the first node.
a) addition of the second node in communication with the first node; and b) removal of the second node in communication with the first node.
8. A first node as in claim 6, wherein said means for performing bus initialization comprises:
means for determining a parent-child relationship between the first node and each of the at least one adjacent node.
means for determining a parent-child relationship between the first node and each of the at least one adjacent node.
9. A first node as in claim 8, wherein said means for performing bus initialization comprises:
means for determining an unique address of the first node for communication with the at least one adjacent node.
means for determining an unique address of the first node for communication with the at least one adjacent node.
10. A machine readable medium containing executable computer program instructions which when executed by a data processing system cause said system to perform a method for a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining a first determination that a parent-child relationship between the first node and one of the at least one adjacent node is to be changed;
sustaining a " Bus Initialization " (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the first determination; and communicating with the at least one adjacent node to perform bus initialization.
determining a first determination that a parent-child relationship between the first node and one of the at least one adjacent node is to be changed;
sustaining a " Bus Initialization " (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the first determination; and communicating with the at least one adjacent node to perform bus initialization.
11. A medium as in claim 10, wherein said communicating comprises:
delaying for a period before propagating a "You Are My Parent" (YAMP) signal from the first node to any of the at least one adjacent node to increase a chance of the first node to become a parent of the at least one adjacent node.
delaying for a period before propagating a "You Are My Parent" (YAMP) signal from the first node to any of the at least one adjacent node to increase a chance of the first node to become a parent of the at least one adjacent node.
12. A medium as in claim 11, wherein the period is sufficient long such that the first node receives a "You Are My Parent" (YAMP) signal from each of the at least one adjacent node to become a parent of the at least one adjacent node.
13. A medium as in claim 10, wherein said communicating comprises:
determining an unique address of the first node for communication with the at least one adjacent node.
determining an unique address of the first node for communication with the at least one adjacent node.
14. A machine readable medium containing executable computer program instructions which when executed by a data processing system cause said system to perform a method for a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining a change in status of a second node in communication with the first node through a point-to-point link;
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the change; and performing bus initialization in communication with the at least one adjacent node.
determining a change in status of a second node in communication with the first node through a point-to-point link;
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the change; and performing bus initialization in communication with the at least one adjacent node.
15. A medium as in claim 14, wherein the change in status comprises one of:
a) addition of the second node in communication with the first node; and b) removal of the second node in communication with the first node.
a) addition of the second node in communication with the first node; and b) removal of the second node in communication with the first node.
16. A medium as in claim 14, wherein said performing bus initialization comprises:
determining a parent-child relationship between the first node and each of the at least one adjacent node.
determining a parent-child relationship between the first node and each of the at least one adjacent node.
17. A medium as in claim 16, wherein said performing bus initialization comprises:
determining an unique address of the first node for communication with the at least one adjacent node.
determining an unique address of the first node for communication with the at least one adjacent node.
18. A machine readable medium containing executable computer program instructions which when executed by a data processing system cause said system to perform a method for a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining an error condition in communication through the at least one links;
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the error condition; and performing bus initialization in communication with the at least one adjacent node.
determining an error condition in communication through the at least one links;
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the error condition; and performing bus initialization in communication with the at least one adjacent node.
19. A medium as in claim 18, wherein said performing bus initialization comprises:
determining a parent-child relationship between the first node and each of the at least one adjacent node.
determining a parent-child relationship between the first node and each of the at least one adjacent node.
20. A medium as in claim 19, wherein said performing bus initialization comprises:
determining an unique address of the first node for communication with the at least one adjacent node.
determining an unique address of the first node for communication with the at least one adjacent node.
21. A machine readable medium containing executable computer program instructions which when executed by a data processing system cause said system to perform a method for a first node to communicate with a plurality of adjacent nodes through a plurality of point-to-point links connected from the first node to the plurality adjacent nodes respectively, the method comprising:
receiving a "Bus Initialization" (BI) signal from a second node of the plurality of adjacent nodes;
sustaining the BI signal for a period of time to propagate the BI signal from the first node to the plurality of adjacent nodes except the second node in response to said receiving the BI signal; and performing bus initialization in communication with the plurality of adjacent nodes.
receiving a "Bus Initialization" (BI) signal from a second node of the plurality of adjacent nodes;
sustaining the BI signal for a period of time to propagate the BI signal from the first node to the plurality of adjacent nodes except the second node in response to said receiving the BI signal; and performing bus initialization in communication with the plurality of adjacent nodes.
22. A medium as in claim 21, wherein said performing bus initialization comprises:
determining a parent-child relationship between the first node and each of the plurality of adjacent nodes.
determining a parent-child relationship between the first node and each of the plurality of adjacent nodes.
23. A medium as in claim 21, wherein said performing bus initialization comprises:
determining an unique address of the first node for communication with the plurality of adjacent nodes.
determining an unique address of the first node for communication with the plurality of adjacent nodes.
24. A medium as in claim 21, wherein the method further comprises:
determining a first determination that bus initialization is necessary; and sustaining a BI signal for a period of time to propagate the BI signal to the plurality of adjacent nodes in response to the first determination.
determining a first determination that bus initialization is necessary; and sustaining a BI signal for a period of time to propagate the BI signal to the plurality of adjacent nodes in response to the first determination.
25. A medium as in claim 24, wherein the first determination is in response to one of:
a) determining that a parent-child relationship between the first node and one of the plurality of adjacent nodes is to be changed;
b) determining a adjacent node becoming engaged to the first node for communication;
c) determining a adjacent node becoming disengaged from the first node for communication; and d) determining an error condition in communication through the plurality of links.
a) determining that a parent-child relationship between the first node and one of the plurality of adjacent nodes is to be changed;
b) determining a adjacent node becoming engaged to the first node for communication;
c) determining a adjacent node becoming disengaged from the first node for communication; and d) determining an error condition in communication through the plurality of links.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/994,983 | 1992-12-21 | ||
| US07/994,983 US5630173A (en) | 1992-12-21 | 1992-12-21 | Methods and apparatus for bus access arbitration of nodes organized into acyclic directed graph by cyclic token passing and alternatively propagating request to root node and grant signal to the child node |
| CA2503335A CA2503335C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2503335A Division CA2503335C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2698356A1 true CA2698356A1 (en) | 1994-07-07 |
| CA2698356C CA2698356C (en) | 2011-04-12 |
Family
ID=25541282
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2698356A Expired - Lifetime CA2698356C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
| CA002408252A Expired - Lifetime CA2408252C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
| CA002151369A Expired - Lifetime CA2151369C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for bus access arbitration of nodes organized into acyclic token passing and alternatively propagating request to root node and grant signal to the child node |
| CA2503335A Expired - Lifetime CA2503335C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002408252A Expired - Lifetime CA2408252C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
| CA002151369A Expired - Lifetime CA2151369C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for bus access arbitration of nodes organized into acyclic token passing and alternatively propagating request to root node and grant signal to the child node |
| CA2503335A Expired - Lifetime CA2503335C (en) | 1992-12-21 | 1993-12-16 | Method and apparatus for pre-emptively arbitrating on an acyclic directed graph |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US5630173A (en) |
| EP (4) | EP0674788B1 (en) |
| JP (7) | JP3638949B2 (en) |
| KR (1) | KR100290517B1 (en) |
| AU (1) | AU5953994A (en) |
| CA (4) | CA2698356C (en) |
| DE (4) | DE69334172T2 (en) |
| HK (3) | HK1037036A1 (en) |
| WO (1) | WO1994015302A1 (en) |
Families Citing this family (116)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5875301A (en) * | 1994-12-19 | 1999-02-23 | Apple Computer, Inc. | Method and apparatus for the addition and removal of nodes from a common interconnect |
| US7334030B2 (en) * | 1994-12-19 | 2008-02-19 | Apple Inc. | Method and apparatus for the addition and removal of nodes from a common interconnect |
| US5784648A (en) * | 1995-12-01 | 1998-07-21 | Apple Computer, Inc. | Token style arbitration on a serial bus by passing an unrequested bus grand signal and returning the token by a token refusal signal |
| US5758105A (en) * | 1995-12-04 | 1998-05-26 | International Business Machines Corporation | Method and apparatus for bus arbitration between isochronous and non-isochronous devices |
| US7388092B2 (en) * | 1996-05-03 | 2008-06-17 | Applera Corporation | Oligonucleotides and analogs labeled with energy transfer dyes |
| US6131119A (en) * | 1997-04-01 | 2000-10-10 | Sony Corporation | Automatic configuration system for mapping node addresses within a bus structure to their physical location |
| JP3222086B2 (en) * | 1997-04-07 | 2001-10-22 | 矢崎総業株式会社 | Tree structure address setting method and system |
| US6145018A (en) * | 1997-11-24 | 2000-11-07 | Intel Corporation | Method for hindering some types of nodes from becoming a bus arbitration controller |
| US6041348A (en) * | 1997-12-01 | 2000-03-21 | Lsi Logic Corporation | N-port algorithm for disabling a node within a network during reset |
| US6411628B1 (en) * | 1998-02-02 | 2002-06-25 | Intel Corporation | Distributed arbitration on a full duplex bus |
| US6393557B1 (en) | 1998-05-08 | 2002-05-21 | International Business Machines Corporation | Dynamic method for configuring a computer system |
| US6434656B1 (en) * | 1998-05-08 | 2002-08-13 | International Business Machines Corporation | Method for routing I/O data in a multiprocessor system having a non-uniform memory access architecture |
| JP3277887B2 (en) * | 1998-06-19 | 2002-04-22 | 日本電気株式会社 | Transmission / reception method, transmission / reception circuit and method for controlling transmission / reception circuit |
| US6122723A (en) * | 1998-08-20 | 2000-09-19 | International Business Machines Corporation | Switching multi-initiator SCSI devices to a singular target bus |
| US6438604B1 (en) | 1998-10-05 | 2002-08-20 | Canon Kabushiki Kaisha | Digital video network interface |
| US7013354B1 (en) | 1998-10-05 | 2006-03-14 | Canon Kabushiki Kaisha | Channel protocol for IEEE 1394 data transmission |
| US6657973B1 (en) * | 1998-10-27 | 2003-12-02 | Matsushita Electric Industrial Co., Ltd. | Communications node, network system and method of controlling network system |
| JP3326399B2 (en) | 1998-12-17 | 2002-09-24 | 松下電器産業株式会社 | Communication node, information device having the same, and network system |
| US6256698B1 (en) | 1999-01-11 | 2001-07-03 | Sony Corporation | Method of and apparatus for providing self-sustained even arbitration within an IEEE 1394 serial bus network of devices |
| US7062456B1 (en) | 1999-02-09 | 2006-06-13 | The Chase Manhattan Bank | System and method for back office processing of banking transactions using electronic files |
| US6810452B1 (en) | 1999-03-19 | 2004-10-26 | Sony Corporation | Method and system for quarantine during bus topology configuration |
| US6374319B1 (en) * | 1999-06-22 | 2002-04-16 | Philips Electronics North America Corporation | Flag-controlled arbitration of requesting agents |
| US6628607B1 (en) | 1999-07-09 | 2003-09-30 | Apple Computer, Inc. | Method and apparatus for loop breaking on a serial bus |
| US6910090B1 (en) | 1999-09-21 | 2005-06-21 | Sony Corporation | Maintaining communications in a bus bridge interconnect |
| EP1090856A1 (en) * | 1999-10-04 | 2001-04-11 | LAB Industrie Misch- und Wiegetechnik GmbH | System and method for unloading of bulk material from a container, especially from a box-shaped transport container |
| US6691096B1 (en) | 1999-10-28 | 2004-02-10 | Apple Computer, Inc. | General purpose data container method and apparatus for implementing AV/C descriptors |
| US6959343B1 (en) | 1999-11-01 | 2005-10-25 | Apple Computer, Inc. | Method and apparatus for dynamic link driver configuration |
| US6671768B1 (en) | 1999-11-01 | 2003-12-30 | Apple Computer, Inc. | System and method for providing dynamic configuration ROM using double image buffers for use with serial bus devices |
| US6631426B1 (en) | 1999-11-02 | 2003-10-07 | Apple Computer, Inc. | Automatic ID allocation for AV/C entities |
| US8762446B1 (en) | 1999-11-02 | 2014-06-24 | Apple Inc. | Bridged distributed device control over multiple transports method and apparatus |
| US6618750B1 (en) | 1999-11-02 | 2003-09-09 | Apple Computer, Inc. | Method and apparatus for determining communication paths |
| US6813663B1 (en) | 1999-11-02 | 2004-11-02 | Apple Computer, Inc. | Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images |
| US8185549B1 (en) * | 1999-11-03 | 2012-05-22 | A9.Com, Inc. | Method and system for navigating within a body of data using one of a number of alternative browse graphs |
| US6587904B1 (en) * | 1999-11-05 | 2003-07-01 | Apple Computer, Inc. | Method and apparatus for preventing loops in a full-duplex bus |
| US6636914B1 (en) | 1999-11-05 | 2003-10-21 | Apple Computer, Inc. | Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases |
| TW448365B (en) * | 1999-11-15 | 2001-08-01 | Via Tech Inc | Bus arbitration method providing preemption function between control chip sets |
| US6457086B1 (en) | 1999-11-16 | 2002-09-24 | Apple Computers, Inc. | Method and apparatus for accelerating detection of serial bus device speed signals |
| US6728821B1 (en) | 1999-11-29 | 2004-04-27 | Sony Corporation | Method and system for adjusting isochronous bandwidths on a bus |
| US6751697B1 (en) * | 1999-11-29 | 2004-06-15 | Sony Corporation | Method and system for a multi-phase net refresh on a bus bridge interconnect |
| US6639918B1 (en) | 2000-01-18 | 2003-10-28 | Apple Computer, Inc. | Method and apparatus for border node behavior on a full-duplex bus |
| US7266617B1 (en) | 2000-01-18 | 2007-09-04 | Apple Inc. | Method and apparatus for border node behavior on a full-duplex bus |
| US7421507B2 (en) * | 2000-02-16 | 2008-09-02 | Apple Inc. | Transmission of AV/C transactions over multiple transports method and apparatus |
| US7050453B1 (en) * | 2000-02-17 | 2006-05-23 | Apple Computer, Inc. | Method and apparatus for ensuring compatibility on a high performance serial bus |
| US6831928B1 (en) | 2000-02-17 | 2004-12-14 | Apple Computer, Inc. | Method and apparatus for ensuring compatibility on a high performance serial bus |
| US6484171B1 (en) | 2000-03-31 | 2002-11-19 | International Business Machines Corporation | System method and computer program for prioritizing filter rules |
| US6718497B1 (en) | 2000-04-21 | 2004-04-06 | Apple Computer, Inc. | Method and apparatus for generating jitter test patterns on a high performance serial bus |
| US6618785B1 (en) | 2000-04-21 | 2003-09-09 | Apple Computer, Inc. | Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus |
| JP2001313646A (en) * | 2000-04-27 | 2001-11-09 | Sony Corp | Electronic device and method for controlling state of its physical layer circuit |
| US6757773B1 (en) | 2000-06-30 | 2004-06-29 | Sony Corporation | System and method for determining support capability of a device coupled to a bus system |
| US7328211B2 (en) | 2000-09-21 | 2008-02-05 | Jpmorgan Chase Bank, N.A. | System and methods for improved linguistic pattern matching |
| JP4097891B2 (en) * | 2000-11-27 | 2008-06-11 | 三菱電機株式会社 | Synchronization system using IEEE 1394 |
| US6891805B2 (en) * | 2001-02-06 | 2005-05-10 | Telephonics Corporation | Communications system |
| US7024505B2 (en) * | 2002-03-28 | 2006-04-04 | Seagate Technology Llc | Fair arbitration method in a distributed arbitration system |
| US7007123B2 (en) * | 2002-03-28 | 2006-02-28 | Alcatel | Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node |
| US6886051B2 (en) * | 2002-03-28 | 2005-04-26 | Seagate Technology Llc | Device discovery method and apparatus |
| US7987246B2 (en) | 2002-05-23 | 2011-07-26 | Jpmorgan Chase Bank | Method and system for client browser update |
| US7340650B2 (en) * | 2002-10-30 | 2008-03-04 | Jp Morgan Chase & Co. | Method to measure stored procedure execution statistics |
| US20040103199A1 (en) * | 2002-11-22 | 2004-05-27 | Anthony Chao | Method and system for client browser update from a lite cache |
| US7149752B2 (en) * | 2002-12-03 | 2006-12-12 | Jp Morgan Chase Bank | Method for simplifying databinding in application programs |
| US7085759B2 (en) | 2002-12-06 | 2006-08-01 | Jpmorgan Chase Bank | System and method for communicating data to a process |
| US7457302B1 (en) | 2002-12-31 | 2008-11-25 | Apple Inc. | Enhancement to loop healing for malconfigured bus prevention |
| US7417973B1 (en) | 2002-12-31 | 2008-08-26 | Apple Inc. | Method, apparatus and computer program product for ensuring node participation in a network bus |
| US8032439B2 (en) | 2003-01-07 | 2011-10-04 | Jpmorgan Chase Bank, N.A. | System and method for process scheduling |
| US7401156B2 (en) * | 2003-02-03 | 2008-07-15 | Jp Morgan Chase Bank | Method using control interface to suspend software network environment running on network devices for loading and executing another software network environment |
| US7379998B2 (en) * | 2003-03-31 | 2008-05-27 | Jp Morgan Chase Bank | System and method for multi-platform queue queries |
| US20040210696A1 (en) * | 2003-04-18 | 2004-10-21 | Meyer Michael J. | Method and apparatus for round robin resource arbitration |
| US20040230602A1 (en) * | 2003-05-14 | 2004-11-18 | Andrew Doddington | System and method for decoupling data presentation layer and data gathering and storage layer in a distributed data processing system |
| US7366722B2 (en) * | 2003-05-15 | 2008-04-29 | Jp Morgan Chase Bank | System and method for specifying application services and distributing them across multiple processors using XML |
| US7509641B2 (en) * | 2003-05-16 | 2009-03-24 | Jp Morgan Chase Bank | Job processing framework |
| US7353284B2 (en) * | 2003-06-13 | 2008-04-01 | Apple Inc. | Synchronized transmission of audio and video data from a computer to a client via an interface |
| US7668099B2 (en) * | 2003-06-13 | 2010-02-23 | Apple Inc. | Synthesis of vertical blanking signal |
| US20040255338A1 (en) * | 2003-06-13 | 2004-12-16 | Apple Computer, Inc. | Interface for sending synchronized audio and video data |
| US8275910B1 (en) | 2003-07-02 | 2012-09-25 | Apple Inc. | Source packet bridge |
| US7069278B2 (en) | 2003-08-08 | 2006-06-27 | Jpmorgan Chase Bank, N.A. | System for archive integrity management and related methods |
| US20050065965A1 (en) * | 2003-09-19 | 2005-03-24 | Ziemann David M. | Navigation of tree data structures |
| US7270227B2 (en) | 2003-10-29 | 2007-09-18 | Lockheed Martin Corporation | Material handling system and method of use |
| US7788567B1 (en) * | 2003-11-18 | 2010-08-31 | Apple Inc. | Symbol encoding for tolerance to single byte errors |
| US7995606B1 (en) | 2003-12-03 | 2011-08-09 | Apple Inc. | Fly-by and ack-accelerated arbitration for broadcast packets |
| US7502338B1 (en) | 2003-12-19 | 2009-03-10 | Apple Inc. | De-emphasis training on a point-to-point connection |
| US7421696B2 (en) * | 2003-12-22 | 2008-09-02 | Jp Morgan Chase Bank | Methods and systems for managing successful completion of a network of processes |
| US7237135B1 (en) | 2003-12-29 | 2007-06-26 | Apple Inc. | Cyclemaster synchronization in a distributed bridge |
| US7308517B1 (en) * | 2003-12-29 | 2007-12-11 | Apple Inc. | Gap count analysis for a high speed serialized bus |
| US20050144174A1 (en) * | 2003-12-31 | 2005-06-30 | Leonid Pesenson | Framework for providing remote processing of a graphical user interface |
| US20050175027A1 (en) * | 2004-02-09 | 2005-08-11 | Phonex Broadband Corporation | System and method for requesting and granting access to a network channel |
| US7183906B2 (en) * | 2004-03-19 | 2007-02-27 | Lockheed Martin Corporation | Threat scanning machine management system |
| US20050222990A1 (en) * | 2004-04-06 | 2005-10-06 | Milne Kenneth T | Methods and systems for using script files to obtain, format and disseminate database information |
| US20050231358A1 (en) * | 2004-04-19 | 2005-10-20 | Company Steven L | Search engine for singles with (GPS) position data |
| GB2429371B (en) | 2004-04-26 | 2008-03-26 | J P Morgan Chase Bank | System and method for routing messages |
| US7212113B2 (en) * | 2004-05-04 | 2007-05-01 | Lockheed Martin Corporation | Passenger and item tracking with system alerts |
| US20050251398A1 (en) * | 2004-05-04 | 2005-11-10 | Lockheed Martin Corporation | Threat scanning with pooled operators |
| US20050251397A1 (en) * | 2004-05-04 | 2005-11-10 | Lockheed Martin Corporation | Passenger and item tracking with predictive analysis |
| US7392471B1 (en) | 2004-07-28 | 2008-06-24 | Jp Morgan Chase Bank | System and method for comparing extensible markup language (XML) documents |
| US7366974B2 (en) * | 2004-09-03 | 2008-04-29 | Jp Morgan Chase Bank | System and method for managing template attributes |
| US20060059210A1 (en) * | 2004-09-16 | 2006-03-16 | Macdonald Glynne | Generic database structure and related systems and methods for storing data independent of data type |
| US20090132466A1 (en) * | 2004-10-13 | 2009-05-21 | Jp Morgan Chase Bank | System and method for archiving data |
| US7739436B2 (en) * | 2004-11-01 | 2010-06-15 | Sonics, Inc. | Method and apparatus for round robin resource arbitration with a fast request to grant response |
| US20060282886A1 (en) * | 2005-06-09 | 2006-12-14 | Lockheed Martin Corporation | Service oriented security device management network |
| US7684421B2 (en) * | 2005-06-09 | 2010-03-23 | Lockheed Martin Corporation | Information routing in a distributed environment |
| US8223666B2 (en) * | 2005-08-23 | 2012-07-17 | Cisco Technology, Inc. | Method of constructing a forwarding database for a data communications network |
| US7969995B2 (en) * | 2005-08-23 | 2011-06-28 | Cisco Technology, Inc. | Method and apparatus for constructing a forwarding database for a data communications network |
| US8065606B1 (en) | 2005-09-16 | 2011-11-22 | Jpmorgan Chase Bank, N.A. | System and method for automating document generation |
| US7499933B1 (en) | 2005-11-12 | 2009-03-03 | Jpmorgan Chase Bank, N.A. | System and method for managing enterprise application configuration |
| US7610172B2 (en) * | 2006-06-16 | 2009-10-27 | Jpmorgan Chase Bank, N.A. | Method and system for monitoring non-occurring events |
| US8483108B2 (en) * | 2006-07-24 | 2013-07-09 | Apple Inc. | Apparatus and methods for de-emphasis training on a point-to-point connection |
| US20080060910A1 (en) * | 2006-09-08 | 2008-03-13 | Shawn Younkin | Passenger carry-on bagging system for security checkpoints |
| CN101179516B (en) * | 2006-11-10 | 2010-06-09 | 北京航空航天大学 | Digraph based data distributing method |
| US8104076B1 (en) | 2006-11-13 | 2012-01-24 | Jpmorgan Chase Bank, N.A. | Application access control system |
| US7610429B2 (en) * | 2007-01-30 | 2009-10-27 | Hewlett-Packard Development Company, L.P. | Method and system for determining device criticality in a computer configuration |
| US9009235B2 (en) | 2008-06-17 | 2015-04-14 | Attivio, Inc. | Ordered message processing |
| US8312088B2 (en) * | 2009-07-27 | 2012-11-13 | Sandisk Il Ltd. | Device identifier selection |
| US8392614B2 (en) | 2009-07-27 | 2013-03-05 | Sandisk Il Ltd. | Device identifier selection |
| FR2951290B1 (en) * | 2009-10-08 | 2011-12-09 | Commissariat Energie Atomique | MULTI-SOURCE MEMORY DIRECT ACCESS CONTROLLER, CORRESPONDING COMPUTER PROGRAM AND PROGRAM |
| US8495656B2 (en) | 2010-10-15 | 2013-07-23 | Attivio, Inc. | Ordered processing of groups of messages |
| US9038177B1 (en) | 2010-11-30 | 2015-05-19 | Jpmorgan Chase Bank, N.A. | Method and system for implementing multi-level data fusion |
| US9292588B1 (en) | 2011-07-20 | 2016-03-22 | Jpmorgan Chase Bank, N.A. | Safe storing data for disaster recovery |
| US10540373B1 (en) | 2013-03-04 | 2020-01-21 | Jpmorgan Chase Bank, N.A. | Clause library manager |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2443101A1 (en) * | 1978-11-30 | 1980-06-27 | Ibm France | IMPROVEMENT IN PRIORITY INTERFACE SELECTION SYSTEMS |
| US4344134A (en) * | 1980-06-30 | 1982-08-10 | Burroughs Corporation | Partitionable parallel processor |
| US4412285A (en) * | 1981-04-01 | 1983-10-25 | Teradata Corporation | Multiprocessor intercommunication system and method |
| US4698752A (en) * | 1982-11-15 | 1987-10-06 | American Telephone And Telegraph Company At&T Bell Laboratories | Data base locking |
| IT1159351B (en) * | 1983-02-03 | 1987-02-25 | Cselt Centro Studi Lab Telecom | DISTRIBUTED STRUCTURE REFEREE CIRCUIT FOR BUS REQUESTS FOR A MULTIPROCESSOR SYSTEM |
| US5113523A (en) * | 1985-05-06 | 1992-05-12 | Ncube Corporation | High performance computer system |
| US4706080A (en) * | 1985-08-26 | 1987-11-10 | Bell Communications Research, Inc. | Interconnection of broadcast networks |
| US4897833A (en) * | 1987-10-16 | 1990-01-30 | Digital Equipment Corporation | Hierarchical arbitration system |
| DE3838945A1 (en) * | 1987-11-18 | 1989-06-08 | Hitachi Ltd | NETWORK SYSTEM WITH LOCAL NETWORKS AND WITH A HIERARCHICAL CHOICE OF PATH |
| US4811337A (en) * | 1988-01-15 | 1989-03-07 | Vitalink Communications Corporation | Distributed load sharing |
| US5027342A (en) * | 1989-05-03 | 1991-06-25 | The University Of Toronto Innovations Foundation | Local area network |
| US5138615A (en) * | 1989-06-22 | 1992-08-11 | Digital Equipment Corporation | Reconfiguration system and method for high-speed mesh connected local area network |
| US5150360A (en) * | 1990-03-07 | 1992-09-22 | Digital Equipment Corporation | Utilization of redundant links in bridged networks |
| US5301333A (en) * | 1990-06-14 | 1994-04-05 | Bell Communications Research, Inc. | Tree structured variable priority arbitration implementing a round-robin scheduling policy |
| US5353412A (en) * | 1990-10-03 | 1994-10-04 | Thinking Machines Corporation | Partition control circuit for separately controlling message sending of nodes of tree-shaped routing network to divide the network into a number of partitions |
| CA2093355A1 (en) * | 1990-10-03 | 1992-04-04 | David C. Douglas | Parallel computer system |
| FR2668626B1 (en) * | 1990-10-30 | 1992-12-18 | Thomson Csf | METHOD FOR CONFIGURING A MESH COMPUTER SYSTEM. |
| FR2676558B1 (en) * | 1991-05-15 | 1993-07-23 | Opticable | METHOD FOR AUTOMATICALLY DETERMINING THE CONFIGURATION OF A NETWORK. |
| DE69229167T2 (en) * | 1992-03-27 | 1999-11-04 | Alcatel Sa | Access control arrangement |
-
1992
- 1992-12-21 US US07/994,983 patent/US5630173A/en not_active Expired - Lifetime
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1993
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- 1993-12-16 CA CA002151369A patent/CA2151369C/en not_active Expired - Lifetime
- 1993-12-16 CA CA2503335A patent/CA2503335C/en not_active Expired - Lifetime
- 1993-12-16 EP EP01100800A patent/EP1094395B1/en not_active Expired - Lifetime
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- 1993-12-16 EP EP01100794A patent/EP1132821B1/en not_active Expired - Lifetime
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- 1996-09-24 US US08/710,970 patent/US5802289A/en not_active Expired - Lifetime
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