CA2539280A1 - High reliability multilayer circuit substrates and methods for their formation - Google Patents

High reliability multilayer circuit substrates and methods for their formation Download PDF

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Publication number
CA2539280A1
CA2539280A1 CA002539280A CA2539280A CA2539280A1 CA 2539280 A1 CA2539280 A1 CA 2539280A1 CA 002539280 A CA002539280 A CA 002539280A CA 2539280 A CA2539280 A CA 2539280A CA 2539280 A1 CA2539280 A1 CA 2539280A1
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CA
Canada
Prior art keywords
base substrate
conductor
thin film
conductors
conductive ink
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002539280A
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French (fr)
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CA2539280C (en
Inventor
Shaun Pendo
Rajiv Shah
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Medtronic Minimed Inc
Original Assignee
Medtronic Minimed, Inc.
Shaun Pendo
Rajiv Shah
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Filing date
Publication date
Application filed by Medtronic Minimed, Inc., Shaun Pendo, Rajiv Shah filed Critical Medtronic Minimed, Inc.
Publication of CA2539280A1 publication Critical patent/CA2539280A1/en
Application granted granted Critical
Publication of CA2539280C publication Critical patent/CA2539280C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/085—Using vacuum or low pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders

Abstract

A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Claims (31)

1. A method for forming a multilayer circuit substrate, comprising:
providing a dielectric base substrate;
forming conductors on the base substrate;
forming sacrificial structures on the base substrate and conductors to define areas to be protected from deposition of a dielectric layer;
vacuum depositing a dielectric thin film on the base substrate, the conductors and the sacrificial structures; and removing the sacrificial structures to leave a patterned deposited dielectric thin film on the conductors and the base substrate.
2. The method claimed in claim 1, wherein forming the conductors comprises:
depositing a blanket layer of a conductor material; and patterning the blanket layer of conductor material.
3. The method claimed in claim 2, wherein the blanket layer of conductor material is formed by physical vapor deposition.
4. The method claimed in claim 2, wherein the blanket layer of conductor material is formed by evaporation.
5. The method claimed in claim 2, wherein the blanket layer of conductor material is formed by chemical vapor deposition.
6. The method claimed in claim 2, wherein the blanket layer of conductor material is patterned by a photoresist lift-off process.
7. The method claimed in claim 2, wherein the blanket layer of conductor material is patterned by a chemical etching process.
8. The method claimed in claim 1, wherein the conductors are formed by a shadow mask patterning process.
9. The method claimed in claim 1, wherein the conductors are formed by a screen printing process.
10. The method claimed in claim 1, wherein the sacrificial structures are formed by a shadow mask deposition process.
11. The method claimed in claim 10, wherein the sacrificial structures are formed of aluminum and are removed using a ferric chloride solution.
12. The method claimed in claim 10, wherein the shadow mask deposition process utilizes a shadow mask having laser drilled via holes.
13. The method claimed in claim 1, further comprising mounting a circuit component on the deposited dielectric layer.
14. The method claimed in claim 1, wherein the base substrate comprises a hermetic via, and wherein one of the conductors is formed in contact the hermetic via.
15. The method claimed in claim 1, wherein the base substrate comprises a hermetic via, and wherein providing the base substrate comprises:
forming a via hole in the base substrate;
respectively forming multiple layers of conductive ink on sidewalls of the via hole;
filling a space between said sidewalls with conductive ink; and sintering the conductive material in the via hole.
16. The method claimed in claim 15, wherein forming said multiple layers comprises:
introducing a conductive ink to the via hole;
applying a vacuum to the via hole to form a layer of said conductive ink on sidewalls of the hole; and repeating said introducing and said applying to form said multiple layers of conductive ink on the sidewalls.
17. The method claimed in claim 16, wherein the conductive ink is introduced to the via hole by screen printing.
18. The method claimed in claim 16, wherein applying the vacuum eliminates voids in the conductive ink introduced into the via hole.
19. The method claimed in claim 16, wherein the vacuum is applied to one end of the via hole
20. The method claimed in claim 16, wherein the conductive ink used to fill the space between the sidewalls is less dilute than the conductive ink used to form said multiple layers.
21. The method claimed in claim 16, wherein applying the vacuum is followed by thermal processing to remove solvent and organic binder from the conductive ink.
22. The method claimed in claim 15, wherein providing the base substrate further comprises removing residual conductive material from surfaces of the base substrate.
23. The method claimed in claim 15, wherein the via hole is formed by laser drilling.
24. The method claimed in claim 23, wherein said laser drilling is followed by annealing to smooth the sidewalls of the via hole.
25. The method claimed in claim 1, wherein the base substrate comprises a hermetic via, and wherein the method further comprises:
forming a conductor on the base substrate in contact with the hermetic via; and forming a cap over the conductor and the hermetic via.
26. The method claimed in claim 25, wherein the cap is formed by a shadow mask deposition technique.
27. A multilayer circuit substrate, comprising:
a dielectric base substrate;
a conductor formed on the base substrate; and a patterned vacuum deposited dielectric thin film formed on the base substrate and the conductor.
28. The structure claimed in claim 27, further comprising an electronic component mounted on the deposited dielectric thin film and electrically connected to the conductor through the deposited dielectric layer.
29. The structure claimed in claim 27, further comprising:
a second conductor formed on the deposited dielectric thin film and connected to the first conductor through the deposited dielectric thin film;
and a second patterned vacuum deposited dielectric thin film formed on the deposited dielectric layer and the second conductor.
30. The structure claimed in claim 29, further comprising an electronic component mounted on the second deposited dielectric thin film and electrically connected to the second conductor through the second deposited dielectric thin film.
31. The structure claimed in claim 27, wherein the base substrate comprises a hermetic via, and wherein the conductor is formed in electrical contact with the hermetic via.
CA2539280A 2003-09-26 2004-09-02 High reliability multilayer circuit substrates and methods for their formation Expired - Fee Related CA2539280C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/671,996 US7138330B2 (en) 2002-09-27 2003-09-26 High reliability multilayer circuit substrates and methods for their formation
US10/671,996 2003-09-26
PCT/US2004/028600 WO2005034598A1 (en) 2003-09-26 2004-09-02 High reliability multilayer circuit substrates and methods for their formation

Publications (2)

Publication Number Publication Date
CA2539280A1 true CA2539280A1 (en) 2005-04-14
CA2539280C CA2539280C (en) 2011-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA2539280A Expired - Fee Related CA2539280C (en) 2003-09-26 2004-09-02 High reliability multilayer circuit substrates and methods for their formation

Country Status (8)

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US (3) US7138330B2 (en)
EP (1) EP1665915B1 (en)
JP (2) JP4790614B2 (en)
AT (1) ATE492146T1 (en)
CA (1) CA2539280C (en)
DE (1) DE602004030587D1 (en)
DK (1) DK1665915T3 (en)
WO (1) WO2005034598A1 (en)

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