CA2536799A1 - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

Info

Publication number
CA2536799A1
CA2536799A1 CA 2536799 CA2536799A CA2536799A1 CA 2536799 A1 CA2536799 A1 CA 2536799A1 CA 2536799 CA2536799 CA 2536799 CA 2536799 A CA2536799 A CA 2536799A CA 2536799 A1 CA2536799 A1 CA 2536799A1
Authority
CA
Canada
Prior art keywords
semiconductor
semiconductor substrate
semiconductor package
substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2536799
Other languages
French (fr)
Other versions
CA2536799C (en
Inventor
Satoshi Yamamoto
Tatsuo Suemasu
Sayaka Hirafune
Toshihiko Isokawa
Koichi Shiotani
Kazuya Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Fujikura Ltd.
Olympus Corporation
Satoshi Yamamoto
Tatsuo Suemasu
Sayaka Hirafune
Toshihiko Isokawa
Koichi Shiotani
Kazuya Matsumoto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd., Olympus Corporation, Satoshi Yamamoto, Tatsuo Suemasu, Sayaka Hirafune, Toshihiko Isokawa, Koichi Shiotani, Kazuya Matsumoto filed Critical Fujikura Ltd.
Publication of CA2536799A1 publication Critical patent/CA2536799A1/en
Application granted granted Critical
Publication of CA2536799C publication Critical patent/CA2536799C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

A semiconductor package includes a semiconductor element having a circuit element arranged on a first surface of a semiconductor substrate; an external wiring region arranged on a second surface of the semiconductor substrate; a support substrate arranged on the first surface of the semiconductor substrate; an electrode pad arranged on the first surface of the semiconductor substrate; and a through electrode reaching from the electrode pad to the second surface of the semiconductor substrate.

Description

DESCRIPTION
SEMICONDUCTOR PACKAGE AND MET~I017 OF MANUFACTURING TH$ SAME
TECIiNiCAL FIELD
The preseztt ixivention relates primarily to chip size semiconductor packages comprising semiconductor integrated circuits, particularly solid-state image sensors such as CCD and CMOS, and a method of manufacturing these packages.
Priority is claimed on Japanese Patent Application No. 2003-30484$, filed6on August 28, 2003, and Japanese Patent Application No. 2003-419613, filed on December 17, 2003, the contents of which ate incorporated herein by reference.
BACKGROUND ART
Coz~vent~ionally, when mounting semiconductor integrated circuits, particularly solid-state image sensors including CCD (Charge Coupled Device) or CMOS
(Complementary MetahOxide Semiconductor), the method shown in FIG. 13 is typically used. That is, in this mounting method, a solid state image sensor 1001 is placed ~n a receptacle 1002 made of ceramic or resin or the like, wire bonding 1003 is performed between the sensor and a lead frame (uot shown) to provide an electrical connectimn, and a glass lid 1004 is then fitted to provide a hermetic seal. Reference numeral 1005 indicates an outer lead.
Recently, with the progress in miniaturization, particularly in portable devices, there has been a demand for smaller housings and internal circuit boards. Of course, the demand for such miniaturization also exists for semiconductor elements, which are one of the surface mounted components which male up a circuit board. Furthermore, the same miniaturization is demanded of solid-state image sensors, which are a form of semiconductor element. It has been difficult to satisfy demand for such m.iniaturi~ation for conventional semiconductor packages as shown in FICx. 13.
In order to meet this demand for miniaturization of semiconductor elementh, research and development is being actively pursued in the field of Chip Size Packages (referred to as "CSP" below). Above all, in recent years the development of wafei level CSPs is being actively pursued with an object of providing srnallex, liglxter and thinner packages.
As described in the specification of Japanese Patent No. 3313547, a wafer level CSP typically has resin and rewiring on the silicon wafer element surface, and also has metal posts or solder balls for providing solder connections, arranged in the desired locations on the silicon wafer element surface.
However, it is difficult to apply the wafer level CSP as described above to a solid-state image sensor. This is because in the case in which a typical CSp manufacturing process is applied to a solid-state image sensor manufacturing process, the rewiring and the post metal and the like prevent a light receiving region from being secured, and asla result the element cannot fulfill its funedon satisfactorily.
In order to solve the above problem, in Japanese Unexamined Patent Application, First Publication No. 2001-351997, a CSP is proposed in which the rewiring and the solder balls and the like are placed on a semiconductor substrate surface which is opposite to that on which the semiconductor element is formed. However, with the techniques prqposed in Japanese Unexamined Patent Application, Fiurst Publication No. 2001-351997, there is concern that damage may result from etching for forming noz~-through at~d deep hble performed fi-om the light receiving region surface side of the solid-state image senior, or the plasma exposure performed when forming the conductive layer.
Furthermore,jin the step of subjecting the rear surface to etching for thinning, a highly accurate etching technique is required so as to expose the conductive layer evenly.
Consequently, this invites a rise in manufacturing costs by requiring special manufacturing equipment or the like. In addition, further steps are required to ensure that the etched silicon surface and the exposed conductive layer are properly electrically insulated from one another.
k'urthermore, another method foz solving the above problem is proposed iru National Publication of Japanese Translated Version No. H09-511097 (PCT
publication No. W095/19645), and it is disclosed that by making use of partial notches provided in the silicon substrate, the metal wires which extend from the electrode pads on the sur~ce where the element is formed can be provided on the opposite surface. however, because the structure of this type of CSP is such that part of the metal lines drawn out from the semiconductor element is exposed at the end face of the silicon substrate, there is ~
problem in that wire corrosion tends to occur, which causes a deterioration (reducrion) in reliability. Purtltermore, because of the need for pattern formation, the notches are formed by V-grooving. These V-shaped grooves must be formed so as to be the same width as the scribe width or wider, which presents a problem in that it leads to a reduction in the yield of the semiconductor element_ DISCL,OSUR.E OF THE INVENTION
An object of the present invention is to provide a semiconductor package for a wafer level CSP, which can be miniaturized, has high reliability, and is inexpensive, and which does not cause any deterioration in the performance of semiconductor ele~rients particularly solid state image sensors, end also to provide a method of rnanufactuzing such a semiconductor package_ A semiconductor package according to the present invention includes: a semiconductor element provided with a circuit element on one surface of a semicopduetor substrate; an external wiring region provided on an other surface of the semiconduktor substrate; a support substrate disposed on the one surface of the semiconductor su$strate;
an electrode pad disposed on the one surface of the semiconductor substrate;
and a~
through-electrode which extends from the electrode pad through to the other surface of the semiconductor substrate.
With the semiconductor package according to the present invention, wire taonding as performed with conventional packages is not required, and for example, it is possible to establish an electrical connection between the electrode pad and the external termihal of a separate substrate via external wiring, without being limited to the arrangement oflthe electrode pad on the one surface of the semiconductor substrate. Consequently, miniaturization of the semiconductor package can be realized. Furthermore, beca~nse notched regions such as 'V-shaped grooves are not required, none of the semiconductor substrate is wasted, and the yield (area utilization) ofthe circuit element can be increased.
Furthermore, the,through-electrode can be processed entirely using typicals semiconductor manufacturing equipment. Cozisequently, an inexpensive and small semiconductor package can be realized.
Photolithographic techniques used in normal semiconductor manufacturing processes can be applied to the through-electrode. Because the processing accuracy of the through-electrode is determined by the semiconductor photolithographic process, mierofabrication can be realized. Consequently, the semiconductor package of the present invention is readily compatible with other circuit substrates in which the external terminals are formed with a fine pitch using photolithographic techniques, and interconnection of the terminals is possible. As a result, it is possible to provide a semiconductor package including a plurality of semiconductor elements in a stacked arrangement, namely a semiconductor package having three dimensional layered wiring.
A connection section for providing a connection to an external terminal may be provided on the external wiring region.
An adhesive layer may be provided on the one surface of the semiconductatr S substrate, and this adhesive layer may adhere and secure the one surface of the semiconductor substrate to the support substrate.
The electrode pad may be disposed on the one surface of the semiconductot~
substrate in that region where the circuit element is not present.
An external wire which extends from the through-electrode and connects t~ the extexnal wiring region may be provided. In this case, photolithographic techniques used in normal semiconductor manufacturing processes can be applied to the external wirh~g.
Consequently, microprocessing is possible for the external wiring, as for the through-electrode. .As a result, the semiconductor package of the present invention is readitly compatible with other circuit substrates in which the external terminals are formed with a 1 S fine pitch using photolithographic techniques, and interconnection. of the terminals is possible.
The entire other surface side of the semiconductor substrate, excluding they connection sectioxa, zrray be covered by a protective film. In this case, on the othet surface of the se~tz~,iconductor substrate, the wiring configuration is such that the metal portion is not exposed, and a semiconductor package with high reliability (high moisture re~stance) can be realized. Specifically, in a semiconductor package including a solid state ilhciage sensor, any deterioration in the performance of the solid state image sensor can b~
controlled by covering the whole surface except the metal posts with a protective elm.
Consequently, a low cost CSP level semiconductor package which is both small alnd highly reliable can be realized without any redudbion in performance.

The support substrate may be made of a material which is optically tsanspatent. In this case, the semiconductor package may include, as the circuit element, a solid-state image sensor with a light receiving region (CCD, CMOS for example), or another type of optical element. Consequently, a small semiconductor package which includes a sblid-S state image sensor or another type of optical element can be provided.
The adhesive layer may be provided at least on the one surface of the semiconductor substrate, in a region where the electrode pad is provided. In this case, the region where the electrode pad is provided which contlects to the through-electrodb, is adhered to the support substrate directly via the adhesive layer. Therefore physical reinforcement of the through-electrode by the support substrate is aeltieved.
As a result, sem~icoztductor packages can be provided with high yield.
The external wiring region may be awar~ged in an opposing relatlonsh.ip to ~aa external terminal. In this case, it is easy to electrically connect the external wiring region provided on the other surface of the semiconductor substrate to the external terminal.
Two or more senniconductor substrates may be provided in a layered conf'rguration_ In this case, by providing two or more sezxiiconductor substrates in a layered configuration, it is possible to provide a high futaCtion semiconductor package.
An external wire for connecting to a terminal of another semiconductor eldment may extend from the througlx-electrode. In this case, it is possible for a given through-electrode on one of the plurality of semiconductor substrates to function as an intelrpvser.
Those parts of the through-electrode which are bonded to the electrode pad may be provided within a plane of the electrode pad. 1n this case, even if the through-eled~trodes are abnomlally shaped in the cross-section direction of the semiconductor paekagf, for example thick in the middle or narrow in the middle (a shape in which the approximate center is thicker or thinner than the ends), a construction in which the entire end flies of the through-electrode is bonded completely to the electrode pad can be realized.
Accordingly, it is possible to obtain a highly reliable electrical connection due to such factors as now wiring resistance in the connection section between the electrode pad and the thro~gh-electrodes. Furthermore, because a state results in which the entire end face of they through-electrode is bonded completely to the electrode pad, there is rio heat history related deterioration in cbaracteristics, and therefore the resulting semiconductor package has high environxncntal reliability. .
A semiconductor package manufacturing method of manufacturing a semiconductor package comprising a semiconductor element with a circuit element provided on one surface of a semiconductor substrate and an external wiring region provided on an other surface of said semiconductor substrate according to the present invention ixlcludes a step A of adhering and securing a support substrate to the ones surface of said semiconductor substrate; a step B of thinning the other surface of the semiconductor substrate; a step C of forming a thmugh-hole which reaches through to an 1 S electrode pad disposed on the one sltrface of the semiconductor substrate, from the other surface of the semiconductor substrate; and a step 17 of forming a through-electrode in the through-hole.
According to the semiconductor package manufacturAZ~g method of the present invention, wire bonding as performed with conventional packages is not required, ~azld it is possible to establish an electrical connection betweezt the electrode pads and the external terminals of a separate substrate via external wiring, without being limited to the arrangement of the electrode pads on the one surface of the semiconductor substrarte, fox example. Consequently, miniaturization of the semiconductor package can be realized.
Furthermore, the through-electrodes can be processed entirely using standard semiconductor manufacturing equipment. Consequently, a semiconductor package which g is both inexpensive and small can be realized.
External wires, for example, can be formed in a given loca'on on the other~surface of the semiconductor substrate via the through-electrodes. As a result, it is possiblb to provide a semiconductor package including a plurality of substrates in a stacked arrangement, namely a semiconductor package having three dimensional layered Wiring.
Because notched regions such as V-shaped grooves are not required, none mf the semiconductor substrate is wasted, and the yield (area utilization) o~the circuit elehient can be increased, Furthermore, all processes subsequent to the process for bonding and securfng the support substrate to the semiconductor substrate are performed from the other surfl~ee of the semiconductor substrate. Consequently, damage to the circuit elements duxin~
processing by plasma exposure or the like Can be reduced.
According to the above, through-electrodes can be formed in a semicondudtor substrate manufactured according to standard manufacturing processes, without clanging the arrangement or shape of the wiring of the semiconductor substrate.
Consequently, semiconductor packages with reduced size, higher functionality and higher density become possible.
In the step C, the through-hole may be formed so that at least in that part whence the through-hole contacts the electrode pad, a cross section of the through hole is disposed inside the electrode pad. In this case, the through-hole is formed so that at least itt that part where the through-hole contacts the electrode pad, a cross section of the through-Bole is disposed inside the electrode pad, even if the through-holes are abnormally shaped in the cross-section direction of the semiconductor package, for example thick in the middle or narrow in the middle (a shape in which the approximate center is thicker or thittnor than the ends), the entire e~.d face of the through~lectrode formed by filling the through-holes with an electroconductive material, can be joined completely to the electrode pad, g'Ihis has such advantages as a lowering of wiring resistance izt the connection section bdtween the electrode pads and the through-electrodes, which results in a highly reliable electrical connection. Furthermore, because the entire end face of the through-electrode canibe joined completely with the electrode pad, there is no deterioration in characteristics due to heat history or the like, which enables the manufacture of a semiconductor with high environmental reliability.
In addition, by forming the through-holes so that at least in those parts wheae the through-holes contact the ele~ode pads, the cross-section of the through-holes are disposed inside the electrode pads, the electrode pad can act as an etching-stop layer in the etching process used to form the through-holes. Consequently, the process of forrihing the through-holes can be halted at the point in time when the surfaces of the electrode pads, on the side which is bonded to the semiconductor substrate, are exposed inside the th~ough-holes. Accordingly, such defieiexxcies as the through-holes penetrating completely through to the surface of the electrode pads can be prevented. Furthermore, the etching performed to form the through-holes does not damage the circuit elements provided on the surface of the semiconductor substrate.
In the step C, the formation of the through-hole may be halted at the point ~n time when the electrode pad is exposed inside the through-hole.
In the step D, an external wire for connecting the external wiring region totthe through-electrode may be formed at the same time as the through-electrode is forded inside the through-hole.
In the step D, a connection section for connecting to an external terminal shay be provided on the external wiring region.
In the step A, a semiconductor element which includes a semiconductor stlbstsate in wafer form may be prepared, and after the step D, there may be a step E of dicing tie semiconductor substrate in wafer form.
A semiconductor substrate may be used in which the electrode pad is arranged on the one surface of the semiconductor substrate, ita a region where the circuit element is not provided.
After the step D, there tray be a step of coverixxg the entire other surface side of the semiconductor substrate, except for the cotaz~ection section with a protective film. ~n this case, a wiring configuration is obtained for the reverse side (the other side) of the semiconductor package in which the metal portions are not exposed, enabling a highly 10 reliable (highly moistwre resistant) semiconductor package to be realized.
BRIEF DESCRIPTION OF 'TIIE DRAWINGS
FIG. IA is a plan view showing an example of a semiconductor package according to a first aspect of the present invention, FIG. 1B is an outline cross-sectional view along the line X-X in FIG. 1A.
FIG. 1C is a perspective view of another example of the semiconductor package according to the first aspect of the present invention, seen from the part corresponding to the base in FIG. 1A.
FIG. 2 is an outline cross-sectional view showing an example of sexnicondtictor packages according to the first aspect of the present invention in wafer form.
FICi. 3A is an outline cross-sectional view showing an example of the semiconductor package according to the first aspect of the present invention, whete an adhesive layer pattern is provided.
FIG. 3B is a plan view of FIG. 3A.
FIG. 3C is a plan view showing an example of the semiconductor packaged with an adhesive layer pattern different from that of the semiconductor package in FIG. 3)3.
FIG. 3D is a plan view showing an example of the semiconductor package f~vith yet another adhesive layer pattern different from that of the semiconductor package iri FIG. 3B.
FIG. 4A is an outline cross-sectional view showing an example of a step ini the semiconductor manufacturing process according to a first aspect ofthe present invention.
FIG. 4B is an outline cross-sectional view showing an example of a step which follows that of FIG. 4A.
FIG. 4C is an outline cross-sectional view showing an example of a step wkiich follows that of FIG. 4B.
FIG. 4D is an outline cross-sectional view showing an example of a step which follows that of FIG. 4C.
FIG. 5A is an outline cross-sectional view showing an example of a step ww~iich follows that of FIG. 4D.
FIG. 5B is an outline cross-sectional view slowing an example of a step which 1 S follows that of FIG. 5A.
FIG. SC is an outline cross-sectional view showing an example of a step wI'ich follows that of FIG. 5B.
FIG. 6A is an outline cross~sectional view showing an example of a step iri the semiconductor package manufacturing process usilxg a setz~iconductor substrate inl wafer form, according to a first aspect of the present invention.
FIG. 6B is an outline cross-sectnonial view showing an example of a step wiilich follows that of FIG. 6A.
FIG. 6C is an outline cross-sectional new showing an example of a step ulhich follows that of FIG. 6B.
FIG. 6D is an outline cross-sectional view showing an example of a step v~hich follows that of FIG, 6C.
FIG. 6E is an outline cross-sectional view showing an example of a step which follows that of FIG. 6D, FIG. 7A is an outline cross-sectional view showing an example of a semiednductor package according to a second aspect of the present invention.
FIG. 7B is a perspective view of another example of a semiconductor package aeeoxdiztg to the second aspect of the present invention, seen from the part corresponding to the base in FIG. 7A.
FIG. 8 is a cross-sectional view showing an example of semiconductor packages accordirig to the second aspect of the present ixxvention, in wafer form.
FIG. 9 is an outline cross-sectional view showing an example of the semicmnductor package according to the second aspect of tlxe present invention, where an adhesive layer pattern is provided.
FIG. 10A is an outline cross-sectional view showing an example of a step i~
the semiconductor manufacturing process according to the seeoz~d aspect of the present invention.
FIG. l OB is an outline cross-sectional view showing an example of a step which follows that of FIG, 10A.
FIG. lOC is an outline cross-sectional view Showing an example of a step ~ivhich follows that of FIG. 1 OB.
FIG. 1 1A is an outline cross-sectional view showing az~ example of a step in the semieonduGtox pacltage manufacturing process using a semiconductor substrate l.t~iwafer fortrt, according to the second aspect of the present invention.
FIG. 11B is an outline cross-sectional view showing axt example of a step which follows that of FIG, 11 A.

FIG. 11 C is an outline cross-sectional view showing an example of a step v4hich follows that of FIG. 11 B.
FIG. 11D is an outline cross-sectional view showing an example of a step Which follows that of FIG. 11 C.
FIG. 12 is an outline cross-sectional view showing an example of a semiconductor pad on which a dummy electrode pad is provided, according to the second aspect df the present invention.
FIG. 13 is an outline cross-sectional view showing an example of a conver~iorral semiconductor package.
BEST MODE FOR CARRYIhiG OUT THE 1NYENTION
As follows is a description of the preferred embodiments of the present invlention, with z~eference to the drawings. However, the present invention is not limited to the embodiments below, and for example the structural elements of these embodirnenis may be appropriately interchanged.
(First Aspect) First, a semiconductor package according to a first aspect of the present ini~ention is described with reference to FIG. 1A through FIGS. 3D.
FIG. 1 A is a plan view showing au example of the semiconductor package according to the first aspect of the present invention. FIG. 1B is a cross-sectional view along the line X-X in FIG, 1A. fIG. 1C is another exatr~ple of a semiconductor package according to the first aspect of the present invention, representing a perspective viisw seen from the part corresponding to the base in FIG. 1A. The semiconductor packages~shown in FIG. 1A through FIG. 1C are shown after being cut into individual chips by s dicing i4 process. Furthermore, the semiconductor package shown in FIG. 1 C has the same construction as that shown in FIG. 1 A and FIG. 1 B, with the exception that a protelctive layer 113 is not provided.
FIG. 2 is a cross-sectional view showing an example of semiconductor packages in wafer form before beizlg cut into individual chips. Iz~. the present invention, semiconductor packages which are prepared by using a semiconductor substrate in wafer form and in a state they are not cut into individual chips are defined as the semiconductor packages in wafer form.
hn FIG. 1 A through FIG. 1 C, and FIG, 2, reference numeral 100 indicates ri semiconductor package, 101 ixxdxcates a semiconductor substrate, 102 indicates a semiconductor element, 103 indicates a circuit element, 104 indicates a support substrate, 105 indicates an adhesive layer, 106 indicates an electrode pad, 107 indicates an eliectrical insulation film, 108 indicates a through-electrode, 109 indicates an external wire, ~ 10 indicates an external wiring region, 111 indicates a metal post, 112 izxdicates a thrdiugh-hole, and 113 indicates a protective film_ The description below uses the example of a solid-state image sensor as the semiconductor element 102. Furthertxiore, the description omits a detailed description of the coz~uction and the like of the semiconductor element itself, describing only hose parts which relate to the present invention.
As shown in FIG. 1B, in this semiconductor package 100, the semiconduetbr element 102, including a circuit element 103 including a light receiving setlsor (ndt shown), and a signal processing circuit (not shown) and the like, provided on one surface 1901a of the semiconductor substrate 101, is bonded to the support substrate 104 by the adhesive layer 105.
The electrode pads 106 are provided in regions of the surface 1 O1 a of the semiconductor substrate 101 where the circuit element is not formed. 1n~ the semiconductor substrate 101, through-holes 112 are formed in the sections where the electrode pads are provided, from the other surface 101b through to the one surfae~ lOla.
Furthermore, electrical insulation film 107 is provided on the other surfacellOlb of S the semiconductor substrate 101, and on the inside surface ofthe through-holes 11~. In addition, through-electrodes 108 are provided inside the through-holes 112 via then electrical insulation film 107. The section 108b of the through-elecfxodes 108 whibh contacts the electrode pad 106 is provided within the plane of the bottom surface 1I06a of the electrode pad 106. In other words, the cross-sectional area of the section 108biof the 10 through-electrodes 108 which contacts the electrode pad 106 is less than the area df the bottom surface 106a of the electrode pad 106, and the through-electrodes 108 are formed such that the section 108b which contacts the electrode pad 106 does not protrude from the bottom surface 106x. Furthermore, in the semiconductor package 100 used as an example in FIG. 1B, the section 108b of the through-electrodes 108 which contacts the eler.~rode 15 pad 106 is the end face nearest the surface lOla of the semieondtxctor substrate 10l, hence the end face which joins the electrode pad 106.
The shape of the through-holes 112 and the through-electrodes 108 in the atoss-sectional direction of the seznicorxductor package 100 is not limited to that shown in FIG. 1, and abnormal shapes, such as thick in the middle or narrow in the middle (that is the approximate center is thicker or thinner than the ends), may also be used.
The external wires 109 which extend from the through-electrodes 108 are provided on the other surface 101 b via the electrical insulati,on~ film 107.
External wiring regions 110 are provided ou the other surface 101 b, and ark connected electrically to one end of the external wires 109. Furthermore, metal posts 111, acring as a connection section, are provided on the external wiring regions 110 so ~s to protrude from the surface of the protective film 113 which covers the other surface! 101 b of the semiconductor package 100. Providing these metal posts 111 allows the semiconductor package 100 to be connected to the external terminals of another su~stxate or the like more easily.
The other surface 101 b of the semiconductor substrate 1 O l is covered with the protective layer 113, except fox where the metal posts 111 are provided.
As shown in FIG. 1C, it is possible to not provide the protective film 113, llleaving the through,-electrodes 108 and the external wires exposed.
Semiconductor silicon substrates and the life can be used as the semiconductor substrate 101.
As the suppor.~t substrate 104, a substrate is used which is made of a materitll having sufficient practical transrnissivity of the wavelength sensitivity range, that is the ei~ective wavelength range, of the solid-state image sensor, namely the semiconductor elemjent 102, Particularly, the material preferably has a coefficient of thermal expansion which closely matches that of the semiconductor silicon substrate at the bonding temperature wl~n bonded to the semiconductor element 102.
The adhesive material which makes up the adhesive layer 105 is made of a~
material which has properties of electric insulation, and has sufficient transznissivity. Pref~rxed adhesive materials for the adhesive layer 105 include polyixnide resin, epoxy resirl~ and benzocyclobutane (BC8) resin, for example.
If a mierolen~s (not shown) is provided on the light receiving sensor includbd in the circuit element 103, then as shown in FIG. 3A and FIG. 3B, as the adhesive Iayer BIOS, an adhesive layer pattern l O5a which has an opening in the region over tire circuit element I 03 zxxay be provided on the one surface 1 O1 a of the semiconductor substrate 1 O 1 where the electrode pads are provided. Tlae semiconductor element 102 and the suppol;tlsubstrate 104 are bonded together by this adhesive layer pattern lOSa, thus providing a gap 114 over the circuit element 103. As a result, light from external sources can enter the micr~lens without passing through the adhesive layer pattern l OSa, allowing sufficient optical performance by the microlens (not shown).
If the adhesive layer pattern lOSa is not present above the circuit element provided oz~ the one side lOla of the semiconductor substrate 101, then suli:icient transmissivity is no longer required. Accordingly, a5 the adhesive material which fakes up the adhesive layer pattern lOSa, standard thermosetting type adhesives and ultratviolet hardening type adhesives and the like can be used.
Furthermore, as shown in FIG. 3C, there is no need to provide the adhesivellayer pattern l OSa around the entire boxder of the circuit element 103, and it may be provided on those regions of the one surface 1 O 1 a of the semiconductor substrate 101 where the electrode pads 106 are provided. In addition, as shown in FIG. 3D, the adhesive ialyer pattern lOSa may be pz'ovided so as to cover the electrode pads 106, 1 S In the present invention, the adhesive layer pattern lOSa is not limited to thrr patterns described above, and any form of pattern may be used provided that it cari physically reinforce the through-holes 112.
Standard materials used izt the semiconductor manufacturing process such ~s aluminum and copper are used to make the through-electrodes 108, the external wires 109 and the external wiring regions 110, but for the electrical wiring, any material can ~e used provided that it is a metal which does trot negatively affect the semiconductor eletrient 102.
The material used to make up the metal posts 111 is a material which can ~stablisll a good connection with external terminals, and generally, preferable materials inc~trde copper, gold and solder.
The protective film 113 is made of a material having electrical insulating pl-operties, sufficient thermal resistance, and sufficient corrosion resistance. The protective film 113 is preferably a silicon nitride film or silicon oxide film or the like, formed using a plasma CVD method. The material of which the protective filin 113 is made may be polymeric resin material such as a polyimide resin, a epoxy resin, a benzocyclobutene (BCB)gresin, or a resin foz~ forming a solder mask, or the like.
Next, a method of manufacturing the semiconductor package according to the first aspect of the present invention is described with reference to FIG. 4A through FIGC 4D, FIG. 5A through FIG. SC, and FIG. 6A through FIG. 6E.
FIG. 4A through FIG. 4D and FIG. 5A through FIG. SC are cross-sectional views showing an example of a manufacturing process for semiconductor packages using a diced semiconductor element. FIG. 6A through FIG. 6E are cross-sectional views showing an example of a rmanufacturing process for semiconductor packages using a semiconductor substrate in wafer form.
Here, the description is based primarily on FIG. 4A through FIG. 4D and FIG.

thzrough FIG. SC.
First, as shown in FIG. 4A, a semiconductor element 202, including a eircilit element 203 including a light receiving sensor (not shown), and a signal processing circuit (not shown) and the like, provided ozt one surface 201 a of the semiconductor substrate 201, and a support substrate 204 on a surface 204a of which is provided au adhesive layer 205, are prepared.
The member used as the support substrate 204 preferably hes a Coef$cientfof thermal expansion which closely matches that of the semiconductor silicon substrate 202 at the bonding tennperature when bonded to the semiconductor substrate 201.
Specifically, such members as those made of Pyrex (registered trademark) glass, and the glass;
substrates typically used in liquid czystal substrates, are suitable for use in the i9 manufacturing method of the present aspect, If the circuit element 203 is not requiked to have optical characteristics, then the support substrate 204 need not be transparent.:
Preferred adhesive materials for use when performing thermocompression bonding of the semiconductor element 202 and the support substrate 204 include polyimide~resin, epoxy resin, or BCB resin or the like.
Because the semiconductor element 202 is a solid-state image sensor including a light receiving sensor, the adhesive material used must have sui~tcient practical transmissivity of the sensitive wavelength range, that is the effective wavelength range, of the semiconductor element 202.
Because of limitations imposed by the microlens (not shown) or the like placed on the light receiving sensor of the circuit element 203, if an adhesive layer pattern which has an opening so as to omit the adhesive material in the area of the circuit element 20B is used as the adhesive layer 205, then transmi.ssivity is not required of the adhesive mate~al, and standard thermosetting type adhesives and ultraviolet hardening type adhesives anti the like I S can be used. In this case, the adhesive layer 205 should be thicker than the microlbns.
Furthermore, the method used to bond the semiconductor element 202 andithe support substrate 204 is not limited to thermocompression bonding, and any bondifng method can be applied, such as metal eutectic bonding and anode bonding, provi.d~d that the bonding method does not impair the function of the semiconductor element.
FIG. 4B and FIG. 6A show the state of the semiconductor package after bdnding of the semiconductor element 202 and the support substrate 204 is completed.
As shown in FIG. 4C and FIG. 6B, the semiconductor substrate 201 is they polished and thinned down from an other surface 201 b side of the semiconductor substrate 201.
In this polishing process, a polishing method which uses a standard chemi,~al mechanical polisher (CMP) or back grinder (BG) is preferred, and yet more preferable is a polishing process which uses both these devices.
The upper limit in terms of how far the semiconductor substrate 201 can beg polished is determined by the maximum depth at which the circuit element 203 operates 5 (for exannple the thickness of the well layer or the buried layer or the like), and theiamount of polishing can be determined arbitrarily within this limit. The amount of polishing of the semiconductor substrate 201 can be determined appropriately within the range of the upper limit ~z~entioned above based on the subsequent etching process of the semiconductor substrate 201 and the arrangement of the electrode pads 206.
10 In addition, the polishing process is not limited to methods using a BG or C~IvfP, and any method may be used provided that the method can thin down the othex su~ace 201 b of the semiconductor substrate 201 evenly and does not impede the subsequent etching mask formation process. Examples of polishing methods which may be used include wet etching methods using te~amethylammoriium hydroxide ~TM~ solution or 15 potassium hydroxide (KOH) solution or the like, or dry etching methods such as reactive ion etching (RIE) and chemical dry etching (CDE).
As shown in FIG. 4D, pattern formation of a thin film 207 is performed on~the thinned down other surface 201c of the semiconductor substrate 201, to act as a mask during subsequent etching of the semiconductor substrate 201.
20 The thin film 207 is preferably deposited under conditions which do not cause any deterioration in the fiutctionality of the semiconductor element 202.
Particularly, ~f the semiconductor element 202 is a solid-state image sensor, the thin film 207 is preferably deposited under conditions which do not cause any deterioration in the functionality of a thin film made of organic materials such as a color filter or microlens placed on the light receiving sensor of the circuit element included in the semiconductor element.
The thermal resistance of the organic materials is typically around 250°C.
As the thin film 207, films which can be deposited at approximately 200°CSsuch as low temperature PCVD oxide films and low temperature PCVD nitride films, or fifms applied by spin coating such as spin on glass (SOG) films and fluor9oresin films, are preferable.
Furthermore, the pattern for the thin film 207 is determined as appropriate according to the etching pattern of the subsequent etching process of the semicondhctor substrate 201. For a silicon (100) substrate of the type typically used to form semiconductor elements, in terms of the ease of performing subsequent anisotropia etching of the semiconductor substrate 201, the thin film 207 preferably has a rectangular pattern.
As shown in FIG, SA and FIG. 6C, by then performing anisotropic etching~of the semiconductor substt'aate 201 using the thin film 207 as a mask, through-holes 208 scan be formed frot'zt the other surface 201 c of the semiconductor substrate 201 through to ithe one surface 201a, in the locations of the electrode pads 206. Consequently, an other surface 206a (the base) of the electrode pads 206 is exposed on the other surface 201 b side of the semiconductor substrate 201, via the through-holes 208.
Here, in this step, the through-holes 208 are formed such that in at least thdse parts where the through-holes 208 contact the electrode pads 206, a cross-section 208b perpendicular to the depth direction of the through-holes 208 is provided within tfle plane of the other surface (base) 206a of the electrode pads 206. In other words, the threugh-holes 208 ate formed such that the entire joint surface between the through-elec~des, which are formed in a subsequent process by filling the through-holes 208 with ari electroconductive material, and the electrode pads 206, is disposed withixi the plane of the other surface (base) 206a of the electrode pads 206.
In the present invention, the shape of the through-holes 208 in the cross-selction direction. of the semiconductor substrate 201 is not limited. to that shown in FIG. 5 land FIG.
6, and the through-holes may be irregularly shaped, for example thick in the middlb or narrow in the middle (that is a shape in which the approximate center is thicker or thinner than the ends).
In addition, in this step, the formation of the through-holes 208 is halted at the point in time when the other surfaces 206a of the electrode pads 206 are exposed inside the through-holes 208.
Here, in this step, exposing the other surface (base) 206a of the electrode p~lds 206 to the inside of the through-holes 208 means that a portion of the other surface (bane) 206a of the electzode pad 206 with an area approximately equivalent to the size of the tlhough-holes z08 (the area of the cross-section 208b perpendicular to the depth direction df the through-holes 208) is exposed.
For the anisotropic etching, a wet etching method using tetramethylammonfum hydroxide (T~A~ solution or potassium hydroxide (KOF~ solution or the like is.
preferred, but dry etching methods such as reactive ion etching (RIE) and chemical dry etching (CT~E) can also be used.
In the manufacturing method of this aspect, because plasma is irradiated frbm the other surface 201 c side of the semiconductor substrate 201 even when a dry etching method is used, there is no danger of the circuit element 203 being damaged by thd plasma exposure, causing its performance to deteriorate.
Furthermore, in this etching step, an insulating film (not shown) such as a ifhermal oxidation film provided on the other surface (base) 206a side of the electrode pad X06 functions as an etch stopper, and the support substrate 204 bonded by the adhesive layer 205 functions as physical reiztforcement for the electrode pads 206, and consequently the through-holes 208 can be formed in a stable manner. Furthermore, by usi~.g the insulating film provided on the other surface (base) 206a side of the electrode pad 206 as an elteh stopper, the formation of the through-holes 208 can be halted at the poixat in time vahen the other surface (base) 206a side of the electrode pad 206 is exposed inside the throu~h-holes 208. Accordingly, such deficiencies as the through-holes penetrating completely t)~rough to the surface of the electrode pad can be prevented. Furthermore, there is no dancer of the circuit element 203 provided on the one surface 201 a of the semiconductor substrate 201 being damaged.
Furthermore, the through-holes 208 can easily be formed so that at least in those parts where the through-holes 208 and the electrode pads 206 contact each other, tie cross-section 208b perpendicular to the depth direction of the through-holes 208 is dispofed within the plane of the other surface (base) 206a of the electrode pads 206.
Conseguently, the entire end face of the through-electrodes formed by ~xlling the through-holes 2b8 with an electroconductive material can be joined completely with the other surface (bash) 206a of the electrode pads 206. Accordingly, the wiring resistance at the connection between the electrode pads 206 and the through~lectrodes can be lowered (reduced), enabling a highly reliable electrical connection. Furthermore, because the entire end face of the through-electrodes can be joined completely to the electrode pads 206, there is no deterio~c~ation in characteristics due to heat history, which enables the manufacture i~f a semicvnduetor package with high reliability.
Next, in order to insulate both the through-electrodes provided inside the tHrough-holes 208 and the external wires extending from the through-electrodes az~d provided on the other surf~aee 201 c of the semiconductor substrate 201 from the setx~.iconductorl element 202, an electrical insulation film 209 is formed on the other surface 201 c of the semiconductor substrate 201 and inside the through-holes 208.
2S In the sanne manner as the thin film 207 used as the etchizxg mask, the electrical insulation film 209 is preferably deposited under conditions which do not cause any deterioration in the functionality of the circuit element 203. Parkicularly, if the cirduit element 203 is a solid-state image sensor, then preferably the thin film 207 is depo$ited under conditions which do not cause any deterioration in the functionality of a thit~ $lin made of organic materials such as a color filter or a microlens placed on the light r~eeiving sensor included in the circuit element 203. The thermal resistance of the organic materials mentioned above is typically around 250°C.
In the same manner as the thin film 207, as the electrical insulation film 2019, films which can be deposited at approximately 200°C such as low temperature~PCVD o~tide films and low temperature PCVD nitride films, or films applied by spin eoatip,g such as spin on glass (SOG) films and fluororesin films, are preferable.
The electrical insulation film formed on the other surface (base) 206a of the electxode pads 206 is then selectively removed. 'Here, a semiconductor lithographin process or etching process is used with a standard resist. If the through-holes 208 ire deep, that is if the semiconductor substrate 201 is thick, then the resist is applied using a~pray application method, and then exposed using a priojectaon exposure device or the tilde with a long focal depth.
As shown in FIG. 5B and FIG. 6D, through-electrodes 210 made of a ntetaXlic thin film are formed inside the through-holes 208 with the other surface (base) 206a oflthe electrode pads 206 at theix base end. Furthermore, external wires 211, which extend from the through-electrodes 210, are formed on the ot$~er surface 201c of the semicond~ietor substrate 201. fixternal wiring regions 212, connected to one end of the external wires 211, are formed in an opposing relationship to the extertxal terminals of another substrdte (not shown).
The through-electrodes 210, the external' wires 211 and the external wiringoregions 212 are all formed at the same time, by fwst forming a metallic thin film using a stAndard sputtering method or evaporation method or the like, and then patterning the metallic thin film into the desired shape using a semiconductor photolithographic process and etching process_ In the same mariner as the removal of the electrical insulation film descri>~ed 5 above, if the through-holes 208 are deep, then the resist is applied using a spray application method, and then exposed using a projection exposure device or the like with a long focal depth.
From the viewpoint of improving reliability, preferably plating surface trealtment with nickel or gold or the like is performed on the surfaces of the patterned throug~-10 electrodes 210, external wires 211 and external wiring regions 212, as needed.
Normally, aluminum is used to make the through-electrodes 210, the external wires 211 and the external wiring regions 212, but a rrietallic material such as copper, nid~kel and gold may be used, provided that the material is either the same as that used to malor the eleah~ode pads 206, or is chemically compatible.
15 Next, in order to gh~ield the through-electrodes 210, the external wires 21 I !md the external wiring regions 212 from the outside air '(moisture), a protective film 213 fade of a silicon nitride film or silicon oxide film or the like is formed thereon.
The protective film 213 is made of a material having electrical insulating properties, su~cient thermal resistance, and sufficient corrosion resistance_ The protective film 213 is prefernb~y a 20 silicon nitride film or silicon oxide film ox the like, formed using a plasma CVl~ method.
For example, after the thin film which constitutes the probectlve film 213 is formed using a plasma CVD method or the like, the portion of the thin ~rlm which is formed on tt~
external wiring regions 212 is selectively removed using a semiconductor photolithographic process arid etching process, thereby exposing part of the external wiring 25 regions 212.

The matezial of which the protective flltn 213 is made may be polymeric resin material such as a polyimide resin, a epoxy resin, a benzoeyclobutene (BCB) resins or a resin for forming a solder mask, or the like. For example, the protective filzzt~ 213 rhay be made of a resin for forming a solder mask and may be combined with a solder ma$~ for S providing a connection with the external terminals of another substrate (not shown.
As shown in FIG. 5C and FIG_ 6E, metal posts 214 are formed on th,e exposed parts of the external wiring regions 2i2 so as to protrude from the surface of the protective film 213.
An electrolytic plating method or a stud bump method or the like is used td form the metal posts 214.
Copper, gold and solder and the like are preferred as the material used to miake the metal posts, but other materials may be used provided that these materials enable connection to the external terminals of another substrate (not shown).
When manufacturing seztxiconductor packages using a semiconductor substrate in wafer form, the final step is to perform dicing of the semiconductor packages alot~ the dicing line (the alternate dotted and dashed line in FIG_ 6E). As a result semiconductor packages in chip form as shown in FIG. SC are obtained.
To perform the dicing process, a standard dicing machine yr etching machine or tlae like is used.
In the present invention, the semiconductor element may also be a light emitting element, a standard IC chip, or a micromachine element, as well as the solid-state image sensor used as an example in the first aspect_ According to this first aspect, conventional wire bonding becomes unnecessary, there are no zestrictions on the placement of the electrode pads provided on the orie surface of the semiconductor substrate, and electrical connection is possible between the electrode pads arid the external terminals of another substrate. Consequently, miniaturization of the semiconductor package can be realized_ Furthermore, by covering all parts of the other surface of the semiconductor substrate except for the metal posts with a protective film, a wiring configuration i~
obtained in which the metal parts on the other surface of the semiconductor substrdte are not exposed. Consequently, a semiconductor package with high reliability (high rrlolsture resistance) can be realized.
The through-electrodes and the external wires can all be processed using st~dard semiconductor manufacturing devices, Consequently, an inexpensive and small semiconductor package can be realized.
Photolithographie techniques used in normal semicoztduetor manufacturing processes can be applied to the through-electrodes and the external wires.
Because the processing accuracy of the through-eleebmdes and the exterzxal wires is determined by the semiconductor photolithographic process, microfabrication is possible.
Consequently the semiconductor package of the present invention is readily compatible with other circuit substrates in which the external terminals are formed with a fine pitch using photolithographic techniques, and interconnection of the terminals is possible. A.st a result it is possible to provide a semiconductor package including a plurality of semicon~luotor elements in a stacked arrangement, namely a semiconductor package having threew dimensional layered wiring.
Fttxtheimore, because in tlae semiconductor package according to the first ~.spect, notched regions in the form o~ V-shaped grooves or the like are not required, none of the semiconductor substrate is wasted, and the yield (area utilization) of the circuit element can be increased.

(Second Aspect) Next, a semiconductor package according to a second aspect of the prtsent invention is described with reference to FTG. 7A, FIG. 7B, FIG. 8 and FIG. 9.
FIG. 7A is an outline cross-sectional view showing an example of a semiecpductor package according to the second aspect of the present invention. FIG. 7B is another example of a semiconductor package according to the second aspect, seen from the part corresponding to the base in FIG. 7A. The semiconductor packages shown in FIGS
7A and FIG. 7B have been diced. Furthermore, the semiconductor package shown in FiG~
7B has the same construckion as the semiconductor package shown in FIG. 7A, with the exception that a protective film 413 is not provided.
FIG. 8 is a cross-sectional view showing an example of semiconductor packages in wafer form, prior to being diced into individual chips.
In FIG. 7A, FIG. 7B and FIG. 8, reference numeral 300 indicates a semiconductor package, 301 indicates a semiconductor substrate, 302 indicates a semiconductor dlement, 303 indicates a circuit element, 304 indicates a support substrate, 305 indicates an~adhesive layer, 306 indicates an electrode pad, 307 indicates an electrical insulation film, 308 indicates a through~lectrode, 309 indicates an external wire, 310 indicates an external wiring region, 3l 1 indicates a metal post, 313 indicates a protective film, 401 indi!t;ates a semiconductor substrate, 402 indicates a semiconductor element, 406 indicates an;
electrode pad, 407 indicates an electrical insulation film, 408 indicates a through-electrode, 409 indicates an external wire, 410 indicates an external wiring region, 411 indicates a metal post, 412 indicates a through-hole, 413 indicates a protective film, an:d 500 indicates a semiconductor package which has several semiconductor substrates in a layered!
configuration.
In the description below, for the circuit element 303, the example of a solili state image sensor is used. Furthermore, the description omits a detailed description of tie construction and the like of the semiconductor element itself, describing only those parts which relate to the present invention.
As shown in FIC3. 7A, in this semiconductor package 500, the semiconduet~r package 300 obtained according to the first aspect and a separate semiconductor substrate 401 having a circuit element (not showtx) are provided in a layered configuration. 'the metal posts 311 provided so as to protrude from an other surface 300b (the under surface) of the semiconductor package 300 are connected electrically to the electrode pads X06 provided on one surface 401 a (the upper surface) of the semiconductor substrate 4p 1 _ In the semiconductor substrate 401, through-holes 412 are formed in the sections where the electrode pads 406 are provnded, from the other surface 401 b through to~the one surface 401 a. Through-electrodes 408 are provided inside the through-holes 412 with the electrode pads 406 at their base end. External wires which extend from the throug~-electrodes 408 are provided on the other surface 401 b of the semiconductor substrate 401.
External wiring regions 410 are provided on the other surface 441b, and these external wiring regions 410 are electrically connected to orate end of the external vv~res 409.
Furthermore, metal posts 411, acting as a connection section, are provided on the external wiring regions 410 so as to protrude frozen the surface of the protective film 413 w$ich covers the other surface 401b of the semiconductor substrate 401. Providing these metal posts 411 allows the semiconductor substrate 401 to be easily connected to the external ternrtina;s of another substrate.
Preferred materials used to uxake the through-electrodes 408, the external wires 409 and the external wiring regions 410 are such materials as aluminum and copper, bht any material catx be used to make the electrical wiring provided that it is a metal whic)~ does not adversely affect the semiconductor package 300 and the semiconductor subshiate 401.

The metal posts 411 are preferably made of materials which are suited to establishing a connection with external terminals, typically copper, gold or solder dr the like.
If a mierolens (not shown) is provided on the light receiving sensor iz~cludekl in the circuit eleuaent 303, then as shown in FIG. 9, an adhesive layer pattern 305a whicH has an opening in the region over the circuit element 303 may be provided. The semicon~uetor element 302 and the support substrate 304 are bonded together by the adhesive Iayør pattern 305a, providing a gap 314 over the circuit element 303. As a result, light from external sources can enter the microlens without passing through the adhesive layer pattern 10 305a, allowing sufficient optical performance by the microlens (not shown)_ The construction of the semiconductor package shown here as an example is two semiconductor substrates in a layered configuration, but the semiconductor package of the present invention is not limited to this construction, and a construction with three br more semiconductor substrates iu layered configuration zztay also be used.
15 Next, a method of manufacturing the semiconductor package according to the second aspect ofthe invention is described with reference to FIG. l0A through FIG. lOC
and FIG_ 11A through FIG. 11D.
FIG, l0A through FIG. l OC are cx9oss-sectional views showing an exampld of a manufachwing process for semiconductor packages using a diced semiconductor slubstrate.
20 FIG. 11A through FIG. 11D are cross-sectional views showing an example of a manufacturing process for semiconductor packages using a semiconductor substraite inn wafer form.
Here, the description will center on FIG, l0A through FIG. 1 OC.
First, as shown in FIG. 10A and FIG. 1 lA, a semiconductor package 600 dbtained 25 according to the mazxufacturing method of the aforementioned first embodiment, end a semiconductor substrate 701 having a circuit element (not shown), a signal processing circuit (not shown) and electrode pads 706 provided on one surface 701a thereof ale prepared.
As shown in FIG. 1 OB and FIG. 11 B, the semiconductor package 600 and the semiconductor substrate 701 are bonded together by a method such as thermocomliression bonding, so that an electrical connection is established between, the metal posts 611 extending from an other surface 600b of the semiconductor package 600, and the electrode pads 706 provided on one surface 701 a of the semiconductoz substrate 701, The method used to bond the semiconductor package 600 to the semieondu~ctoz substrate 701 is not limited to thertxlocompression bonding, and any bonding nlethbd can be applied, such as metal eutectic bonding and anode bonding, provided that the binding method does not impair the function of the semiconductor element.
The semiconductor substrate 701 is then polished and thinned down from ~n other surface 701b side of the semiconductor substrate 701 (see FIG lOB, FIG 11C).
In this polishing process, a polishing method which uses a standard chemicsal mechanical polisher (CMP) or back grinder (BG) is preferred, and yet more preferhble is a polishing process which uses both these devices.
In the same tnana~er as the first embodiraent, the upper limit ita terms of hour far the semiconductor substrate 701 can be polished is determined by the maximum depth at which the circuit element (not shown) operates (for example the thickness of the v~ell layer or the buried layer ox the like), and the amount of polishing can be determined arbitrarily within this li.~nait. The amount of polishing of the semiconductor substrate 701 cad be determined appropriately within the range of the upper limit mentioned above based on the subsequent etching process of the semiconductor substrate 701 and the arrangemeht of the electrode pads 706.

In addition, the polishing process is not limited to methods using a BG or ~, and any method may be used provided that the method can thin down the other surface 701b of the semiconductor substrate 701 evenly and does xiot impede the subsequent etching mask formation process_ Examples of polishing methods which may be used include wet etching methods using tetramethylammonium hydroxide (TMA,Ii) solution or potassiutxa hydroxide (1{OIT) solution or the like, or dry etching methods such as reactive ion etching (RIE) and chemical dry etching (CbE).
As shown in FIG. 10C, the same steps as in the first embodiment are then performed on the thinned-down other surface 70Ic ofthe semiconductor substrate X101, to provide through-electrodes 708, external wires 709, external wiring regions 710, rbetal posts 711 and a protective film 713.
Here, in the steps of forming the through-holes 712, the through-electrodes 708, the external wires 709, the external wiritxg regions 710 and the metal posts 711, processing of the semiconductor package 600 to enable the package to fulfill its role as the support substrate for the semiconductor substrate 701 can be performed easily.
Furthermore, the external wiring regions 710 and the metal posts 711 are preferably disposed in posltiozis which allow an electrical connection to be established with the external ternninals of another substrate (not shown).
When manufacturing semiconductor packages using a semiconductor substrate in wafer forth, the final step is to perform dicing of the semiconductor packages alonjg the dicing line (the alternate dotted and dashed line in F1G. I 1D). As a result, a semiQOnductor package in chip fort7~, as shown in FIG. l OC is obtained.
To perform the dicing process, a standard dicing machine or etching t~aachPme or the like is used.
In the present invention, the semiconductor element may also be a light er#titting element, a standard IC chip, or a micromachine element, as well as the solid-state image sensor used as an example in the second aspect.
Furthermore, as shown in FIG. 12, a dummy electrode pad 715 may be prodded on the semiconductor substrate 701, and an electrical connection may be established via this dummy electrode pad 715 between the metal posts 611 of the semiconductor package 600 arid the through-electrodes 708 of the semiconductor substrate 701. In this case, thle external wires 609 and external wiring regions 610 of the semiconductor package 800 can be drawn out directly to the outside of the semiconductor package, via the externallwires 709, the external wiring regions 710 and the through-electrodes 708. In other words, it is also possible for the through-electrodes 708 of the semiconductor substrate 701 to (function as an interposer. Such a configuration is effective for use as a power supply line or the like for driving the semiconductor package 600 in FIG. l OC, for example.
In addition, in this second aspect, as shown in. FIG. 11A thmugh FIG. 11D~
when layering a plurality of semiconductor substrates which are izt wafer foam, it is necessary ~or the other semiconductor substrates to have the same electrode placement as the latest semiconductor substrate.
According to the second aspect, wire bondxrrg as performed with conventional packages is not required, and it is possible to establish an electrical connection between the electrode pads on the one surface of the semiconductor substrate and the external ~iermi.nals of a separate substrate via external wiring, without being limited to the arrRngemeizt of the electrode pads on the one surface of the semiconductor substrate, for example.
Furthermore, by covering all parts of the other surface of the semiconductbr substrate except for the metal posts with a protective film, a wiring configuration is obtained in which the metal parts on the other surface of the semiconductor subst>fate are not exposed. Consequently, a setnicoz~ductor package with high reliability (high »ioisture resistance) can be realized.
'The through-electrodes and the external wires can all be processed using standard semiconductor manufacturing devices. Consequently, an inexpensive and small semiconductor package can be realized.
Photolithographic techniques used in normal semiconductor manufacturingf processes can be applied to the through-electrodes and the external wires.
Because the processing accuracy of the through-electrodes and the external wires is determined! by the semiconductor photolithogmphic process, microfabrication is possible.
Consequedtly the semiconductor package of the present ixwention is readily compatible with other citcuit substrates in which the external terminals are formed with a fine pitch using photolithographic techniques, and interconnection of the terminals is possible. As to result it is possible to provide a semiconductor package including a plurality of semiconductor elements in a stacked arrangement, namely a semiconductor package having three dimensional layered wiring.
Furthermore, because in the semiconductor package according to the second aspect, notched regions in the form of V-shaped grooves or the like are not required, nonei of the semiconductor substrate is wasted, and the yield (area utilization) of the circuit elehzent can be increased.
While preferred embodiments of the invention, have been described and illustrated above, it should be understood that these are exemplary of the invention and are nbt to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention.
Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims, INDUSTRIAL APPLICABILITY
The semiconductor package and manufacturing method thereof according t~ the present invention can be applied to wafer level CSP semiconductor packages as well as non-wafer-level-CSP semiconductor packages, and therefore a low cost semiconductor 5 package with high precision and high reliability can be realized.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not 'to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention.
Aecordi~gly, the 10 invention is not to be considered as being limited by the foregoing description, and is only limited by the scope o~ the appended claims.

Claims (20)

1. A semiconductor package comprising:
a semiconductor element provided with a circuit element on one surface of in semiconductor substrate;
an external wiring region provided on an other surface of said semiconductor substrate;
a support substrate disposed on the one surface of said semiconductor substrate;
an electrode pad disposed on the one surface of said semiconductor substrate;
and a through-electrode which extends from said electrode pad through to the other surface of said semiconductor substrate.
2. A semiconductor package according to claim 1, wherein a connection section for providing a connection to an external terminal is provided on said external wiring region.
3. A semiconductor package according to claim 1, wherein an adhesive layer is provided on the one surface of said semiconductor substrate, and this adhesive layer adheres and secures the one surface of said semiconductor substrate to the support substrate.
4. A semiconductor package according to claim 1, wherein said electrode pad are disposed on the one surface of said semiconductor substrate in that region where said circuit element is not present.
5. A semiconductor package according to claim 1, wherein an external wire which extends from said through-electrode and connects to said external wiring region is provided.
6. A semiconductor package according to claim 2, wherein the entire other surface side of said semiconductor substrate, excluding said connection section, is covered by a protective film.
7. A semiconductor package according to claim 1, wherein said support substrate is made of a material which is optically transparent.
8. A semiconductor package according to claim 3, wherein said adhesive layer is provided at least on the one surface of said semiconductor substrate, in a region where said electrode pad is provided.
9. A semiconductor package according to claim 1, wherein said external wiring region is arranged in an opposing relationship to an external terminal.
10. A semiconductor package according to claim 1, wherein two or more semiconductor substrates are provided in a layered configuration.
11. A semiconductor package according to claim 10, wherein an external wire for connecting to a terminal of another semiconductor element extends from said through-electrode.
12. A semiconductor package according to claim 1, wherein those parts of said through-electrode which are bonded to said electrode pad are provided within a plane of said electrode pad.
13. A semiconductor package manufacturing method of manufacturing a semiconductor package comprising a semiconductor element with a circuit element provided on one surface of a semiconductor substrate and an external wiring region provided on an other surface of said semiconductor substrate, comprising:
a step A of adhering and securing a support substrate to the one surface of said semiconductor substrate;
a step B of thinning the other surface of said semiconductor substrate;
a step C of forming a through-hole which reaches through to an electrode pad disposed on the one surface of said semiconductor substrate, from the other surface of said semiconductor substrate; and a step D of forming a through-electrode in said through-hole.
14. A semiconductor package manufacturing method according to claim 13, wherein in said step C, forming said through-hole so that at least in that part where said through-hole contacts said electrode pad, a cross section of said through-hole is disposed inside said electrode pad.
15. A semiconductor package manufacturing method according to Claim 13, wherein in step C, halting the formation of said through-hole at the point in time when said electrode pad is exposed inside said through-hole.
16. A semiconductor package manufacturing method according to claim 13, wherein in said step D, forming an external wire for connecting said external wiring region to said through-electrode at the same time as forming the through-electrode inside said through-hole.
17. A semiconductor package manufacturing method according to claim 13, wherein in said step D, providing a connection section for connecting to an external terminal on said external wiring region.
18. A semiconductor package manufacturing method according to claim 13, wherein in the step A, preparing a semiconductor element which comprises a semiconductor substrate in wafer form, and further comprising a step E, after said step D, of dicing said semiconductor substrate in wafer form.
19, A semiconductor package manufacturing method according to claim 13, wherein using a semiconductor substrate in which said electrode pad is arranged on the one surface of said semiconductor substrate, in a region where said circuit element is not provided.
20. A semiconductor package manufacturing method according to claim 13, further comprising a step, after said step D, of covering the entire other surface side of said semiconductor substrate, except for said connection section, with a protective film.
CA 2536799 2003-08-28 2004-08-25 Semiconductor package and method of manufacturing the same Active CA2536799C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2003304848 2003-08-28
JP2003-304848 2003-08-28
JP2003419613 2003-12-17
JP2003-419613 2003-12-17
PCT/JP2004/012588 WO2005022631A1 (en) 2003-08-28 2004-08-25 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CA2536799A1 true CA2536799A1 (en) 2005-03-10
CA2536799C CA2536799C (en) 2013-11-12

Family

ID=34277643

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2536799 Active CA2536799C (en) 2003-08-28 2004-08-25 Semiconductor package and method of manufacturing the same

Country Status (7)

Country Link
US (1) US7180149B2 (en)
EP (1) EP1662564B1 (en)
JP (2) JP4722702B2 (en)
KR (1) KR101180815B1 (en)
AU (1) AU2004268299B2 (en)
CA (1) CA2536799C (en)
WO (1) WO2005022631A1 (en)

Families Citing this family (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4000507B2 (en) * 2001-10-04 2007-10-31 ソニー株式会社 Method for manufacturing solid-state imaging device
US7056810B2 (en) * 2002-12-18 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
JP2008532307A (en) * 2005-03-02 2008-08-14 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Semiconductor package and method for manufacturing a production package
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
JP2007012995A (en) * 2005-07-01 2007-01-18 Toshiba Corp Microminiature camera module and method of manufacturing same
KR101134168B1 (en) * 2005-08-24 2012-04-09 삼성전자주식회사 Semiconductor chip and manufacturing method thereof, display panel using the same and manufacturing method thereof
SG130061A1 (en) * 2005-08-24 2007-03-20 Micron Technology Inc Microelectronic devices and microelectronic support devices, and associated assemblies and methods
JP4745007B2 (en) * 2005-09-29 2011-08-10 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP2009512213A (en) * 2005-10-11 2009-03-19 ボク，タエソック Simoth image sensor wafer level package using silicon via contact and method of manufacturing the same
US7393758B2 (en) * 2005-11-03 2008-07-01 Maxim Integrated Products, Inc. Wafer level packaging process
US7307348B2 (en) * 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
KR100691398B1 (en) * 2006-03-14 2007-03-12 삼성전자주식회사 Micro element package and manufacturing method thereof
KR100748722B1 (en) * 2006-04-03 2007-08-13 삼성전자주식회사 Micro element package module and manufacturing method thereof
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
JP5114017B2 (en) * 2006-05-11 2013-01-09 オリンパス株式会社 Semiconductor device and method for manufacturing the same
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
KR100832845B1 (en) * 2006-10-03 2008-05-28 삼성전자주식회사 Semiconductor Package Structure And Method Of Fabricating The Same
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8569876B2 (en) * 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
JP4403424B2 (en) * 2006-11-30 2010-01-27 ソニー株式会社 Solid-state imaging device
US7531443B2 (en) * 2006-12-08 2009-05-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through interconnects and back side redistribution conductors
KR100833194B1 (en) * 2006-12-19 2008-05-28 삼성전자주식회사 Semiconductor package with redistribution layer of semiconductor chip direcltly contacted with substrate and method for fabricating the same
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US7618857B2 (en) * 2007-01-17 2009-11-17 International Business Machines Corporation Method of reducing detrimental STI-induced stress in MOSFET channels
US8013350B2 (en) 2007-02-05 2011-09-06 Panasonic Corporation Optical device and method for manufacturing optical device, and camera module and endoscope module equipped with optical device
JP5584474B2 (en) * 2007-03-05 2014-09-03 インヴェンサス・コーポレイション Chip with rear contact connected to front contact by through via
JP4380718B2 (en) 2007-03-15 2009-12-09 ソニー株式会社 Manufacturing method of semiconductor device
US7767544B2 (en) * 2007-04-12 2010-08-03 Micron Technology Inc. Semiconductor fabrication method and system
JP5301108B2 (en) * 2007-04-20 2013-09-25 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Semiconductor device
US8183151B2 (en) * 2007-05-04 2012-05-22 Micron Technology, Inc. Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom
US20080308922A1 (en) * 2007-06-14 2008-12-18 Yiwen Zhang Method for packaging semiconductors at a wafer level
KR100826989B1 (en) * 2007-06-20 2008-05-02 주식회사 하이닉스반도체 Semiconductor package and method for fabricating the same
JP2009016623A (en) * 2007-07-05 2009-01-22 Olympus Corp Semiconductor package
KR101458538B1 (en) 2007-07-27 2014-11-07 테세라, 인코포레이티드 A stacked microelectronic unit, and method of fabrication thereof
KR101538648B1 (en) 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
CN101861646B (en) 2007-08-03 2015-03-18 泰塞拉公司 Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
CN101123231B (en) * 2007-08-31 2010-11-03 晶方半导体科技（苏州）有限公司 Encapsulation structure for wafer chip dimension of micro mechanical-electrical system and its making method
JP4693827B2 (en) * 2007-09-20 2011-06-01 株式会社東芝 Semiconductor device and manufacturing method thereof
US7547630B2 (en) * 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
JP4468427B2 (en) 2007-09-27 2010-05-26 株式会社東芝 Manufacturing method of semiconductor device
JP5172267B2 (en) * 2007-10-09 2013-03-27 富士フイルム株式会社 Imaging device
FR2922682A1 (en) 2007-10-23 2009-04-24 St Microelectronics Rousset Micromodule i.e. image capturing micromodule, fabricating method for e.g. mobile telephone, involves forming connection between lateral conductive layer and conductive layer of housing by depositing conductive material in cavity
JP5197219B2 (en) * 2007-11-22 2013-05-15 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP2009147218A (en) 2007-12-17 2009-07-02 Toshiba Corp Semiconductor device, and method for manufacturing the same
JP4799543B2 (en) * 2007-12-27 2011-10-26 株式会社東芝 Semiconductor package and camera module
KR101446330B1 (en) * 2008-01-29 2014-10-02 삼성전자주식회사 Image sensor having through via
CN101499480B (en) * 2008-01-30 2013-03-20 松下电器产业株式会社 Semiconductor chip and semiconductor device
JP5271561B2 (en) * 2008-02-15 2013-08-21 本田技研工業株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5271562B2 (en) * 2008-02-15 2013-08-21 本田技研工業株式会社 Semiconductor device and manufacturing method of semiconductor device
JP4713602B2 (en) * 2008-02-21 2011-06-29 パナソニック株式会社 Substrate module, method for manufacturing the same, and electronic device
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
DE202008005708U1 (en) * 2008-04-24 2008-07-10 Vishay Semiconductor Gmbh Surface-mountable electronic component
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
JP5242282B2 (en) 2008-07-31 2013-07-24 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2010040862A (en) * 2008-08-06 2010-02-18 Fujikura Ltd Semiconductor device
JP4818332B2 (en) * 2008-08-12 2011-11-16 株式会社東芝 Semiconductor device, method for manufacturing semiconductor device, and camera module
US10515872B1 (en) 2008-09-22 2019-12-24 Hrl Laboratories, Llc Metallic sub-collector for HBT and BJT transistors
US8860092B1 (en) * 2008-09-22 2014-10-14 Hrl Laboratories, Llc Metallic sub-collector for HBT and BJT transistors
JP5408995B2 (en) * 2008-12-24 2014-02-05 株式会社フジクラ Semiconductor package
JP2010177569A (en) * 2009-01-30 2010-08-12 Panasonic Corp Optical device and method of manufacturing the same
JP2010177568A (en) * 2009-01-30 2010-08-12 Panasonic Corp Semiconductor device and electronic apparatus using the same, and method of manufacturing semiconductor device
EP2406821A2 (en) 2009-03-13 2012-01-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
JP2010245121A (en) * 2009-04-01 2010-10-28 Toshiba Corp Semiconductor device
IN2012DN00452A (en) 2009-07-30 2015-05-15 Megica Corp
TWI497658B (en) * 2009-10-07 2015-08-21 Xintec Inc Chip package and fabrication method thereof
JP2011146486A (en) * 2010-01-13 2011-07-28 Panasonic Corp Optical device, method for manufacturing the same, and electronic apparatus
JP2012003225A (en) * 2010-01-27 2012-01-05 Fujifilm Corp Polymerizable composition for solder resist and method for forming solder resist pattern
JP2011187754A (en) * 2010-03-10 2011-09-22 Toshiba Corp Solid-state imaging device and method of manufacturing the same
JP5757749B2 (en) 2010-05-19 2015-07-29 富士フイルム株式会社 Polymerizable composition
US8536671B2 (en) * 2010-06-07 2013-09-17 Tsang-Yu Liu Chip package
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
JP5544239B2 (en) 2010-07-29 2014-07-09 富士フイルム株式会社 Polymerizable composition
US8692358B2 (en) * 2010-08-26 2014-04-08 Yu-Lung Huang Image sensor chip package and method for forming the same
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP5674399B2 (en) 2010-09-22 2015-02-25 富士フイルム株式会社 Polymerizable composition, photosensitive layer, permanent pattern, wafer level lens, solid-state imaging device, and pattern forming method
KR101059490B1 (en) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 Conductive pads defined by embedded traces
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
FR2969381A1 (en) * 2010-12-21 2012-06-22 St Microelectronics Crolles 2 Electronic chip, has set of connection pillars electrically connected with vias, where pillars form protuberant regions relative to substrate and are provided with portion embedded in housing formed in thickness of substrate
JP5417364B2 (en) 2011-03-08 2014-02-12 富士フイルム株式会社 Curable composition for solid-state imaging device, photosensitive layer, permanent pattern, wafer level lens, solid-state imaging device, and pattern forming method using the same
US8461691B2 (en) * 2011-04-29 2013-06-11 Infineon Technologies Ag Chip-packaging module for a chip and a method for forming a chip-packaging module
CN102779800B (en) * 2011-05-09 2015-10-07 精材科技股份有限公司 Wafer encapsulation body and forming method thereof
JP6002372B2 (en) * 2011-08-05 2016-10-05 株式会社フジクラ Bonding substrate with through wiring
JP5836019B2 (en) * 2011-09-01 2015-12-24 株式会社フジクラ Component built-in substrate and manufacturing method thereof
JP2013143520A (en) * 2012-01-12 2013-07-22 Sony Corp Image pickup unit and method of manufacturing image pickup unit
US8916980B2 (en) * 2012-02-16 2014-12-23 Omnivision Technologies, Inc. Pad and circuit layout for semiconductor devices
US10269863B2 (en) * 2012-04-18 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for via last through-vias
JPWO2013179764A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Imaging device manufacturing method and semiconductor device manufacturing method
CN104364898A (en) 2012-05-30 2015-02-18 奥林巴斯株式会社 Method of manufacturing image pickup device and method of manufacturing semiconductor device
EP2858105A4 (en) 2012-05-30 2016-05-18 Olympus Corp Imaging device, semiconductor device, and imaging unit
JP6395600B2 (en) 2012-05-30 2018-09-26 オリンパス株式会社 Imaging device manufacturing method and semiconductor device manufacturing method
KR101401988B1 (en) 2012-09-07 2014-05-30 주식회사 동부하이텍 Semiconductor package and semiconductor package forming scheme
JP6007694B2 (en) * 2012-09-14 2016-10-12 ソニー株式会社 Solid-state imaging device and electronic apparatus
JP2014086465A (en) * 2012-10-19 2014-05-12 Toshiba Corp Solid-state imaging device
CN104284060B (en) * 2013-07-12 2019-07-02 鸿富锦精密工业（深圳）有限公司 Camera mould group
JP2015056557A (en) * 2013-09-12 2015-03-23 株式会社東芝 Semiconductor device
DE102014101366B3 (en) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip mounting on over-chip adhesion or dielectric layer on substrate
CN107210306B (en) * 2015-01-23 2020-07-14 奥林巴斯株式会社 Imaging device and endoscope
TWI628723B (en) * 2015-03-10 2018-07-01 精材科技股份有限公司 A chip sacle sensing chip package and a manufacturing method thereof
WO2017036381A1 (en) * 2015-09-02 2017-03-09 苏州晶方半导体科技股份有限公司 Package structure and packaging method
TWI649856B (en) * 2016-05-13 2019-02-01 精材科技股份有限公司 Chip package and manufacturing method thereof
KR102486561B1 (en) 2017-12-06 2023-01-10 삼성전자주식회사 Methods of forming redistribution lines and methods of manufacturing semiconductor devices using the same
JP7462263B2 (en) 2020-03-24 2024-04-05 パナソニックＩｐマネジメント株式会社 Semiconductor element and solid-state imaging device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH085566Y2 (en) * 1989-07-12 1996-02-14 オリンパス光学工業株式会社 Solid-state imaging device
IL108359A (en) 1994-01-17 2001-04-30 Shellcase Ltd Method and apparatus for producing integrated circuit devices
JP3313547B2 (en) 1995-08-30 2002-08-12 沖電気工業株式会社 Manufacturing method of chip size package
JP3563604B2 (en) * 1998-07-29 2004-09-08 株式会社東芝 Multi-chip semiconductor device and memory card
US6780661B1 (en) 2000-04-12 2004-08-24 Finisar Corporation Integration of top-emitting and top-illuminated optoelectronic devices with micro-optic and electronic integrated circuits
JP3879816B2 (en) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE
JP2001351997A (en) 2000-06-09 2001-12-21 Canon Inc Structure mounted with light-receiving sensor and method using the same
JP2002094082A (en) * 2000-07-11 2002-03-29 Seiko Epson Corp Optical element and its manufacturing method and electronic equipment
JP3839271B2 (en) 2001-05-01 2006-11-01 富士写真フイルム株式会社 Solid-state imaging device and manufacturing method thereof
EP1419102A2 (en) 2001-08-24 2004-05-19 Schott Ag Method for producing micro-electromechanical components
DE10141571B8 (en) 2001-08-24 2005-05-25 Schott Ag A method of assembling a semiconductor device and integrated circuit fabricated therewith that is suitable for three-dimensional, multi-layered circuits
WO2003041174A1 (en) * 2001-11-05 2003-05-15 Mitsumasa Koyanagi Solid-state image sensor and its production method
TWI229435B (en) * 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
JP2004095849A (en) * 2002-08-30 2004-03-25 Fujikura Ltd Method for manufacturing semiconductor substrate with through electrode, and method for manufacturing semiconductor device with through electrode

Also Published As

Publication number Publication date
EP1662564A1 (en) 2006-05-31
EP1662564B1 (en) 2018-05-30
WO2005022631A1 (en) 2005-03-10
AU2004268299B2 (en) 2009-05-21
US7180149B2 (en) 2007-02-20
KR20060115720A (en) 2006-11-09
US20050056903A1 (en) 2005-03-17
JP4722702B2 (en) 2011-07-13
JP2009194396A (en) 2009-08-27
AU2004268299A1 (en) 2005-03-10
JPWO2005022631A1 (en) 2006-10-26
CA2536799C (en) 2013-11-12
EP1662564A4 (en) 2011-08-03
KR101180815B1 (en) 2012-09-07

Similar Documents

Publication Publication Date Title
CA2536799A1 (en) Semiconductor package and method of manufacturing the same
US6930327B2 (en) Solid-state imaging device and method of manufacturing the same
KR100752713B1 (en) Wafer level chip scale package of image sensor and manufacturing method thereof
US8153458B2 (en) Image sensing devices and methods for fabricating the same
US7534656B2 (en) Image sensor device and method of manufacturing the same
US7981727B2 (en) Electronic device wafer level scale packages and fabrication methods thereof
KR100651115B1 (en) Semiconductor device and fabrication method thereof
US7408257B2 (en) Packaging chip and packaging method thereof
JP2004153130A (en) Semiconductor device and its manufacturing method
JP2004140037A (en) Semiconductor device and its manufacturing process
KR20080074773A (en) Image sensor package with die receiving opening and method of the same
KR101906467B1 (en) Compliant interconnects in wafers
JP2002231918A (en) Solid-state image pickup device and its manufacturing method
US20090050995A1 (en) Electronic device wafer level scale packges and fabrication methods thereof
US7768140B2 (en) Semiconductor device
JP2002231921A (en) Solid-state image pickup device and its manufacturing method
US20110147905A1 (en) Semiconductor device and method of manufacturing the same
US10276463B2 (en) Semiconductor device and method for manufacturing the same
US10651374B2 (en) Semiconductor device, and method for manufacturing the same
US20090111217A1 (en) Method of manufacturing chip-on-chip semiconductor device

Legal Events

Date Code Title Description
EEER Examination request