CA2439783C - Improvements in or relating to communication systems - Google Patents
Improvements in or relating to communication systems Download PDFInfo
- Publication number
- CA2439783C CA2439783C CA002439783A CA2439783A CA2439783C CA 2439783 C CA2439783 C CA 2439783C CA 002439783 A CA002439783 A CA 002439783A CA 2439783 A CA2439783 A CA 2439783A CA 2439783 C CA2439783 C CA 2439783C
- Authority
- CA
- Canada
- Prior art keywords
- bus
- node
- switch
- interface
- timeslot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0007—Construction
- H04Q2011/0024—Construction using space switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0007—Construction
- H04Q2011/0033—Construction using time division switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0037—Operation
- H04Q2011/0039—Electrical control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0037—Operation
- H04Q2011/005—Arbitration and scheduling
Abstract
A communication system for the mutual interconnection of a plurality of lower traffic level (5 Terabit) switch nodes via a relatively higher traffic level (Petabit) connection bus, which system comprises in operative association with each node, a two part TDM optical data management interface, wherein a first of the two parts comprises a time slot resequencer which serves to provide for the transmission of data from its associated node to the bus, and wherein a second of the two parts comprises a time slot specific combiner which serves for the transmission of data from the bus to its associated node, each node and the bus having independent data scheduling.
Description
IMPROVEMENTS IN OR RELATING TO COMMUNICATION SYSTEMS.
FIELD OF INVENTION
The present invention relates to communication systems. More particularly but not exclusively it relates to such systems which use optical TDM (time division multiplex) switch cores.
BACKGROUND OF THE INVENTION
TDM switch cores are well known to the cognoscenti and moreover, the operation of an optical backplane and/or apparatus for use therewith is described, for example, in Great Britain Patent Application Nos. GB 2353157A, and GB 2362280A.
Accordingly, neither detailed switchcore description nor detailed optical backplane description herein, is believed to be necessary.
The capacity of the apparatus described in GB2362280A is limited by the throughput of the optical backplane. Typically this is 5 Terabit/s. However in the future, higher capacity switch cores will be required and these can be achieved by the interconnection of a plurality of 5 Terabit/s switch nodes so that any one or more of the ingress ports of any one of such nodes can be selectively connected to the egress port or ports of any other of such nodes via a static Petabit/s optical connection bus. Therefore, it is desirable to provide an optical interconnection system to satisfy this particular requirement. It should however be understood, that the present invention may also find more general application in communication systems.
SUMMARY OF THE INVENTION
In a first aspect of the invention, there is provided a time division multiplexing (TDM) optical communication system for mutual interconnection of a plurality of switch nodes via a connection bus comprising in operative association with each node, a two part time division multiplexing TDM data management interface, wherein: a first of the two parts comprises a time slot resequencer which serves to provide for the transmission of data from its associated node to the bus, wherein the timeslot resequencer of each interface comprises an optical splitter fed from its associated switch node and coupled to the bus via a timeslot selector, a time delay device, and an optical combiner which feeds the bus, and wherein a second of the two parts comprises a time slot specific combiner which serves for the transmission of data from the bus to its associated node, wherein the timeslot-specific combiner of each interface comprises a time delay device, a timeslot selector and an optical combiner via which its associated switch node is fed from the bus, each node and the bus having independent data scheduling, the switch nodes being operational at a lower traffic transmission level than the connection bus, the data being transmitted optically between the switch nodes, the interface, and the bus.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of a specific embodiment of the invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the present invention will now be described, by way of example only, with reference to the attached figure.
Fig. 1 is a schematic representation of an embodiment of a switch node interconnection system of the present invention.
DETAILED DESCRIPTION
Referring now to the drawing, a communication system comprises a plurality of Terabit switch nodes, only two of which 1, and 2, are shown in the drawing for simplicity of description. Each of the nodes 1, 2, comprises a 128X128 single node switch fabric.
2a The node 1, includes ingress ports 3, coupled to an output line 4, and egress ports 5, each coupled to an input line 6, via a timeslot selector 7, and an optical grating 8, switch operation being locally controlled by means of a scheduler 9. The other node 2, is substantially identical comprising, ingress ports 10, coupled to an output line 11, and egress ports 12, each coupled to an input line 13, via a time slot selector 14, and an optical grating 15, switch operation being locally controlled by a scheduler 16.
In order to connect any one or more of the ingress ports 3, of the node 1, via an optical bus arrangement which may be implemented as a crossconnect 17, which has its own scheduling engine 18, to any egress port of any other node, (such as one of the egress port or ports 12, of the node 2, for example), a two level traffic management interface system is provided which comprises for each node a similar Petabit expansion box. In this particular embodiment boxes 19, and 20, for the nodes 1, and 2, respectively are provided.
FIELD OF INVENTION
The present invention relates to communication systems. More particularly but not exclusively it relates to such systems which use optical TDM (time division multiplex) switch cores.
BACKGROUND OF THE INVENTION
TDM switch cores are well known to the cognoscenti and moreover, the operation of an optical backplane and/or apparatus for use therewith is described, for example, in Great Britain Patent Application Nos. GB 2353157A, and GB 2362280A.
Accordingly, neither detailed switchcore description nor detailed optical backplane description herein, is believed to be necessary.
The capacity of the apparatus described in GB2362280A is limited by the throughput of the optical backplane. Typically this is 5 Terabit/s. However in the future, higher capacity switch cores will be required and these can be achieved by the interconnection of a plurality of 5 Terabit/s switch nodes so that any one or more of the ingress ports of any one of such nodes can be selectively connected to the egress port or ports of any other of such nodes via a static Petabit/s optical connection bus. Therefore, it is desirable to provide an optical interconnection system to satisfy this particular requirement. It should however be understood, that the present invention may also find more general application in communication systems.
SUMMARY OF THE INVENTION
In a first aspect of the invention, there is provided a time division multiplexing (TDM) optical communication system for mutual interconnection of a plurality of switch nodes via a connection bus comprising in operative association with each node, a two part time division multiplexing TDM data management interface, wherein: a first of the two parts comprises a time slot resequencer which serves to provide for the transmission of data from its associated node to the bus, wherein the timeslot resequencer of each interface comprises an optical splitter fed from its associated switch node and coupled to the bus via a timeslot selector, a time delay device, and an optical combiner which feeds the bus, and wherein a second of the two parts comprises a time slot specific combiner which serves for the transmission of data from the bus to its associated node, wherein the timeslot-specific combiner of each interface comprises a time delay device, a timeslot selector and an optical combiner via which its associated switch node is fed from the bus, each node and the bus having independent data scheduling, the switch nodes being operational at a lower traffic transmission level than the connection bus, the data being transmitted optically between the switch nodes, the interface, and the bus.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of a specific embodiment of the invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the present invention will now be described, by way of example only, with reference to the attached figure.
Fig. 1 is a schematic representation of an embodiment of a switch node interconnection system of the present invention.
DETAILED DESCRIPTION
Referring now to the drawing, a communication system comprises a plurality of Terabit switch nodes, only two of which 1, and 2, are shown in the drawing for simplicity of description. Each of the nodes 1, 2, comprises a 128X128 single node switch fabric.
2a The node 1, includes ingress ports 3, coupled to an output line 4, and egress ports 5, each coupled to an input line 6, via a timeslot selector 7, and an optical grating 8, switch operation being locally controlled by means of a scheduler 9. The other node 2, is substantially identical comprising, ingress ports 10, coupled to an output line 11, and egress ports 12, each coupled to an input line 13, via a time slot selector 14, and an optical grating 15, switch operation being locally controlled by a scheduler 16.
In order to connect any one or more of the ingress ports 3, of the node 1, via an optical bus arrangement which may be implemented as a crossconnect 17, which has its own scheduling engine 18, to any egress port of any other node, (such as one of the egress port or ports 12, of the node 2, for example), a two level traffic management interface system is provided which comprises for each node a similar Petabit expansion box. In this particular embodiment boxes 19, and 20, for the nodes 1, and 2, respectively are provided.
The expansion box 19, handles traffic to/from the node 1, and comprises a time slot resequencer 21, which operates on the 5 Terabit level to couple the ingress ports 3, to the crossconnect 17, and a time-slot specific combiner 22, which operates on the Petabit level to couple the crossconnect 17, to the egress ports 5.
Similarly, the expansion box 20, handles traffic to/from the node 2, and comprises a time slot resequencer 23, which operates on the 5 Terabit level to couple the ingress ports 10, to the crossconnect 17, and a time-slot specific combiner 24, which operates to on the Petabit level to couple the crossconnect 17, to the egress ports 12.
The time slot resequencer 21, operating on the 5 Terabit level, comprises an optical splitter 25, fed from the line 4, a time slot selector 26, a time delay 27, and an optical combiner 28, coupled to the crossconnect 17, whereas its associated timeslot-specific combiner 22, which operates on the Petabit level, comprises time delay 29, fed from the crossconnect 17, timeslot selector 30, and an optical combiner 31, which is coupled to the line 6, so as in effect to reverse the data expansion process.
Similarly, the time slot resequencer 23, which operates on the 5 Terabit level, comprises an optical splitter 32, fed from the line 11, a time slot selector 33, a time delay 34, and an optical combiner 35, coupled to the crossconnect 17, whereas its associated timeslot-specific combiner 24, which operates on the Petabit level, comprises time delay 36, fed from the crossconnect 17, a timeslot selector 37, and an optical combiner 38, which is coupled to the line 13.
It will be appreciated that although only two nodes are shown in this example, several nodes may be similarly interconnected to the crossconnect 17, each via its own Petabit expansion box.
In operation, the system as just before described utilises algorithms which run at two levels, i.e. the 5 Terabit level of the switch nodes and the Petabit level of the extension system comprising the expansion boxes 19, and 20, and the crossconnect 17, each node being responsible for managing the slot allocation or scheduling of its own backplane. It will pass to the extension system, information concerning traffic destined for other nodes with which it is linked via the extension system.
Once the extension system has opened a connection between two nodes, the local node will select which of its ingress ports will transmit to the egress port of the external node and pass that information to the traffic management system of the external node.
Similarly, the expansion box 20, handles traffic to/from the node 2, and comprises a time slot resequencer 23, which operates on the 5 Terabit level to couple the ingress ports 10, to the crossconnect 17, and a time-slot specific combiner 24, which operates to on the Petabit level to couple the crossconnect 17, to the egress ports 12.
The time slot resequencer 21, operating on the 5 Terabit level, comprises an optical splitter 25, fed from the line 4, a time slot selector 26, a time delay 27, and an optical combiner 28, coupled to the crossconnect 17, whereas its associated timeslot-specific combiner 22, which operates on the Petabit level, comprises time delay 29, fed from the crossconnect 17, timeslot selector 30, and an optical combiner 31, which is coupled to the line 6, so as in effect to reverse the data expansion process.
Similarly, the time slot resequencer 23, which operates on the 5 Terabit level, comprises an optical splitter 32, fed from the line 11, a time slot selector 33, a time delay 34, and an optical combiner 35, coupled to the crossconnect 17, whereas its associated timeslot-specific combiner 24, which operates on the Petabit level, comprises time delay 36, fed from the crossconnect 17, a timeslot selector 37, and an optical combiner 38, which is coupled to the line 13.
It will be appreciated that although only two nodes are shown in this example, several nodes may be similarly interconnected to the crossconnect 17, each via its own Petabit expansion box.
In operation, the system as just before described utilises algorithms which run at two levels, i.e. the 5 Terabit level of the switch nodes and the Petabit level of the extension system comprising the expansion boxes 19, and 20, and the crossconnect 17, each node being responsible for managing the slot allocation or scheduling of its own backplane. It will pass to the extension system, information concerning traffic destined for other nodes with which it is linked via the extension system.
Once the extension system has opened a connection between two nodes, the local node will select which of its ingress ports will transmit to the egress port of the external node and pass that information to the traffic management system of the external node.
In order to carry information on the ingress nodes backplane, it must be extracted from that backplane, moved in time and inserted into a new slot on an extension backplane. This will carry the traffic to the external node where it will again be extracted, moved in time and inserted into the appropriate slot of the egress nodes back plane. This is in effect an optical time and space switch which is defined in this system by the splitters, couplers and delay lines/devices as shown.
A system as just before described has the advantage that use of the timeslot resequencers facilitate independent delay for each of the 128 timeslots and moreover, all 128 could be outputted if so required. In operation, the timeslot-specific combiners provide a 128:1 optical switch with 50 Pic/sec switching speed. It will be appreciated that scheduling resolves internal/external time slot contention and that the implementation is inherently scalable in accordance with traffic requirements.
A system as just before described has the advantage that use of the timeslot resequencers facilitate independent delay for each of the 128 timeslots and moreover, all 128 could be outputted if so required. In operation, the timeslot-specific combiners provide a 128:1 optical switch with 50 Pic/sec switching speed. It will be appreciated that scheduling resolves internal/external time slot contention and that the implementation is inherently scalable in accordance with traffic requirements.
Claims (4)
1. A time division multiplexing (TDM) optical communication system for mutual interconnection of a plurality of switch nodes via a connection bus comprising in operative association with each node, a two part TDM data management interface, wherein:
a first of the two parts comprises a time slot resequencer which serves to provide for the transmission of data from its associated node to the bus, wherein the timeslot resequencer of each interface comprises an optical splitter fed from its associated switch node and coupled to the bus via a timeslot selector, a time delay device, and an optical combiner which feeds the bus, and wherein a second of the two parts comprises a time slot specific combiner which serves for the transmission of data from the bus to its associated node, wherein the timeslot-specific combiner of each interface comprises a time delay device, a timeslot selector and an optical combiner via which its associated switch node is fed from the bus, each node and the bus having independent data scheduling, the switch nodes being operational at a lower traffic transmission level than the connection bus, the data being transmitted optically between the switch nodes, the interface, and the bus.
a first of the two parts comprises a time slot resequencer which serves to provide for the transmission of data from its associated node to the bus, wherein the timeslot resequencer of each interface comprises an optical splitter fed from its associated switch node and coupled to the bus via a timeslot selector, a time delay device, and an optical combiner which feeds the bus, and wherein a second of the two parts comprises a time slot specific combiner which serves for the transmission of data from the bus to its associated node, wherein the timeslot-specific combiner of each interface comprises a time delay device, a timeslot selector and an optical combiner via which its associated switch node is fed from the bus, each node and the bus having independent data scheduling, the switch nodes being operational at a lower traffic transmission level than the connection bus, the data being transmitted optically between the switch nodes, the interface, and the bus.
2. A communication system as claimed in claim 1, wherein the switch nodes of the system each comprise ingress ports coupled to the timeslot resequencer of an associated interface, and egress ports coupled via grating means and a time slot selector to the time slot-specific combiner of this associated interface.
3. A communication system as claimed in claim 1 or 2, wherein the interface is arranged to provide for 5 Terabit coupling between the switch nodes and the bus, and for Petabit coupling between the bus and the switch nodes.
4. A communication system as claimed in any one of claims 1 to 3, wherein the switch nodes each comprise a 128X128 switch fabric.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0106902.0 | 2001-03-20 | ||
| GB0106902A GB0106902D0 (en) | 2001-03-20 | 2001-03-20 | Data interconnect extension system |
| GB0201107A GB2375458B (en) | 2001-03-20 | 2002-01-18 | Improvements in or relating to communication systems |
| GB0201107.0 | 2002-01-18 | ||
| PCT/GB2002/001295 WO2002076138A2 (en) | 2001-03-20 | 2002-03-18 | Improvements in or relating to communication systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2439783A1 CA2439783A1 (en) | 2002-09-26 |
| CA2439783C true CA2439783C (en) | 2007-12-04 |
Family
ID=26245860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002439783A Expired - Fee Related CA2439783C (en) | 2001-03-20 | 2002-03-18 | Improvements in or relating to communication systems |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7529483B2 (en) |
| EP (1) | EP1371259B1 (en) |
| JP (1) | JP4373093B2 (en) |
| AT (1) | ATE299334T1 (en) |
| AU (1) | AU2002241134B2 (en) |
| CA (1) | CA2439783C (en) |
| DE (1) | DE60204948T2 (en) |
| ES (1) | ES2243695T3 (en) |
| WO (1) | WO2002076138A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8270599B2 (en) * | 2008-02-28 | 2012-09-18 | Ciena Corporation | Transparent protocol independent data compression and encryption |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5303078A (en) * | 1990-12-18 | 1994-04-12 | Bell Communications Research, Inc. | Apparatus and method for large scale ATM switching |
| US5539559A (en) * | 1990-12-18 | 1996-07-23 | Bell Communications Research Inc. | Apparatus and method for photonic contention resolution in a large ATM switch |
| JPH06120973A (en) | 1992-10-06 | 1994-04-28 | Nippon Telegr & Teleph Corp <Ntt> | Atm cross-connection circuit |
| US5367520A (en) * | 1992-11-25 | 1994-11-22 | Bell Communcations Research, Inc. | Method and system for routing cells in an ATM switch |
| JP3261666B2 (en) | 1993-07-14 | 2002-03-04 | 日本電信電話株式会社 | Optical frequency multiplexing type FIFO buffer |
| EP0639037B1 (en) * | 1993-07-14 | 2002-10-02 | Nippon Telegraph And Telephone Corporation | Photonic frequency division multiplexed FIFO buffer |
| US5463624A (en) * | 1994-04-15 | 1995-10-31 | Dsc Communications Corporation | Bus arbitration method for telecommunications switching |
| SE516731C2 (en) * | 1994-06-10 | 2002-02-19 | Ericsson Telefon Ab L M | ATM-adapted three-stage selector unit |
| WO1998034379A1 (en) | 1997-02-03 | 1998-08-06 | Reltec Corporation | Distributed ethernet hub |
| GB9917880D0 (en) * | 1999-07-30 | 1999-09-29 | Roke Manor Research | Fast data modulator |
| JP3582442B2 (en) * | 2000-01-19 | 2004-10-27 | 日本電気株式会社 | Packet communication system and time slot allocation control method used therefor |
| GB2362280A (en) | 2000-05-12 | 2001-11-14 | Roke Manor Research | Optical pulse shaping apparatus |
| US6665495B1 (en) * | 2000-10-27 | 2003-12-16 | Yotta Networks, Inc. | Non-blocking, scalable optical router architecture and method for routing optical traffic |
-
2002
- 2002-03-18 US US10/471,941 patent/US7529483B2/en not_active Expired - Fee Related
- 2002-03-18 AU AU2002241134A patent/AU2002241134B2/en not_active Ceased
- 2002-03-18 DE DE60204948T patent/DE60204948T2/en not_active Expired - Lifetime
- 2002-03-18 EP EP02706972A patent/EP1371259B1/en not_active Expired - Lifetime
- 2002-03-18 JP JP2002573473A patent/JP4373093B2/en not_active Expired - Fee Related
- 2002-03-18 WO PCT/GB2002/001295 patent/WO2002076138A2/en active IP Right Grant
- 2002-03-18 AT AT02706972T patent/ATE299334T1/en not_active IP Right Cessation
- 2002-03-18 ES ES02706972T patent/ES2243695T3/en not_active Expired - Lifetime
- 2002-03-18 CA CA002439783A patent/CA2439783C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20040131087A1 (en) | 2004-07-08 |
| JP2004525570A (en) | 2004-08-19 |
| US7529483B2 (en) | 2009-05-05 |
| DE60204948T2 (en) | 2006-01-12 |
| EP1371259B1 (en) | 2005-07-06 |
| ES2243695T3 (en) | 2005-12-01 |
| ATE299334T1 (en) | 2005-07-15 |
| CA2439783A1 (en) | 2002-09-26 |
| EP1371259A2 (en) | 2003-12-17 |
| DE60204948D1 (en) | 2005-08-11 |
| AU2002241134B2 (en) | 2005-04-28 |
| WO2002076138A2 (en) | 2002-09-26 |
| WO2002076138A3 (en) | 2003-05-30 |
| JP4373093B2 (en) | 2009-11-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |