CA2406054A1 - Method of forming vias in silicon carbide and resulting devices and circuits - Google Patents

Method of forming vias in silicon carbide and resulting devices and circuits Download PDF

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Publication number
CA2406054A1
CA2406054A1 CA002406054A CA2406054A CA2406054A1 CA 2406054 A1 CA2406054 A1 CA 2406054A1 CA 002406054 A CA002406054 A CA 002406054A CA 2406054 A CA2406054 A CA 2406054A CA 2406054 A1 CA2406054 A1 CA 2406054A1
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Prior art keywords
substrate
silicon carbide
conductive
epilayer
contact
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CA002406054A
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French (fr)
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CA2406054C (en
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Zoltan Ring
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Wolfspeed Inc
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Claims (16)

1. A semiconductor device formed in silicon carbide and comprising:

a silicon carbide substrate (20) having respective first (2G) and second (27) surfaces;
a via (37) extending entirely through said silicon carbide substrate;
a conductive contact (25) over said via on said first surface of said silicon carbido substrate;
a device (22, 24) Formed in said substrate and for which said conductive contact comprises an. electrical contact;
a silicon carbide epilayer on said first surface of said substrate with at least portions of said semiconductor device being on said epilayer and said conductive contact to said device being on said epilayer;
a polymer coating (31) covering said epilayer epilayer including said device;
and a transparent layer (34) selected from flee group consisting of indiumtin-oxide cad magnesium oxido on said second surface of said polished transparent substrate.
2. A semiconductor device formed in silicon carbide and comprising:

a silicon carbide substrate (20) having respective first (26) and second (27) surfaces;
a conductive via (40, 41) extending entirely through said silicon carbide substrate;
a conductive contact (25) over said via on said first surface of said silicon carbide substrate;
a device (22, 24) formed in said substrate and for which said conductive contact comprises an electrical contact;
a silicon carbide epilayer on said first surface of said substratal with at least portions of said semiconductor device being on said epilayer and said conductive contact to said device being on said epilayer; and a polymer coating (31) covering said entire epilayer including said device.
3. A circuit precursor according to Claim, 1 or Claim 2 and further comprising a layer of photoresist on said layer of indium-tin-oxide.
4. A circuit precursor according to Claim 1 or Claim 2 wherein said via extends through said precursor from said photoresist to said conductive contact for said device.
5. A device ox precursor according to Claim 1 or Claim 2 wherein at least some portions of said silicon carbide substrate are semi-insulating.
6. A circuit precursor according to Claim 1 or Claim 2 wherein said conductive contact comprises indium-tin-oxide.
7. A device or precursor according to Claim 1 or Claim 2 and comprising two or more vias extending entirely through said silicon carbide substrate, with each via being covered on said first surface of said substrate with a conductive contact that forms an electrical contact to a device in said substrate.
8. A semiconductor device according to Claim 2 wherein said silicon carbide substrate is semi-insulating; and further comprising:

a microwave circuit formed on or in said first surface of said substrate, said circuit including a plurality of conductive contacts on said first surface;
and a plurality of said vias extending entirely through said substrate with each of said conductive vias terminating at one of said conductive contacts for forming a complete electrical pathway between said first and second surfaces of said silicon carbide substrate.
9. A monolithic microwave integrated circuit (MMIC) according to Claim 8.
10. An MMIC according to Claim 9 oral further comprising:

at least portions of said microwave circuit being formed in said at least and epilayer;
said conductive contacts being formed on said epilayer; and said vias extending to said contacts through said epilayer as well as through said substrate.
11. A method of fabricating a device on a silicon carbide substrate (20) having first (26) and second (27) surfaces on opposite sides of the substrate;
the method comprising:
placing a conductive etch stop material (25) at a predetermined position on the first surface of the silicon carbide substrate;
grinding the second surface of the substrate;
polishing the ground surface placing a transparent layer (34) selected from the group consisting of indium-tin-oxide and magnesium, oxide an the polished surface;
placing a photoresist (35) on the transparent layer of indium-tin-oxide optically aligning a mask on the photoresist that develops the photoresist to open at a point optically aligned with the conductive etch stop material on the opposite surface of the substrate etching a via (37) in the substrate from the masked second surface until 1 the etched via reaches entirely through the substrate to the conductive etch stop material;
and incorporating the conductive etch stop material on the first surface of the substrata into a device (22, 24) on. the first surface of the substrate.
12. A fabrication method according to Claim 11 wherein the conductive etch stop material is incorporated into the device prior to the steps of masking and etching the substrate.
13. A fabrication method according to Claim 11 comprising metallizing the via to form a conductive connection to the device.
14. A method according to Claim 11 of fabricating an integrated circuit an the silicon carbide substrate while eliminating wire bonding that can otherwise cause undesired inductance, the method comprising:

fabricating a semiconductor device on the first surface of the silicon carbide substrate and with at least one metal contact far the device on the first surface of the substrate and with said metal contact forming said etch stop material; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.
15. A fabricating method according to Claim 14 wherein the step of fabricating the metal contact on the first surface comprises depositing an indium-tin-oxide contact on the first surface.
16. A fabricating method according to Claim 15 further comprising covering the indium-tin-oxide contact with a gold coating.
CA2406054A 2000-04-11 2001-03-30 Method of forming vias in silicon carbide and resulting devices and circuits Expired - Lifetime CA2406054C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/546,821 US6475889B1 (en) 2000-04-11 2000-04-11 Method of forming vias in silicon carbide and resulting devices and circuits
US09/546,821 2000-04-11
PCT/US2001/010289 WO2001078120A1 (en) 2000-04-11 2001-03-30 Method of forming vias in silicon carbide and resulting devices and circuits

Publications (2)

Publication Number Publication Date
CA2406054A1 true CA2406054A1 (en) 2001-10-18
CA2406054C CA2406054C (en) 2010-12-21

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CA2406054A Expired - Lifetime CA2406054C (en) 2000-04-11 2001-03-30 Method of forming vias in silicon carbide and resulting devices and circuits

Country Status (11)

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US (4) US6475889B1 (en)
EP (2) EP1273032B1 (en)
JP (1) JP5142438B2 (en)
KR (1) KR100797130B1 (en)
CN (1) CN1197126C (en)
AT (1) ATE467231T1 (en)
AU (1) AU2001249659A1 (en)
CA (1) CA2406054C (en)
DE (1) DE60142035D1 (en)
TW (1) TW571383B (en)
WO (1) WO2001078120A1 (en)

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