CA2392307A1 - Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon - Google Patents
Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon Download PDFInfo
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- CA2392307A1 CA2392307A1 CA002392307A CA2392307A CA2392307A1 CA 2392307 A1 CA2392307 A1 CA 2392307A1 CA 002392307 A CA002392307 A CA 002392307A CA 2392307 A CA2392307 A CA 2392307A CA 2392307 A1 CA2392307 A1 CA 2392307A1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 120
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 120
- 239000010703 silicon Substances 0.000 title claims abstract description 120
- 238000000034 method Methods 0.000 title claims abstract description 78
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 40
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 16
- 238000004544 sputter deposition Methods 0.000 claims abstract description 59
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000012212 insulator Substances 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- 230000035515 penetration Effects 0.000 claims abstract description 12
- 230000005693 optoelectronics Effects 0.000 claims abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 7
- -1 nitrogen molecular ions Chemical class 0.000 claims abstract description 7
- 230000000737 periodic effect Effects 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000000137 annealing Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 abstract description 36
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 101100269674 Mus musculus Alyref2 gene Proteins 0.000 description 10
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- 238000005530 etching Methods 0.000 description 7
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- 230000000694 effects Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010884 ion-beam technique Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
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- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
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- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000013213 extrapolation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
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- 238000005211 surface analysis Methods 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
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- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
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- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/125—Quantum wire structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Abstract
A process for controllably forming silicon nanostructures such as a silicon quantum wire array. A silicon surface is sputtered by a uniform flow of nitrogen molecular ions in an ultrahigh vacuum so as to form a periodic wave - like relief in which the throughs of said relief are level with the silicon- insulator border of the SOI material. The ion energy, the ion incidence angl e to the surface of said material, the temperature of the silicon layer, the formation depth of the wave-like relief, the height of said wave-like relief and the ion penetration range into silicon are all determined on the basis o f a selected wavelength of the wave-like relief in the range of 9 nm to 120 nm . A silicon nitride mask having pendant edges is used to define the area of th e silicon surface on which the array is formed. Impurities are removed from th e silicon surface within the mask window prior to sputtering. For the purpose of forming a silicon quantum wire array, the thickness of the SOI silicon layer is selected to be greater than the sum of said formation depth, said height and said ion penetration range, the fabrication of the silicon wires being controlled by a threshold value of a secondary ion emission signal from the SOI insulator. The nanostructure may be employed in optoelectronic and nanoelectronic devices such as a FET.
Description
1 "Methods of Formation of a Silicon Nanostructure, a 2 Silicon Quantum Wire Array and Devices based thereon"
4 The invention relates to methods of forming quasi-one-dimensional solid-state silicon nanostructures. Such 6 nanostructures may form the basis for nanoscale 7 electronic and optoelectronic fabrication techniques, 8 particularly but not exclusively of silicon quantum 9 wire arrays, and can be used to fabricate silicon-based optoelectronic and nanoelectronic devices.
12 More particularly, the invention concerns forming 13 silicon quantum wires by ion irradiation and, more 14 specifically, to a process of sputtering a hi:-gh-purity surface of silicon-on-insulator (SOI) material by a.
16 uniform flow of nitrogen molecular ions, so as to form 17 a wave-like relief providing an array of nanoscale 18 silicon "quantum wires". The quantum wire array can be 19 used as a light source in optoelectronic devices through the array conduction or in nanoelectronic 21 devices; e.g. as a channel in a field effect transistor 22 (FET).
24 A known method for forming silicon quantum wires with a cross-section of 10x15 nm2 embedded in silicon oxide 26 uses low-energy ion implantation of oxygen into 27 silicon, electron-beam lithography and wet chemical 1 etching, followed by high-temperature annealing in an 2 inert environment. This results in the formation of 3 silicon quantum wires embedded in silicon oxide at the 4 bottom centre of V-grooves (Y. Ishikawa, N. Shibata, F.
Fukatsu "Fabrication of [110]-aligned Si quantum wires 6 embedded in Si02 by low-energy oxygen implantation"
7 Nuclear Instruments and Methods in Physics Research, B, 8 1999, v. 147, pp. 304-309;- Elsevier Science Ltd.) 9 [Refl] .
11 There are several disadvantages to this known method.
12 The use of electron-beam lithography and wet chemical 13 etching when forming V-grooves on the silicon surface 14 both limit the element density of the structure and reduce the wire yield. The absence of in situ control 16 of the process further reduces the wire yield. The 17 small wire density prevents the wires being useful for 18 nanoelectronic devices of the type in which the 19 interaction of charged particles in the neighbouring wires is important.
22 Previously published work, of which the present 23 inventors were among the joint authors, discloses a 24 method of forming wave-ordered-structures (WOS) on silicon, and in particular on SOI. The method 26 comprises the steps of sputtering the SOI silicon layer 27 by a nitrogen molecular ion probe scanned in a raster 28 pattern in an ultra-high vacuum so as to form a 29 periodical, wave-like nanoscale relief (WOS). The "wave front" of the nanoscale relief is in the 31 direction of the ion incidence. The method includes 32 detecting a secondary ion emission signal from the SOI
33 insulator and terminating sputtering when this signal 34 reaches a predetermined value. This reference also discloses the dependence of WOS formation upon the ion 36 energy, E, the ion incidence angle, 0, relative to the 1 surface normal, and the temperature, T, of the SOI
2 sample. The work also identifies a characteristic of 3 the relief formation process, namely the sputtering 4 depth Dm corresponding to the onset of intense growth of a WOS and discusses the dependency of Dm upon E, 8, T, 6 and the WOS wavelength ~. The work further indicates 7 that the SOI silicon thickness DB should not be less 8 than the sputtering depth at which a stable WOS is 9 formed with the desired wavelength (this depth being equal to the relief formation depth referred to 11 hereinafter as DF). (V. K. Smirnov, D.S. Kibalov, S.A.
12 Krivelevich, P.A. Lepshin, E.V. Potapov, R.A. Yankov, 13 W. Skorupa, V.V. Makarov, A.B. Danilin "Wave-ordered 14 structures formed on SOI wafers by reactive ion beams"
- Nuclear Instruments and Methods in Physics Research 16 B, 1999, v. 147, pp. 310-315; Elsevier Science Ltd.) 17 [Ref2 J .
19 Further work involving one of the present inventors discloses a process of annealing material of the type 21 disclosed in Ref2 in an inert environment at a 22 temperature of 1000°C for one hour and the resulting 23 internal structure of a WOS at the silicon-insulator 24 interface of the SOI material. (V. K. Smirnov,. A.B.
Danilin; "Nanoscale wave-ordered structures:on SOI"
26 Proceedings of the NATO Advanced Research Workshop.
27 "Perspective, science and technologies for novel 28 silicon on insulator devices"/Ed By P.I.F. Hemment, 29 1999, Elsevier Science Ltd.) [Ref3].
31 Further work involving one of the present inventors 32 discloses the dependencies of silicon nitride (Si3N4) 33 layer thickness, DN, on the ion energy E, ion incidence 34 angle to the surface and high-temperature annealing (900 - 1100°C for one hour). The annealing has no 36 effect on DN but maximises the Si/S13N4 interface 1 sharpness. As shown therein, DN is equal to the ion 2 penetration range into silicon, R, which is shown to be 3 a linear function of E for the same energy range as 4 that used for WOS formation. On the basis of data disclosed in this reference, the dependence of R on E
6 can be expressed as:
7 R (nm) - 1 . 5E (keV) +4 . (1) 9 (V. I. Bachurin, A.B. Churilov, E.V. Potapov, V.K.
Smirnov, V.V. Makarov and A.B. Danilin; "Formation of 11 Thin Silicon Nitride Layers on Si by Low Energy NZ' Ion 12 Bomardment" - Nuclear Instruments and Methods in 13 Physics Research B, 1999, v. 147, pp. 316-319) [Ref4].
The above mentioned references Ref2, Ref3 and Ref4 in 16 combination disclose a basic method for the formation 17 of a silicon quantum wire array. The principal 18 advantage of using a silicon quantum wire array, as 19 compared with the use of separated wires, in nanoelectronic and optoelectronic devices lies firstly 21 in the increase of device yield and enhancement of the 22 signal=to-noise ratio of the current characteristics, 2.3< and.also in providing the potential for new 24 capabilities in array-based devices due to the interaction of charged particles in neighbouring 26 quantum wires.
28 There are a number of disadvantages associated with-the 29 basic method as disclosed in Ref2, Ref3 and Ref4. Ref2 does not address the question of whether the WOS
31 wavelength a changes as the sputtering depth increases 32 from Dm to DF or whether there is any inter-relationship 33 between Dm and DF. The present invention recognises 34 that the characteristics of the process should be related to the final WOS structure as developed at the 36 depth DF rather than to the depth Dm as discussed in WO 01/39259 PCT/IB00/0139?
1 Ref2. In addition, Ref2 does not address the question 2 of whether there are limits of the domain in the (E, 8) 3 plane in which WOS formation takes place.
12 More particularly, the invention concerns forming 13 silicon quantum wires by ion irradiation and, more 14 specifically, to a process of sputtering a hi:-gh-purity surface of silicon-on-insulator (SOI) material by a.
16 uniform flow of nitrogen molecular ions, so as to form 17 a wave-like relief providing an array of nanoscale 18 silicon "quantum wires". The quantum wire array can be 19 used as a light source in optoelectronic devices through the array conduction or in nanoelectronic 21 devices; e.g. as a channel in a field effect transistor 22 (FET).
24 A known method for forming silicon quantum wires with a cross-section of 10x15 nm2 embedded in silicon oxide 26 uses low-energy ion implantation of oxygen into 27 silicon, electron-beam lithography and wet chemical 1 etching, followed by high-temperature annealing in an 2 inert environment. This results in the formation of 3 silicon quantum wires embedded in silicon oxide at the 4 bottom centre of V-grooves (Y. Ishikawa, N. Shibata, F.
Fukatsu "Fabrication of [110]-aligned Si quantum wires 6 embedded in Si02 by low-energy oxygen implantation"
7 Nuclear Instruments and Methods in Physics Research, B, 8 1999, v. 147, pp. 304-309;- Elsevier Science Ltd.) 9 [Refl] .
11 There are several disadvantages to this known method.
12 The use of electron-beam lithography and wet chemical 13 etching when forming V-grooves on the silicon surface 14 both limit the element density of the structure and reduce the wire yield. The absence of in situ control 16 of the process further reduces the wire yield. The 17 small wire density prevents the wires being useful for 18 nanoelectronic devices of the type in which the 19 interaction of charged particles in the neighbouring wires is important.
22 Previously published work, of which the present 23 inventors were among the joint authors, discloses a 24 method of forming wave-ordered-structures (WOS) on silicon, and in particular on SOI. The method 26 comprises the steps of sputtering the SOI silicon layer 27 by a nitrogen molecular ion probe scanned in a raster 28 pattern in an ultra-high vacuum so as to form a 29 periodical, wave-like nanoscale relief (WOS). The "wave front" of the nanoscale relief is in the 31 direction of the ion incidence. The method includes 32 detecting a secondary ion emission signal from the SOI
33 insulator and terminating sputtering when this signal 34 reaches a predetermined value. This reference also discloses the dependence of WOS formation upon the ion 36 energy, E, the ion incidence angle, 0, relative to the 1 surface normal, and the temperature, T, of the SOI
2 sample. The work also identifies a characteristic of 3 the relief formation process, namely the sputtering 4 depth Dm corresponding to the onset of intense growth of a WOS and discusses the dependency of Dm upon E, 8, T, 6 and the WOS wavelength ~. The work further indicates 7 that the SOI silicon thickness DB should not be less 8 than the sputtering depth at which a stable WOS is 9 formed with the desired wavelength (this depth being equal to the relief formation depth referred to 11 hereinafter as DF). (V. K. Smirnov, D.S. Kibalov, S.A.
12 Krivelevich, P.A. Lepshin, E.V. Potapov, R.A. Yankov, 13 W. Skorupa, V.V. Makarov, A.B. Danilin "Wave-ordered 14 structures formed on SOI wafers by reactive ion beams"
- Nuclear Instruments and Methods in Physics Research 16 B, 1999, v. 147, pp. 310-315; Elsevier Science Ltd.) 17 [Ref2 J .
19 Further work involving one of the present inventors discloses a process of annealing material of the type 21 disclosed in Ref2 in an inert environment at a 22 temperature of 1000°C for one hour and the resulting 23 internal structure of a WOS at the silicon-insulator 24 interface of the SOI material. (V. K. Smirnov,. A.B.
Danilin; "Nanoscale wave-ordered structures:on SOI"
26 Proceedings of the NATO Advanced Research Workshop.
27 "Perspective, science and technologies for novel 28 silicon on insulator devices"/Ed By P.I.F. Hemment, 29 1999, Elsevier Science Ltd.) [Ref3].
31 Further work involving one of the present inventors 32 discloses the dependencies of silicon nitride (Si3N4) 33 layer thickness, DN, on the ion energy E, ion incidence 34 angle to the surface and high-temperature annealing (900 - 1100°C for one hour). The annealing has no 36 effect on DN but maximises the Si/S13N4 interface 1 sharpness. As shown therein, DN is equal to the ion 2 penetration range into silicon, R, which is shown to be 3 a linear function of E for the same energy range as 4 that used for WOS formation. On the basis of data disclosed in this reference, the dependence of R on E
6 can be expressed as:
7 R (nm) - 1 . 5E (keV) +4 . (1) 9 (V. I. Bachurin, A.B. Churilov, E.V. Potapov, V.K.
Smirnov, V.V. Makarov and A.B. Danilin; "Formation of 11 Thin Silicon Nitride Layers on Si by Low Energy NZ' Ion 12 Bomardment" - Nuclear Instruments and Methods in 13 Physics Research B, 1999, v. 147, pp. 316-319) [Ref4].
The above mentioned references Ref2, Ref3 and Ref4 in 16 combination disclose a basic method for the formation 17 of a silicon quantum wire array. The principal 18 advantage of using a silicon quantum wire array, as 19 compared with the use of separated wires, in nanoelectronic and optoelectronic devices lies firstly 21 in the increase of device yield and enhancement of the 22 signal=to-noise ratio of the current characteristics, 2.3< and.also in providing the potential for new 24 capabilities in array-based devices due to the interaction of charged particles in neighbouring 26 quantum wires.
28 There are a number of disadvantages associated with-the 29 basic method as disclosed in Ref2, Ref3 and Ref4. Ref2 does not address the question of whether the WOS
31 wavelength a changes as the sputtering depth increases 32 from Dm to DF or whether there is any inter-relationship 33 between Dm and DF. The present invention recognises 34 that the characteristics of the process should be related to the final WOS structure as developed at the 36 depth DF rather than to the depth Dm as discussed in WO 01/39259 PCT/IB00/0139?
1 Ref2. In addition, Ref2 does not address the question 2 of whether there are limits of the domain in the (E, 8) 3 plane in which WOS formation takes place.
5 Such limitations in the work disclosed in Ref2, Ref3 6 and Ref4 mean that the required thickness of the SOI
silicon layer cannot generally be predetermined from 8 the relationships between the various parameters as 9 discussed in these references. In addition, the essential parameters for controlling the sputtering 11 process (ion energy E, ion incidence angle A and SOI
12 temperature T) cannot be predetermined. Further, for 13 the isolation of neighbouring silicon wires in the WOS
14 formed in SOI, it is important to ensure the troughs of.
the WOS relief coincide accurately with the border 16 between the SOI silicon layer and the SOI insulator 17. layer. Ref2 discloses that the secondary ion emission 18 signal may be employed as a basis for terminating the 19 sputtering process, but does not disclose any way of 2p pre-determining a value of the signal which corresponds-21 to isolation of the silicon wires.
23 That is, the previously published work does:not 24 disclose a general method allowing a WOS to:be formed reliably such that the troughs of the WOS coincide with 26 the SOI silicon-insulator border so as to form an array 27 of isolated silicon wires.
29 In addition, for practical purposes in applying such a process by integration with silicon-based 31 nanoelectronic and optoelectronic technology, it is 32 necessary to ensure the formation of the nanostructure 33 array on a specified microarea of the surface in order 34 to obtain a useful structure, for example, in the form of two isolated silicon pads connected by the array.
36 However, the previously published work does not address 1 such issues as whether techniques such as lithography 2 may be used for this purpose or, if so, what masking 3 layers, if any, might be used.
The present inventors have also determined that the WOS
6 formation process is highly sensitive to the presence 7 of impurities on the SOI surface, particularly the 8 presence of silicon oxide, which degrades the flatness 9 of the WOS relief. As is well known, a thin layer of natural silicon oxide is always present on the surface 11 of silicon exposed to air.
13 All of the abovementioned disadvantages are related in 14 one way or another to the controllability of the WOS
formation process for practical purposes.
17 Nanoelectronic devices are known containing silicon 18 pads connected by a silicon channel with a 20-nm 19 diameter (a so-called "quantum dot"), a 40-nm thick insulator layer covering the surface of the pads and 21 the channel, and an electrode positioned on the surface 22 of the insulator layer. The silicon contact pads and 23 the channel are formed i:n the silicon layer of SOI
24 material (E. Leobandung, L. Guo, Y. Wang, S.Chou "Observation of quantum effects and Coulomb blockade in 26 silicon quantum-dot transistors at temperature over 27 100K" Applied Physics Letters, v. 67, No7 , 1995, pp.
28 938-940, American Institute of Physics, 1995) [Refs].
The disadvantages of this known device lie in the 31 absence of a channel array and in a low device yield 32 because the small dimensions of the devices approach 33 the limits of micro-lithography techniques; i.e. there 34 is low repeatability of the operational results.
36 There is also another device, a quantum-wire-based FET
1 containing silicon pads connected by seven silicon 2 linear channels with a 86x100 nmz rectangular section.
3 The silicon channels are covered with a 30-nm thick 4 silicon oxide layer. An electrode gate is positioned above the group of these channels. This device is made 6 using SOI material (J.P. Colinge, X. Baie, V. Bayot, E.
7 Grivei "A silicon-On-Insulator Quantum Wire" - Solid-8 State Electronics, Vol. 39, No 1, 1996, pp. 49-51, 9 Elsevier Science Ltd 1996) [Ref6].
11 The disadvantage of this known device lies in the 12 impossibility of forming silicon channels at a distance 13 equal to the size of the channel because of the 14 limitations of the known lithography methods used for the fabrication of the device.
17 The various references cited above show how it is 18 possible to fabricate a silicon quantum wire array in 19 particular experimental cases. However, none addresses.
the problem of how to generalise particular 21 experimental processes so that the quantum wires can be 22 made with predetermined dimensions or how to exercise 23 effective process control. In addition, there is a 24 need for integrating the silicon quantum wire array into useful devices; e.g. so as to form a channel array 26 in an EET.
28 In accordance with a first aspect of the invention, 29 there is provided a method of forming a silicon nanostructure, comprising:
31 sputtering a silicon surface by a uniform flow of 32 nitrogen molecular ions in an ultra-high vacuum so as 33 to form a periodic wave-like relief, the wave front of 34 said relief being in the direction of the ion incidence plane; further including the following steps:
36 prior to sputtering:
1 selecting a desired wavelength of the periodic 2 wave-like relief in the range 9 nm to 120 nm;
3 determining the ion energy, the ion incidence 4 angle to the surface of said material, the temperature of said silicon layer, the formation depth of said 6 wave-like relief, the height of said wave-like relief 7 and the ion penetration range into silicon, all on the 8 basis of said selected wavelength.
Preferably, said ion energy, said ion incidence angle, 11 said temperature of said silicon, said formation depth 12 and said height of said wave-like relief are determined 13 on the basis of previously obtained empirical data 14 relating said ion energy, said ion incidence angle, said temperature of said silicon, said formation depth 16 and said height of said wave-like relief to the 17 wavelength of said periodic wave-like relief, and 18 wherein said ion penetration range is determined from 19. said ion energy.
21 Preferably, the method further includes the step, prior 22 to sputtering, of positioning a silicon nitride mask 23 containing a window with pendant edges on said silicon 24 surface over the sputter area, and sputtering said silicon surface through said window.
27 Preferably, the method further includes the step, prior 28 to sputtering, of removing any impurities from the 29 surface of the said silicon layer on which said wave-like relief is to be formed.
32 Preferably, the method further includes, subsequent to 33 sputtering:
34 annealing the material with said relief in an inert environment. Preferably, the material is 36 annealed at a temperature between 1000 and 1200°C for a 1 period of at least one hour.
3 In preferred embodiments of the invention, said silicon 4 nanostructure comprises a silicon quantum wire array and said silicon comprises a silicon layer of a 6 silicon-on-insulator material, the method further 7 including:
8 selecting the thickness of said silicon layer to 9 be greater than the sum of said formation depth of said wave-like relief, said height of said wave-like relief, 11 and said ion penetration range.
13 Preferably, the method further includes:
14 during sputtering:
detecting a secondary ion emission signal from the 16 insulator layer of said silicon-on-insulator material;
17 and 18 terminating sputtering when the value of the 19 detected signal reaches a predetermined threshold value;
22 Preferably, said threshold value of said secondary ion 23. emission signal is that value at which the signal 24 exceeds an average background value by an amount equal to the peak-to-peak height of a noise component of the 26 signal.
28 In accordance with further aspects of the invention, 29 there are provided optoelectronic and electronic devices including quantum wire arrays formed by the 31 method of the first aspect of the invention, such as a 32 device comprising silicon pads connected by said 33 silicon quantum wire array, an insulator layer 34 positioned on said quantum wire array, and an electrode positioned on said insulator.
1 Apparatus for implementing the method consists of an 2 ultra-high vacuum chamber, a sample introduction 3 attachment, an ion microbeam column with adjustable ion 4 energy and ion probe position on the sample surface, an 5 electron gun, a sample holder with positioning, tilting 6 and rotation functions and means for varying and 7 controlling the sample temperature, a secondary 8 electron detector, and a secondary ion mass analyzer.
9 Suitable apparatus is known in the prior art as a 10 multi-technique surface analysis high capability 11 instrument.
silicon layer cannot generally be predetermined from 8 the relationships between the various parameters as 9 discussed in these references. In addition, the essential parameters for controlling the sputtering 11 process (ion energy E, ion incidence angle A and SOI
12 temperature T) cannot be predetermined. Further, for 13 the isolation of neighbouring silicon wires in the WOS
14 formed in SOI, it is important to ensure the troughs of.
the WOS relief coincide accurately with the border 16 between the SOI silicon layer and the SOI insulator 17. layer. Ref2 discloses that the secondary ion emission 18 signal may be employed as a basis for terminating the 19 sputtering process, but does not disclose any way of 2p pre-determining a value of the signal which corresponds-21 to isolation of the silicon wires.
23 That is, the previously published work does:not 24 disclose a general method allowing a WOS to:be formed reliably such that the troughs of the WOS coincide with 26 the SOI silicon-insulator border so as to form an array 27 of isolated silicon wires.
29 In addition, for practical purposes in applying such a process by integration with silicon-based 31 nanoelectronic and optoelectronic technology, it is 32 necessary to ensure the formation of the nanostructure 33 array on a specified microarea of the surface in order 34 to obtain a useful structure, for example, in the form of two isolated silicon pads connected by the array.
36 However, the previously published work does not address 1 such issues as whether techniques such as lithography 2 may be used for this purpose or, if so, what masking 3 layers, if any, might be used.
The present inventors have also determined that the WOS
6 formation process is highly sensitive to the presence 7 of impurities on the SOI surface, particularly the 8 presence of silicon oxide, which degrades the flatness 9 of the WOS relief. As is well known, a thin layer of natural silicon oxide is always present on the surface 11 of silicon exposed to air.
13 All of the abovementioned disadvantages are related in 14 one way or another to the controllability of the WOS
formation process for practical purposes.
17 Nanoelectronic devices are known containing silicon 18 pads connected by a silicon channel with a 20-nm 19 diameter (a so-called "quantum dot"), a 40-nm thick insulator layer covering the surface of the pads and 21 the channel, and an electrode positioned on the surface 22 of the insulator layer. The silicon contact pads and 23 the channel are formed i:n the silicon layer of SOI
24 material (E. Leobandung, L. Guo, Y. Wang, S.Chou "Observation of quantum effects and Coulomb blockade in 26 silicon quantum-dot transistors at temperature over 27 100K" Applied Physics Letters, v. 67, No7 , 1995, pp.
28 938-940, American Institute of Physics, 1995) [Refs].
The disadvantages of this known device lie in the 31 absence of a channel array and in a low device yield 32 because the small dimensions of the devices approach 33 the limits of micro-lithography techniques; i.e. there 34 is low repeatability of the operational results.
36 There is also another device, a quantum-wire-based FET
1 containing silicon pads connected by seven silicon 2 linear channels with a 86x100 nmz rectangular section.
3 The silicon channels are covered with a 30-nm thick 4 silicon oxide layer. An electrode gate is positioned above the group of these channels. This device is made 6 using SOI material (J.P. Colinge, X. Baie, V. Bayot, E.
7 Grivei "A silicon-On-Insulator Quantum Wire" - Solid-8 State Electronics, Vol. 39, No 1, 1996, pp. 49-51, 9 Elsevier Science Ltd 1996) [Ref6].
11 The disadvantage of this known device lies in the 12 impossibility of forming silicon channels at a distance 13 equal to the size of the channel because of the 14 limitations of the known lithography methods used for the fabrication of the device.
17 The various references cited above show how it is 18 possible to fabricate a silicon quantum wire array in 19 particular experimental cases. However, none addresses.
the problem of how to generalise particular 21 experimental processes so that the quantum wires can be 22 made with predetermined dimensions or how to exercise 23 effective process control. In addition, there is a 24 need for integrating the silicon quantum wire array into useful devices; e.g. so as to form a channel array 26 in an EET.
28 In accordance with a first aspect of the invention, 29 there is provided a method of forming a silicon nanostructure, comprising:
31 sputtering a silicon surface by a uniform flow of 32 nitrogen molecular ions in an ultra-high vacuum so as 33 to form a periodic wave-like relief, the wave front of 34 said relief being in the direction of the ion incidence plane; further including the following steps:
36 prior to sputtering:
1 selecting a desired wavelength of the periodic 2 wave-like relief in the range 9 nm to 120 nm;
3 determining the ion energy, the ion incidence 4 angle to the surface of said material, the temperature of said silicon layer, the formation depth of said 6 wave-like relief, the height of said wave-like relief 7 and the ion penetration range into silicon, all on the 8 basis of said selected wavelength.
Preferably, said ion energy, said ion incidence angle, 11 said temperature of said silicon, said formation depth 12 and said height of said wave-like relief are determined 13 on the basis of previously obtained empirical data 14 relating said ion energy, said ion incidence angle, said temperature of said silicon, said formation depth 16 and said height of said wave-like relief to the 17 wavelength of said periodic wave-like relief, and 18 wherein said ion penetration range is determined from 19. said ion energy.
21 Preferably, the method further includes the step, prior 22 to sputtering, of positioning a silicon nitride mask 23 containing a window with pendant edges on said silicon 24 surface over the sputter area, and sputtering said silicon surface through said window.
27 Preferably, the method further includes the step, prior 28 to sputtering, of removing any impurities from the 29 surface of the said silicon layer on which said wave-like relief is to be formed.
32 Preferably, the method further includes, subsequent to 33 sputtering:
34 annealing the material with said relief in an inert environment. Preferably, the material is 36 annealed at a temperature between 1000 and 1200°C for a 1 period of at least one hour.
3 In preferred embodiments of the invention, said silicon 4 nanostructure comprises a silicon quantum wire array and said silicon comprises a silicon layer of a 6 silicon-on-insulator material, the method further 7 including:
8 selecting the thickness of said silicon layer to 9 be greater than the sum of said formation depth of said wave-like relief, said height of said wave-like relief, 11 and said ion penetration range.
13 Preferably, the method further includes:
14 during sputtering:
detecting a secondary ion emission signal from the 16 insulator layer of said silicon-on-insulator material;
17 and 18 terminating sputtering when the value of the 19 detected signal reaches a predetermined threshold value;
22 Preferably, said threshold value of said secondary ion 23. emission signal is that value at which the signal 24 exceeds an average background value by an amount equal to the peak-to-peak height of a noise component of the 26 signal.
28 In accordance with further aspects of the invention, 29 there are provided optoelectronic and electronic devices including quantum wire arrays formed by the 31 method of the first aspect of the invention, such as a 32 device comprising silicon pads connected by said 33 silicon quantum wire array, an insulator layer 34 positioned on said quantum wire array, and an electrode positioned on said insulator.
1 Apparatus for implementing the method consists of an 2 ultra-high vacuum chamber, a sample introduction 3 attachment, an ion microbeam column with adjustable ion 4 energy and ion probe position on the sample surface, an 5 electron gun, a sample holder with positioning, tilting 6 and rotation functions and means for varying and 7 controlling the sample temperature, a secondary 8 electron detector, and a secondary ion mass analyzer.
9 Suitable apparatus is known in the prior art as a 10 multi-technique surface analysis high capability 11 instrument.
13 The invention overcomes the disadvantages of the prior 14 art by providing controllability of the process on the basis of a single parameter, namely the desired array 16 period (wavelength), which governs all of the relevant 17 parameters of the process.
19 Embodiments of the invention will now be described, by way of example only, with reference to the accompanying 21 drawings in which:
23 Fig. 1A is a schematic perspective view of an 24 initial SOI structure, including a silicon nitride mask, for use in accordance with the present invention;
26 Fig. 1B is a schematic perspective view of a final 27 SOI structure after application of the method in 28 accordance with the present invention to the initial 29 structure of Fig. 1A;
Fig. 1C is a graph illustrating the manner in 31 which a secondary ion emission signal is employed in 32 controlling the method in accordance with the present 33 invention;
34 Fig. 1D is a cross sectional view, greatly enlarged, of a portion of the sputtered structure of 36 Fig. 1B (detail A of Fig. 1B);
1 Fig. 1E is a graph showing the relationship 2 between ion incidence angle, ion energy and the 3 wavelength of a WOS formed in accordance with the 4 present invention;
Fig. 1F is a graph showing the manner in which the 6 wavelength of a WOS formed in accordance with the 7 present invention varies with the temperature of the 8 SOI material for different ion energies;
9 Figs. 2A to 2D are schematic plan views of an SOI
structure illustrating the formation of a FET device in 11 accordance with the present invention; and 12 Fig. 3 is a schematic perspective view 13 illustrating the structure of a FET with channels in 14 the form of a silicon nanostructure array formed in accordance with the present invention.
17 Referring now to the drawings, Fig. 1A shows an example 18 of an initial SOI structure for use in accordance with 19 the invention, comprising a silicon substrate 5, a silicon oxide insulating layer 4, a silicon layer 3, in 21 which the quantum wires are to be formed, a thin 22 silicon oxide layer 2 formed on top of the silicon 23 layer 3 and a silicon nitride masking layer 1 formed on 24 top of the thin silicon oxide layer 2. Fig. 1B shows the structure after sputtering in accordance with the 26 invention, comprising the silicon substrate 5 and 27 silicon oxide insulating layer 4 as in Fig. 1A, and in 28 which the silicon layer 3 of Fig. 1A has been modified 29 by the sputtering to leave a silicon layer 6 in the areas masked by the masking layer 1 of Fig. 1A and a 31 silicon nanostructure array 7 formed by the sputtering 32 process in the area left exposed by the masking layer 33 1. Arrows indicate the direction of N2+ ion flow during 34 sputtering.
36 The basic sputtering process for forming a WOS is 1 described in Ref2. As described therein, a focused ion 2 beam is raster-scanned across the surface of the SOI
3 material.
Fig. 1D illustrates an example of the cross-section of 6 the silicon nanostructure array formed by a sputtering 7 process in accordance with the present invention, which 8 contains regions of amorphous silicon nitride 8, 9 regions of a mixture of amorphous silicon and silicon nitride 9, regions of silicon oxynitride 10, and 11 regions of crystal silicon 12.
13 The following parameters relating to the SOI material, 14 the WOS structure and the WOS formation process are referred to herein, as illustrated in Fig. 1:
16 DB is the initial thickness of the silicon layer 3 17 of the SOI material.
18 DF is the relief formation depth (i.e. the minimum 19 depth of material removed by sputtering from the original surface of the silicon layer 3 to the crests 21 of the waves of the WOS in order to obtain a stable 22 WOS, the "sputtering depth" being the vertical distance 23 from the original silicon surface to the top of the 24 WOS) .
H is the height of the stabilised WOS relief; i.e.
26 the vertical distance between the wave crest and the 27 nearest wave trough (double the wave amplitude).
28 R is the ion penetration range into silicon for a 29 given ion energy.
31 The present invention is particularly concerned with 32 controlling the sputtering process in order to allow 33 the required silicon nanostructure to be formed 34 reliably with predetermined parameters. Further investigation of the WOS formation process by the 36 present inventors has led to the following conclusions:
1 (a) The WOS wavelength J. remains constant from the 2 initial onset of the formation of the WOS at sputtering 3 depth Dm through to the stabilisation of the WOS
4 structure at sputtering depth DF (the relief formation depth) and thereafter under continued sputtering up to 6 depths several.times the value of DF.
7 (b) The relief height increases linearly with time 8 from the depth Dm to the depth DF, reaching the value H
9 at depth DF and remaining constant thereafter under continued sputtering. That is, the shape and 11 dimensions of the WOS remain substantially constant 12 under continued sputtering beyond DF, however the 13 position of the WOS on the SOI material migrates in a 14 direction opposite to the direction of ion incidence (the broken line 13 in Fig. 1D illustrates the position 16 of the WOS at the time when the sputtering depth equals 17 DF, whilst the main drawing indicates the structure at a 18 later time after sputtering has been terminated).
19 (c) DF is related to Dm by the formula:
2 0 DF = 1 . 5 Dm .
21 (d) DF is related to the WOS wavelength 7~ by the 22 formula:
23 DF(nm) - 1.316 (~ (nm) - 9) (2) 24 for ~ in the range 9 nm to 120 nm.
(e) H is proportional to ~, this proportionality 26 varying with the angle of incidence of the ion beam, 6;
27 e.g.
28 H = 0.26 for A = 41°
29 H = 0.25 for 8 = 43°
H = 0.23 for 8 = 45°
31 H = 0.22a for 8 = 55°
32 H = 0.22 for 8 = 58°. (3) 33 (f) The behaviour of the "true" secondary electron 34 emission from the ion sputtered area of the silicon surface reflects the appearance of the WOS at the 36 sputtering depth Dm and the formation of the stabilised 1 WOS at the sputtering depth DF. The onset of the 2 emission increase is related to the sputtering depth.
4 Investigations were also conducted to determine the manner in which a depends on the ion beam energy E, the 6 ion beam incidence angle a and the temperature of the 7 SOI material, T (or, more specifically, the temperature 8 of the SOI silicon layer). Fig. 1E illustrates data 9 showing how ~ varies with E and 8 at room temperature.
The curve 15 defines the limit of the domain in which 11 WOS formation takes place. The curves 15, 16 and 120 12 limit the part of the WOS domain in which the wave-like 13 relief has a more coherent structure with a linear 14 relationship between ~ and DF according to the formula (2). Fig. 1F illustrates how ~ varies with T for 16 different values of E and 8. Curve 22 corresponds to E
17 - 9 keV, 8 = 45°. Curve 24 corresponds to E = 5 keV, 8 18 - 45°. Curve 2'6 corresponds to E = 9 keV, 8 = 55°.
From these data, it can be seen that, at room 21 temperature, ~ can vary within a useful range of values 22 from 30 nm to 120 nm. Varying the temperature of .the 23 sample from room temperature to 550 K has no 24 significant effect. Heating the sample from 550 K up to 850 K reduces the value of ~ by a factor of 3.3 as 26 compared with the equivalent value at room temperature.
28 The inventors have further determined that the depth DH
29 of the silicon layer 3 of the SOI material required for a given WOS can be expressed by the formula:
31 DB > DF + H + R ( 4 ) 33 It will be noted that a depth DH = DF + H is sufficient 34 for a stable WOS to be formed. However, the present inventors have discovered that it is important for the 36 ion penetration range R to be taken into account when 1 calculating the minimum depth DH in order to ensure the 2 reliable formation of mutually isolated quantum silicon 3 wires by the sputtering process and/or subsequent high 4 temperature annealing of the sputtered product.
6 The inventors' investigations also confirmed that the 7 secondary emission of ions from the SOI insulator 8 begins when the troughs of the WOS reach a distance of 9 about R from the silicon-insulator border of the SOI
10 material (this effect of prior detection of a buried 11 border being previously known in the field of sputter 12 depth profiling).
14 These observations provide the basis for controlling 15 the formation of the desired silicon nanostructures on 16 the basis of a predetermined value of the WOS
19 Embodiments of the invention will now be described, by way of example only, with reference to the accompanying 21 drawings in which:
23 Fig. 1A is a schematic perspective view of an 24 initial SOI structure, including a silicon nitride mask, for use in accordance with the present invention;
26 Fig. 1B is a schematic perspective view of a final 27 SOI structure after application of the method in 28 accordance with the present invention to the initial 29 structure of Fig. 1A;
Fig. 1C is a graph illustrating the manner in 31 which a secondary ion emission signal is employed in 32 controlling the method in accordance with the present 33 invention;
34 Fig. 1D is a cross sectional view, greatly enlarged, of a portion of the sputtered structure of 36 Fig. 1B (detail A of Fig. 1B);
1 Fig. 1E is a graph showing the relationship 2 between ion incidence angle, ion energy and the 3 wavelength of a WOS formed in accordance with the 4 present invention;
Fig. 1F is a graph showing the manner in which the 6 wavelength of a WOS formed in accordance with the 7 present invention varies with the temperature of the 8 SOI material for different ion energies;
9 Figs. 2A to 2D are schematic plan views of an SOI
structure illustrating the formation of a FET device in 11 accordance with the present invention; and 12 Fig. 3 is a schematic perspective view 13 illustrating the structure of a FET with channels in 14 the form of a silicon nanostructure array formed in accordance with the present invention.
17 Referring now to the drawings, Fig. 1A shows an example 18 of an initial SOI structure for use in accordance with 19 the invention, comprising a silicon substrate 5, a silicon oxide insulating layer 4, a silicon layer 3, in 21 which the quantum wires are to be formed, a thin 22 silicon oxide layer 2 formed on top of the silicon 23 layer 3 and a silicon nitride masking layer 1 formed on 24 top of the thin silicon oxide layer 2. Fig. 1B shows the structure after sputtering in accordance with the 26 invention, comprising the silicon substrate 5 and 27 silicon oxide insulating layer 4 as in Fig. 1A, and in 28 which the silicon layer 3 of Fig. 1A has been modified 29 by the sputtering to leave a silicon layer 6 in the areas masked by the masking layer 1 of Fig. 1A and a 31 silicon nanostructure array 7 formed by the sputtering 32 process in the area left exposed by the masking layer 33 1. Arrows indicate the direction of N2+ ion flow during 34 sputtering.
36 The basic sputtering process for forming a WOS is 1 described in Ref2. As described therein, a focused ion 2 beam is raster-scanned across the surface of the SOI
3 material.
Fig. 1D illustrates an example of the cross-section of 6 the silicon nanostructure array formed by a sputtering 7 process in accordance with the present invention, which 8 contains regions of amorphous silicon nitride 8, 9 regions of a mixture of amorphous silicon and silicon nitride 9, regions of silicon oxynitride 10, and 11 regions of crystal silicon 12.
13 The following parameters relating to the SOI material, 14 the WOS structure and the WOS formation process are referred to herein, as illustrated in Fig. 1:
16 DB is the initial thickness of the silicon layer 3 17 of the SOI material.
18 DF is the relief formation depth (i.e. the minimum 19 depth of material removed by sputtering from the original surface of the silicon layer 3 to the crests 21 of the waves of the WOS in order to obtain a stable 22 WOS, the "sputtering depth" being the vertical distance 23 from the original silicon surface to the top of the 24 WOS) .
H is the height of the stabilised WOS relief; i.e.
26 the vertical distance between the wave crest and the 27 nearest wave trough (double the wave amplitude).
28 R is the ion penetration range into silicon for a 29 given ion energy.
31 The present invention is particularly concerned with 32 controlling the sputtering process in order to allow 33 the required silicon nanostructure to be formed 34 reliably with predetermined parameters. Further investigation of the WOS formation process by the 36 present inventors has led to the following conclusions:
1 (a) The WOS wavelength J. remains constant from the 2 initial onset of the formation of the WOS at sputtering 3 depth Dm through to the stabilisation of the WOS
4 structure at sputtering depth DF (the relief formation depth) and thereafter under continued sputtering up to 6 depths several.times the value of DF.
7 (b) The relief height increases linearly with time 8 from the depth Dm to the depth DF, reaching the value H
9 at depth DF and remaining constant thereafter under continued sputtering. That is, the shape and 11 dimensions of the WOS remain substantially constant 12 under continued sputtering beyond DF, however the 13 position of the WOS on the SOI material migrates in a 14 direction opposite to the direction of ion incidence (the broken line 13 in Fig. 1D illustrates the position 16 of the WOS at the time when the sputtering depth equals 17 DF, whilst the main drawing indicates the structure at a 18 later time after sputtering has been terminated).
19 (c) DF is related to Dm by the formula:
2 0 DF = 1 . 5 Dm .
21 (d) DF is related to the WOS wavelength 7~ by the 22 formula:
23 DF(nm) - 1.316 (~ (nm) - 9) (2) 24 for ~ in the range 9 nm to 120 nm.
(e) H is proportional to ~, this proportionality 26 varying with the angle of incidence of the ion beam, 6;
27 e.g.
28 H = 0.26 for A = 41°
29 H = 0.25 for 8 = 43°
H = 0.23 for 8 = 45°
31 H = 0.22a for 8 = 55°
32 H = 0.22 for 8 = 58°. (3) 33 (f) The behaviour of the "true" secondary electron 34 emission from the ion sputtered area of the silicon surface reflects the appearance of the WOS at the 36 sputtering depth Dm and the formation of the stabilised 1 WOS at the sputtering depth DF. The onset of the 2 emission increase is related to the sputtering depth.
4 Investigations were also conducted to determine the manner in which a depends on the ion beam energy E, the 6 ion beam incidence angle a and the temperature of the 7 SOI material, T (or, more specifically, the temperature 8 of the SOI silicon layer). Fig. 1E illustrates data 9 showing how ~ varies with E and 8 at room temperature.
The curve 15 defines the limit of the domain in which 11 WOS formation takes place. The curves 15, 16 and 120 12 limit the part of the WOS domain in which the wave-like 13 relief has a more coherent structure with a linear 14 relationship between ~ and DF according to the formula (2). Fig. 1F illustrates how ~ varies with T for 16 different values of E and 8. Curve 22 corresponds to E
17 - 9 keV, 8 = 45°. Curve 24 corresponds to E = 5 keV, 8 18 - 45°. Curve 2'6 corresponds to E = 9 keV, 8 = 55°.
From these data, it can be seen that, at room 21 temperature, ~ can vary within a useful range of values 22 from 30 nm to 120 nm. Varying the temperature of .the 23 sample from room temperature to 550 K has no 24 significant effect. Heating the sample from 550 K up to 850 K reduces the value of ~ by a factor of 3.3 as 26 compared with the equivalent value at room temperature.
28 The inventors have further determined that the depth DH
29 of the silicon layer 3 of the SOI material required for a given WOS can be expressed by the formula:
31 DB > DF + H + R ( 4 ) 33 It will be noted that a depth DH = DF + H is sufficient 34 for a stable WOS to be formed. However, the present inventors have discovered that it is important for the 36 ion penetration range R to be taken into account when 1 calculating the minimum depth DH in order to ensure the 2 reliable formation of mutually isolated quantum silicon 3 wires by the sputtering process and/or subsequent high 4 temperature annealing of the sputtered product.
6 The inventors' investigations also confirmed that the 7 secondary emission of ions from the SOI insulator 8 begins when the troughs of the WOS reach a distance of 9 about R from the silicon-insulator border of the SOI
10 material (this effect of prior detection of a buried 11 border being previously known in the field of sputter 12 depth profiling).
14 These observations provide the basis for controlling 15 the formation of the desired silicon nanostructures on 16 the basis of a predetermined value of the WOS
17 wavelength 7..
19 The.data illustrated in Fig. 1E allow values of E and a to be determined for a desired value of 7. in the range 21 from 30 nm to 120 nm at room temperature, 30 nm being 22 the minimum .obtainable at room temperature (with E =
23 2 keV and 8 = 58°). Smaller values of ~ can be obtained 24 by heating the SOI material above 550K, as shown in Fig. 1F.
27 Accordingly, for a selected value of 7., suitable values 28 of E, 8 and T can be determined. The ion penetration 29 range and the formation depth DF can be calculated from formulae (1) and (2) and from empirical data (3), and 31 the required depth DF of the SOI silicon layer can then 32 be calculated from formula (4) .
34 For example, if it is desired to fabricate a silicon quantum wire array with a wire period (~) of 30 nm, 36 from Fig. 1E it can be determined (by extrapolation) 1 that for ~ = 30 nm, E = 2 keV and B = 58°. From these 2 values, it can be determined that R = 7 nm, H = 6.6 nm, 3 DF = 27.6 nm, and therefore DB = 41.2 nm.
In a further example, if it is desired to fabricate a 6 silicon quantum wire array with a wire period (~) of 9 7 nm, the sample should be heated to obtain 3.3 fold 8 decrease in ~, so that ~ = 9 nm at 850 K corresponds to 9 ~ = 30 nm at room temperature. From Fig. 1E it can be determined (by extrapolation) that for J. = 9 nm at 850 11 K, E = 2 .keV and 8 = 58°. From these values, it can be 12 determined that R = 7 nm, H = 1.98 nm, DF = 0 nm, and 13 therefore DH = 8.98 nm.
In a further example, if it is desired to fabricate a 16 silicon quantum wire array with a wire period (~).of 17 120 nm, from Fig. 1E it can be determined that for ~ _ 18 120 nm, E = 8keV and 8 = 45°. From these values, it can 19 be determined that R = 16 nm, H = 27.6 nm, DF = 146 nm, and therefore DH = 189.6 nm. Alternative parameters can 21 be determined for the same ~; e.g. for ~ = 120 nm, E =
22 5.5keV and 6 = 43°. From these values, it can be -23 determined that R = 12.25 nm, H = 30 nm, DF = 146 nm, 24 and therefore DH = 188.3 nm.
26 Thus, on the basis of a desired period of the quantum 27 wire array ~ in the range 9 nm to 120 nm, the 28 parameters that control the process can be 29 predetermined as shown above.
31 A wide variety of SOI materials can be used for the 32 process; e.g. SOI obtained by SIMOX (Separation by 33 IMplanted OXygen) technology can be used with the 34 required thickness of silicon layer. Other alternatives will be apparent to those skilled in the 36 art, such as SOI prepared with Smart Cut technology, or 1 monocrystalline films of silicon on either quartz or 2 glass wafers.
4 Fig. 1 relates to an example employing SOI made by SIMOX technology. The thickness of the silicon layer 3 6 should be of high uniformity (suitable SIMOX wafers are 7 available from Ibis, USA).
9 Once the SOI material has been selected, the silicon nitride mask layer 1 can be prepared as shown in Fig.-11 1A. The silicon nitride layer 1 is deposited on top of 12 the thin silicon oxide layer 2. The mask window is 13 formed in the silicon nitride layer 1 by means of 14 lithography and plasmochemical etching, the silicon oxide layer 2 acting as a stop layer for the 16 plasmochemical etching. The thin oxide layer 2 within 17 the window area is then removed by wet chemical 18 etching, forming a pendant edge around the periphery of 19 the mask window. The mask layer is sufficiently thick to prevent the formation of any wave-like relief on the 21 surface of the silicon layer 3 outwith the mask window 22 area. The formation of a pendant edge around the mask 23 window is advantageous in obtaining a uniform WOS
24 surrounded by a flat silicon surface around the edge of the mask window.
27 The silicon layer 6 is grounded (earthed) as indicated 28 at 11 in Fig. 1A during the sputtering process so as to 29 prevent charge damage to the array 7 formed by the sputtering process.
32 The mask window is preferably oriented relative to the 33 direction of the ion beam as indicated in Figs. 1A, 1B
34 and 2, such that the ion incidence plane defined by the surface normal and the ion flow direction is oriented 36 parallel to the longer sides of the rectangular mask 1 window. This maximises the advantageous effect of the 2 pendant edge of the mask window.
4 The mask thickness may be selected such that the mask material is removed by the sputtering process, the mask 6 material and the silicon surface within the mask window 7 being sputtered at approximately equal rates.
9 The sputtering process is carried out on the basis of the parameters E, 8 and T which have previously been 11 determined. Sputtering may be carried out in the 12 ultra-high vacuum chamber of surface analysis apparatus 13 (e. g. type PHI 660 from Perkin Elmer, USA). During 14 sputtering, a secondary ion emission signal from the insulator layer 4 of the SOI material is monitored, and 16 sputtering is terminated when this signal exceeds~a 17 predetermined threshold value, indicating that the 18 troughs of the WOS are approaching the silicon- ' 19 insulator border. As shown in Fig. 1C, the threshold value, S, can suitably be defined as the value at which 21 the signal exceeds the average background value B by an 22 amount equal to the peak-to-peak height of the noise 23 signal N (i.e. S = B + N):
A low energy electron gun (not shown) may be used to 26 compensate for ion charging, by electron irradiation of' 27 the sputtered area (as is known in the field of depth 28 profiling of insulators).
These steps result in the formation of the quantum wire 31 array 7 within the area of the mask window. Fig. 1D
32 illustrates the internal structure of the array 7 when 33 fabricated at room temperature, as described above.
34 When fabricated at 850 K, the internal structure of the array 7 differs from that obtained at room temperature.
36 When prepared at 850 K, the present inventors have 1 discovered that the wavelength of the WOS is reduced by 2 a factor of 3.3, as compared with the wavelength 3 obtained with similar process parameters at room 4 temperature. However, the thicknesses of the layers and the slopes of the sides of the waves remain the 6 same as at room temperature. The structure obtained at 7 850 K does not contain the crystalline silicon regions 8 12. The horizontal dimension of the regions of 9 amorphous silicon nitride 8 is shortened by a factor of 3.3 compared with those formed under room temperature 11 conditions, and the regions of silicon oxynitride 10 12 are not separated. In this case, the regions 9 can be 13 considered as quantum wires after annealing, as 14 described below, isolated from one another by the regions 8.
17 Following completion of the sputtering process, the 18 product is annealed in an inert environment, suitabhy 19 at a temperature of 1000°C to 1200°C for a period of at least one hour, followed by high-temperature oxidation.
21 The annealing process results in the regions of mixture 22 of amorphous silicon and silicon nitride inclusions 9 23 being effectively depleted of nitrogen, resulting in 24 the formation of clear cut nitride borders around th.e regions 9. In addition, the regions 9 are converted 26 into crystalline silicon. The high-temperature 27 oxidation step may be similar to oxidation processes 28 employed in the fabrication of gate oxide layers as is 29 well known in the field of semiconductor fabrication.
31 From the foregoing, it will be seen that the silicon 32 quantum wires of the array obtained by means of the 33 present invention can be formed in one of three basic 34 ways. Firstly, when sputtered at room temperature, the sputtered structure contains regions 12 of crystalline 36 silicon which can be regarded as quantum wires, 1 isolated from one another by regions 8. Secondly, if 2 the structure sputtered at room temperature is 3 subsequently annealed, the regions 9 are converted to 4 crystalline silicon and may also be regarded as quantum 5 wires. In this case, the regions 12 also increase in 6 volume, merging with the regions 9, the quantum wires 7 again being mutually isolated by the regions 8.
8 Thirdly, if the array is sputtered at 850 K, the 9 sputtered structure does not contain any crystalline 10 silicon regions 12, subsequent annealing converting the 11 regions 9 to crystalline silicon and thereby forming 12 the quantum wires of the array, isolated from one 13 another by the regions 8.
15 Annealing also expands the lowermost corner portions of 16 the regions 8, improving the isolation of the regions 9 17 in all of the cases described above.
19 From the foregoing description, it will be understood 20 that quantum wire arrays with a wavelength in the range 21 of about 30 to 120 nm can be formed by sputtering at 22 room temperature, and shorter wavelengths down to about 23 9 nm can be obtained by increasing the temperature of 24 the material during sputtering above about 550 K, with minimum wavelengths being obtained at about 8.50 K.
2.6 Depending on the process parameters, the WOS obtained 27 by sputtering may include regions 12 of crystalline 28 silicon, which may provide useful, mutually 'isolated 29 quantum wires. Where the sputtered structure does not itself include such regions 12, quantum wires are 31 formed in the regions 9 by subsequent annealing of the 32 sputtered product, such annealing being preferred 33 whether or not the sputtered product includes the 34 regions 12.
36 Figs. 2 and 3 illustrate the process of fabricating a 1 device (an FET in this example) incorporating the 2 quantum wire array 7 formed by the process described 3 thus far. Fig. 2A illustrates the mask layer 1 4 defining the mask window on the SOI material .prior to sputtering as previously described. Fig. 2B shows the 6 quantum wire array 7 formed in the silicon layer 6, 7 also as previously described.
9 Fig. 2C illustrates a first step in forming a FET
incorporating the quantum wire array 7. The previously 11 described high-temperature oxidising step forms a thin 12 insulating layer 28 on the surface of the sputtered 13 product. Using known lithography techniques, a 14 polysilicon rectangle 30 is deposited on top of the 15. insulator layer, extending across the width of the 16 array 7. The length L of the array 7 may be.greater 17 than the width W of the polysilicon area 30. The area 18 surrounding the polysilicon 30 can then be etched back 19 to SOI insulator layer 4, leaving. Then, by.means of lithography, the ends of the polysilicon area 30 are' 21 etched to leave silicon pads 36 and 38 at either end of 22 the array 7 and to metallize the pads 36 and 38, as 23 seen in Fig. 2D, where numeral 17 indicates array 7 24 after etching, reduced in length from L to W:
26. It will be understood that, following the fabrication 27 of the quantum wire array, devices may be fabricated 28 incorporating the array by means of any of a variety of 29 conventional semiconductor manufacturing technologies.
31 Figs. 2D and 3 illustrate the FET device formed as 32 described above. In Figs. 2D and 3, numeral 32 33 indicates the oxide insulator layer and 34 indicates 34 the polysilicon layer remaining after etching of the corresponding layers 28 and 30 of Fig. 2C. In Fig. 3 36 the layers 32 and 34 are shown partially removed to 1 reveal the underlying quantum wire array 7, for the 2 purposes of illustration only. In Gig. 2D, the layers 3 32 and 34 can be seen to extend to the pads 36 and 38.
The invention allows devices of this type to be made 6 having dimensions smaller than has hitherto been 7 possible and/or with improved repeatability of results 8 and quality of end product.
The invention has been described thus far with 11 particular reference to the formation of quantum wire 12 arrays based on wave ordered structures formed by 13 sputtering. However, the WOS formed by the basic 14 sputtering process may also be used as a mask for ion implantation (e.g. low energy implantation of '.
16 phosphorous ions) into silicon for quantum computer 17 applications. Ion implantation is the principal 18 technique for introducing dopant atoms into 19 semiconductor materials for VLSI applications. Mask.
layers with windows are normally used for the formation 21 of two-dimensional dopant distributions. Ion 22 implantation is usually followed- by annealing for 23 electrical activation of the dopants and for the 24 restoration of the crystal structure of the semiconductor. For example, if a WOS as illustrated in 26 Fig. 1D is formed, then after high temperature 27 annealing the regions 8 may serve as a mask allowing-28 selective ion implantation into the right hand side of 29 the regions 9 (the direction of low-energy ion flow being normal to the surface of the material). Such an 31 ion implantation process would result in a pattern of 32 alternating doped stripes having the same period as the 33 WOS. Using a WOS period of about 10 nm or less, the 34 phosphorous doped stripes formed in this way are sufficiently close to allow interactions of the type 36 required for quantum computer applications. Ion 1 implantation might also be employed as an alternative 2 method of forming quantum wire arrays using the WOS as 3 a mask.
Improvements and modifications may be incorporated 6 without departing from the scope of the invention as 7 defined in the Claims appended hereto.
23 2 keV and 8 = 58°). Smaller values of ~ can be obtained 24 by heating the SOI material above 550K, as shown in Fig. 1F.
27 Accordingly, for a selected value of 7., suitable values 28 of E, 8 and T can be determined. The ion penetration 29 range and the formation depth DF can be calculated from formulae (1) and (2) and from empirical data (3), and 31 the required depth DF of the SOI silicon layer can then 32 be calculated from formula (4) .
34 For example, if it is desired to fabricate a silicon quantum wire array with a wire period (~) of 30 nm, 36 from Fig. 1E it can be determined (by extrapolation) 1 that for ~ = 30 nm, E = 2 keV and B = 58°. From these 2 values, it can be determined that R = 7 nm, H = 6.6 nm, 3 DF = 27.6 nm, and therefore DB = 41.2 nm.
In a further example, if it is desired to fabricate a 6 silicon quantum wire array with a wire period (~) of 9 7 nm, the sample should be heated to obtain 3.3 fold 8 decrease in ~, so that ~ = 9 nm at 850 K corresponds to 9 ~ = 30 nm at room temperature. From Fig. 1E it can be determined (by extrapolation) that for J. = 9 nm at 850 11 K, E = 2 .keV and 8 = 58°. From these values, it can be 12 determined that R = 7 nm, H = 1.98 nm, DF = 0 nm, and 13 therefore DH = 8.98 nm.
In a further example, if it is desired to fabricate a 16 silicon quantum wire array with a wire period (~).of 17 120 nm, from Fig. 1E it can be determined that for ~ _ 18 120 nm, E = 8keV and 8 = 45°. From these values, it can 19 be determined that R = 16 nm, H = 27.6 nm, DF = 146 nm, and therefore DH = 189.6 nm. Alternative parameters can 21 be determined for the same ~; e.g. for ~ = 120 nm, E =
22 5.5keV and 6 = 43°. From these values, it can be -23 determined that R = 12.25 nm, H = 30 nm, DF = 146 nm, 24 and therefore DH = 188.3 nm.
26 Thus, on the basis of a desired period of the quantum 27 wire array ~ in the range 9 nm to 120 nm, the 28 parameters that control the process can be 29 predetermined as shown above.
31 A wide variety of SOI materials can be used for the 32 process; e.g. SOI obtained by SIMOX (Separation by 33 IMplanted OXygen) technology can be used with the 34 required thickness of silicon layer. Other alternatives will be apparent to those skilled in the 36 art, such as SOI prepared with Smart Cut technology, or 1 monocrystalline films of silicon on either quartz or 2 glass wafers.
4 Fig. 1 relates to an example employing SOI made by SIMOX technology. The thickness of the silicon layer 3 6 should be of high uniformity (suitable SIMOX wafers are 7 available from Ibis, USA).
9 Once the SOI material has been selected, the silicon nitride mask layer 1 can be prepared as shown in Fig.-11 1A. The silicon nitride layer 1 is deposited on top of 12 the thin silicon oxide layer 2. The mask window is 13 formed in the silicon nitride layer 1 by means of 14 lithography and plasmochemical etching, the silicon oxide layer 2 acting as a stop layer for the 16 plasmochemical etching. The thin oxide layer 2 within 17 the window area is then removed by wet chemical 18 etching, forming a pendant edge around the periphery of 19 the mask window. The mask layer is sufficiently thick to prevent the formation of any wave-like relief on the 21 surface of the silicon layer 3 outwith the mask window 22 area. The formation of a pendant edge around the mask 23 window is advantageous in obtaining a uniform WOS
24 surrounded by a flat silicon surface around the edge of the mask window.
27 The silicon layer 6 is grounded (earthed) as indicated 28 at 11 in Fig. 1A during the sputtering process so as to 29 prevent charge damage to the array 7 formed by the sputtering process.
32 The mask window is preferably oriented relative to the 33 direction of the ion beam as indicated in Figs. 1A, 1B
34 and 2, such that the ion incidence plane defined by the surface normal and the ion flow direction is oriented 36 parallel to the longer sides of the rectangular mask 1 window. This maximises the advantageous effect of the 2 pendant edge of the mask window.
4 The mask thickness may be selected such that the mask material is removed by the sputtering process, the mask 6 material and the silicon surface within the mask window 7 being sputtered at approximately equal rates.
9 The sputtering process is carried out on the basis of the parameters E, 8 and T which have previously been 11 determined. Sputtering may be carried out in the 12 ultra-high vacuum chamber of surface analysis apparatus 13 (e. g. type PHI 660 from Perkin Elmer, USA). During 14 sputtering, a secondary ion emission signal from the insulator layer 4 of the SOI material is monitored, and 16 sputtering is terminated when this signal exceeds~a 17 predetermined threshold value, indicating that the 18 troughs of the WOS are approaching the silicon- ' 19 insulator border. As shown in Fig. 1C, the threshold value, S, can suitably be defined as the value at which 21 the signal exceeds the average background value B by an 22 amount equal to the peak-to-peak height of the noise 23 signal N (i.e. S = B + N):
A low energy electron gun (not shown) may be used to 26 compensate for ion charging, by electron irradiation of' 27 the sputtered area (as is known in the field of depth 28 profiling of insulators).
These steps result in the formation of the quantum wire 31 array 7 within the area of the mask window. Fig. 1D
32 illustrates the internal structure of the array 7 when 33 fabricated at room temperature, as described above.
34 When fabricated at 850 K, the internal structure of the array 7 differs from that obtained at room temperature.
36 When prepared at 850 K, the present inventors have 1 discovered that the wavelength of the WOS is reduced by 2 a factor of 3.3, as compared with the wavelength 3 obtained with similar process parameters at room 4 temperature. However, the thicknesses of the layers and the slopes of the sides of the waves remain the 6 same as at room temperature. The structure obtained at 7 850 K does not contain the crystalline silicon regions 8 12. The horizontal dimension of the regions of 9 amorphous silicon nitride 8 is shortened by a factor of 3.3 compared with those formed under room temperature 11 conditions, and the regions of silicon oxynitride 10 12 are not separated. In this case, the regions 9 can be 13 considered as quantum wires after annealing, as 14 described below, isolated from one another by the regions 8.
17 Following completion of the sputtering process, the 18 product is annealed in an inert environment, suitabhy 19 at a temperature of 1000°C to 1200°C for a period of at least one hour, followed by high-temperature oxidation.
21 The annealing process results in the regions of mixture 22 of amorphous silicon and silicon nitride inclusions 9 23 being effectively depleted of nitrogen, resulting in 24 the formation of clear cut nitride borders around th.e regions 9. In addition, the regions 9 are converted 26 into crystalline silicon. The high-temperature 27 oxidation step may be similar to oxidation processes 28 employed in the fabrication of gate oxide layers as is 29 well known in the field of semiconductor fabrication.
31 From the foregoing, it will be seen that the silicon 32 quantum wires of the array obtained by means of the 33 present invention can be formed in one of three basic 34 ways. Firstly, when sputtered at room temperature, the sputtered structure contains regions 12 of crystalline 36 silicon which can be regarded as quantum wires, 1 isolated from one another by regions 8. Secondly, if 2 the structure sputtered at room temperature is 3 subsequently annealed, the regions 9 are converted to 4 crystalline silicon and may also be regarded as quantum 5 wires. In this case, the regions 12 also increase in 6 volume, merging with the regions 9, the quantum wires 7 again being mutually isolated by the regions 8.
8 Thirdly, if the array is sputtered at 850 K, the 9 sputtered structure does not contain any crystalline 10 silicon regions 12, subsequent annealing converting the 11 regions 9 to crystalline silicon and thereby forming 12 the quantum wires of the array, isolated from one 13 another by the regions 8.
15 Annealing also expands the lowermost corner portions of 16 the regions 8, improving the isolation of the regions 9 17 in all of the cases described above.
19 From the foregoing description, it will be understood 20 that quantum wire arrays with a wavelength in the range 21 of about 30 to 120 nm can be formed by sputtering at 22 room temperature, and shorter wavelengths down to about 23 9 nm can be obtained by increasing the temperature of 24 the material during sputtering above about 550 K, with minimum wavelengths being obtained at about 8.50 K.
2.6 Depending on the process parameters, the WOS obtained 27 by sputtering may include regions 12 of crystalline 28 silicon, which may provide useful, mutually 'isolated 29 quantum wires. Where the sputtered structure does not itself include such regions 12, quantum wires are 31 formed in the regions 9 by subsequent annealing of the 32 sputtered product, such annealing being preferred 33 whether or not the sputtered product includes the 34 regions 12.
36 Figs. 2 and 3 illustrate the process of fabricating a 1 device (an FET in this example) incorporating the 2 quantum wire array 7 formed by the process described 3 thus far. Fig. 2A illustrates the mask layer 1 4 defining the mask window on the SOI material .prior to sputtering as previously described. Fig. 2B shows the 6 quantum wire array 7 formed in the silicon layer 6, 7 also as previously described.
9 Fig. 2C illustrates a first step in forming a FET
incorporating the quantum wire array 7. The previously 11 described high-temperature oxidising step forms a thin 12 insulating layer 28 on the surface of the sputtered 13 product. Using known lithography techniques, a 14 polysilicon rectangle 30 is deposited on top of the 15. insulator layer, extending across the width of the 16 array 7. The length L of the array 7 may be.greater 17 than the width W of the polysilicon area 30. The area 18 surrounding the polysilicon 30 can then be etched back 19 to SOI insulator layer 4, leaving. Then, by.means of lithography, the ends of the polysilicon area 30 are' 21 etched to leave silicon pads 36 and 38 at either end of 22 the array 7 and to metallize the pads 36 and 38, as 23 seen in Fig. 2D, where numeral 17 indicates array 7 24 after etching, reduced in length from L to W:
26. It will be understood that, following the fabrication 27 of the quantum wire array, devices may be fabricated 28 incorporating the array by means of any of a variety of 29 conventional semiconductor manufacturing technologies.
31 Figs. 2D and 3 illustrate the FET device formed as 32 described above. In Figs. 2D and 3, numeral 32 33 indicates the oxide insulator layer and 34 indicates 34 the polysilicon layer remaining after etching of the corresponding layers 28 and 30 of Fig. 2C. In Fig. 3 36 the layers 32 and 34 are shown partially removed to 1 reveal the underlying quantum wire array 7, for the 2 purposes of illustration only. In Gig. 2D, the layers 3 32 and 34 can be seen to extend to the pads 36 and 38.
The invention allows devices of this type to be made 6 having dimensions smaller than has hitherto been 7 possible and/or with improved repeatability of results 8 and quality of end product.
The invention has been described thus far with 11 particular reference to the formation of quantum wire 12 arrays based on wave ordered structures formed by 13 sputtering. However, the WOS formed by the basic 14 sputtering process may also be used as a mask for ion implantation (e.g. low energy implantation of '.
16 phosphorous ions) into silicon for quantum computer 17 applications. Ion implantation is the principal 18 technique for introducing dopant atoms into 19 semiconductor materials for VLSI applications. Mask.
layers with windows are normally used for the formation 21 of two-dimensional dopant distributions. Ion 22 implantation is usually followed- by annealing for 23 electrical activation of the dopants and for the 24 restoration of the crystal structure of the semiconductor. For example, if a WOS as illustrated in 26 Fig. 1D is formed, then after high temperature 27 annealing the regions 8 may serve as a mask allowing-28 selective ion implantation into the right hand side of 29 the regions 9 (the direction of low-energy ion flow being normal to the surface of the material). Such an 31 ion implantation process would result in a pattern of 32 alternating doped stripes having the same period as the 33 WOS. Using a WOS period of about 10 nm or less, the 34 phosphorous doped stripes formed in this way are sufficiently close to allow interactions of the type 36 required for quantum computer applications. Ion 1 implantation might also be employed as an alternative 2 method of forming quantum wire arrays using the WOS as 3 a mask.
Improvements and modifications may be incorporated 6 without departing from the scope of the invention as 7 defined in the Claims appended hereto.
Claims (12)
1. A method of forming a silicon nanostructure, comprising:
sputtering a silicon surface by a uniform flow of nitrogen molecular ions in an ultra-high vacuum so as to form a periodic wave-like relief, the wave front of said relief being in the direction of the ion incidence plane; further including the following steps:
prior to sputtering:
selecting a desired wavelength of the periodic wave-like relief in the range 9 nm to 120 nm;
determining the ion energy, the ion incidence angle to the surface of said material, the temperature of said silicon layer, the formation depth of said wave-like relief, the height of said wave-like relief and the ion penetration range into silicon, all on the basis of said selected wavelength.
sputtering a silicon surface by a uniform flow of nitrogen molecular ions in an ultra-high vacuum so as to form a periodic wave-like relief, the wave front of said relief being in the direction of the ion incidence plane; further including the following steps:
prior to sputtering:
selecting a desired wavelength of the periodic wave-like relief in the range 9 nm to 120 nm;
determining the ion energy, the ion incidence angle to the surface of said material, the temperature of said silicon layer, the formation depth of said wave-like relief, the height of said wave-like relief and the ion penetration range into silicon, all on the basis of said selected wavelength.
2. A method as claimed in Claim 1, wherein said ion energy, said ion incidence angle, said temperature of said silicon, said formation depth and said height of said wave-like relief are determined on the basis of previously obtained empirical data relating said ion energy, said ion incidence angle, said temperature of said silicon, said formation depth and said height of said wave-like relief to the wavelength of said periodic wave-like relief, and wherein said ion penetration range is determined from said ion energy.
3. A method as claimed in Claim 1, further including the step, prior to sputtering, of positioning a silicon nitride mask containing a window with pendant edges on said silicon surface over the sputter area, and sputtering said silicon surface through said window.
4. A method as claimed in Claim 1, further including the step, prior to sputtering, of removing any impurities from the surface of the said silicon layer on which said wave-like relief is to be formed.
5. A method as claimed in Claim 1, further including, subsequent to sputtering:
annealing the material with said relief in an inert environment.
annealing the material with said relief in an inert environment.
6. A method as claimed in Claim 1, wherein the material is annealed at a temperature between 1000 and 1200°C for a period of at least one hour.
7. A method as claimed in any preceding Claim, wherein said silicon nanostructure comprises a silicon quantum wire array and said silicon comprises a silicon layer of a silicon-on-insulator material, and further including:
selecting the thickness of said silicon layer to be greater than the sum of said formation depth of said wave-like relief, said height of said wave-like relief, and said ion penetration range.
selecting the thickness of said silicon layer to be greater than the sum of said formation depth of said wave-like relief, said height of said wave-like relief, and said ion penetration range.
8. A method as claimed in Claim 7, further including:
during sputtering:
detecting a secondary ion emission signal from the insulator layer of said silicon-on-insulator material;
and terminating sputtering when the value of the detected signal reaches a predetermined threshold value;
during sputtering:
detecting a secondary ion emission signal from the insulator layer of said silicon-on-insulator material;
and terminating sputtering when the value of the detected signal reaches a predetermined threshold value;
9. A method as claimed in Claim 8, wherein said threshold value of said secondary ion emission signal is that value at which the signal exceeds an average background value by an amount equal to the peak-to-peak height of a noise component of the signal.
10. An optoelectronic device including a quantum wire array formed by the method of Claim 7.
11. An electronic device including a quantum wire array formed by the method of Claim 7.
12. A device as claimed in Claim 11, comprising silicon pads connected by said silicon quantum wire array, an insulator layer positioned on said quantum wire array, and an electrode positioned on said insulator.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU99124768 | 1999-11-25 | ||
| RU99124768/28A RU2173003C2 (en) | 1999-11-25 | 1999-11-25 | Method for producing silicon nanostructure, lattice of silicon quantum conducting tunnels, and devices built around them |
| PCT/IB2000/001397 WO2001039259A1 (en) | 1999-11-25 | 2000-10-02 | Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon |
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| CA2392307A1 true CA2392307A1 (en) | 2001-05-31 |
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| EP (1) | EP1104011A1 (en) |
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| RU2141699C1 (en) | 1997-09-30 | 1999-11-20 | Закрытое акционерное общество Центр "Анализ Веществ" | Process of formation of solid nanostructures |
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